1 /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2 /*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 */
21
22 /*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32 #define DRV_NAME "3c59x"
33
34
35
36 /* A few values that may be tweaked. */
37 /* Keep the ring sizes a power of two for efficiency. */
38 #define TX_RING_SIZE 16
39 #define RX_RING_SIZE 32
40 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42 /* "Knobs" that adjust features and parameters. */
43 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45 #ifndef __arm__
46 static int rx_copybreak = 200;
47 #else
48 /* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50 static int rx_copybreak = 1513;
51 #endif
52 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53 static const int mtu = 1500;
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static int max_interrupt_work = 32;
56 /* Tx timeout interval (millisecs) */
57 static int watchdog = 5000;
58
59 /* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63 #define tx_interrupt_mitigation 1
64
65 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66 #define vortex_debug debug
67 #ifdef VORTEX_DEBUG
68 static int vortex_debug = VORTEX_DEBUG;
69 #else
70 static int vortex_debug = 1;
71 #endif
72
73 #include <linux/module.h>
74 #include <linux/kernel.h>
75 #include <linux/string.h>
76 #include <linux/timer.h>
77 #include <linux/errno.h>
78 #include <linux/in.h>
79 #include <linux/ioport.h>
80 #include <linux/slab.h>
81 #include <linux/interrupt.h>
82 #include <linux/pci.h>
83 #include <linux/mii.h>
84 #include <linux/init.h>
85 #include <linux/netdevice.h>
86 #include <linux/etherdevice.h>
87 #include <linux/skbuff.h>
88 #include <linux/ethtool.h>
89 #include <linux/highmem.h>
90 #include <linux/eisa.h>
91 #include <linux/bitops.h>
92 #include <linux/jiffies.h>
93 #include <asm/irq.h> /* For NR_IRQS only. */
94 #include <asm/io.h>
95 #include <asm/uaccess.h>
96
97 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100 #define RUN_AT(x) (jiffies + (x))
101
102 #include <linux/delay.h>
103
104
105 static char version[] __devinitdata =
106 DRV_NAME ": Donald Becker and others.\n";
107
108 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
109 MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
110 MODULE_LICENSE("GPL");
111
112
113 /* Operational parameter that usually are not changed. */
114
115 /* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119 #define VORTEX_TOTAL_SIZE 0x20
120 #define BOOMERANG_TOTAL_SIZE 0x40
121
122 /* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125 static char mii_preamble_required;
126
127 #define PFX DRV_NAME ": "
128
129
130
131 /*
132 Theory of Operation
133
134 I. Board Compatibility
135
136 This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137 XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138 versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141 The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142 with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145 II. Board-specific settings
146
147 PCI bus devices are configured by the system at boot time, so no jumpers
148 need to be set on the board. The system BIOS should be set to assign the
149 PCI INTA signal to an otherwise unused system IRQ line.
150
151 The EEPROM settings for media type and forced-full-duplex are observed.
152 The EEPROM media type should be left at the default "autoselect" unless using
153 10base2 or AUI connections which cannot be reliably detected.
154
155 III. Driver operation
156
157 The 3c59x series use an interface that's very similar to the previous 3c5x9
158 series. The primary interface is two programmed-I/O FIFOs, with an
159 alternate single-contiguous-region bus-master transfer (see next).
160
161 The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162 lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163 DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164 programmed-I/O interface that has been removed in 'B' and subsequent board
165 revisions.
166
167 One extension that is advertised in a very large font is that the adapters
168 are capable of being bus masters. On the Vortex chip this capability was
169 only for a single contiguous region making it far less useful than the full
170 bus master capability. There is a significant performance impact of taking
171 an extra interrupt or polling for the completion of each transfer, as well
172 as difficulty sharing the single transfer engine between the transmit and
173 receive threads. Using DMA transfers is a win only with large blocks or
174 with the flawed versions of the Intel Orion motherboard PCI controller.
175
176 The Boomerang chip's full-bus-master interface is useful, and has the
177 currently-unused advantages over other similar chips that queued transmit
178 packets may be reordered and receive buffer groups are associated with a
179 single frame.
180
181 With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182 Rather than a fixed intermediate receive buffer, this scheme allocates
183 full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184 the copying breakpoint: it is chosen to trade-off the memory wasted by
185 passing the full-sized skbuff to the queue layer for all frames vs. the
186 copying cost of copying a frame to a correctly-sized skbuff.
187
188 IIIC. Synchronization
189 The driver runs as two independent, single-threaded flows of control. One
190 is the send-packet routine, which enforces single-threaded use by the
191 dev->tbusy flag. The other thread is the interrupt handler, which is single
192 threaded by the hardware and other software.
193
194 IV. Notes
195
196 Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
197 3c590, 3c595, and 3c900 boards.
198 The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199 the EISA version is called "Demon". According to Terry these names come
200 from rides at the local amusement park.
201
202 The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203 This driver only supports ethernet packets because of the skbuff allocation
204 limit of 4K.
205 */
206
207 /* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209 */
210 enum pci_flags_bit {
211 PCI_USES_MASTER=4,
212 };
213
214 enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221 enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
238 CH_3C905B_1,
239
240 CH_3C905B_2,
241 CH_3C905B_FX,
242 CH_3C905C,
243 CH_3C9202,
244 CH_3C980,
245 CH_3C9805,
246
247 CH_3CSOHO100_TX,
248 CH_3C555,
249 CH_3C556,
250 CH_3C556B,
251 CH_3C575,
252
253 CH_3C575_1,
254 CH_3CCFE575,
255 CH_3CCFE575CT,
256 CH_3CCFE656,
257 CH_3CCFEM656,
258
259 CH_3CCFEM656_1,
260 CH_3C450,
261 CH_3C920,
262 CH_3C982A,
263 CH_3C982B,
264
265 CH_905BT4,
266 CH_920B_EMB_WNM,
267 };
268
269
270 /* note: this array directly indexed by above enums, and MUST
271 * be kept in sync with both the enums above, and the PCI device
272 * table below
273 */
274 static struct vortex_chip_info {
275 const char *name;
276 int flags;
277 int drv_flags;
278 int io_size;
279 } vortex_info_tbl[] __devinitdata = {
280 {"3c590 Vortex 10Mbps",
281 PCI_USES_MASTER, IS_VORTEX, 32, },
282 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
283 PCI_USES_MASTER, IS_VORTEX, 32, },
284 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
285 PCI_USES_MASTER, IS_VORTEX, 32, },
286 {"3c595 Vortex 100baseTx",
287 PCI_USES_MASTER, IS_VORTEX, 32, },
288 {"3c595 Vortex 100baseT4",
289 PCI_USES_MASTER, IS_VORTEX, 32, },
290
291 {"3c595 Vortex 100base-MII",
292 PCI_USES_MASTER, IS_VORTEX, 32, },
293 {"3c900 Boomerang 10baseT",
294 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
295 {"3c900 Boomerang 10Mbps Combo",
296 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
297 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
298 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
299 {"3c900 Cyclone 10Mbps Combo",
300 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
301
302 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
303 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
304 {"3c900B-FL Cyclone 10base-FL",
305 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
306 {"3c905 Boomerang 100baseTx",
307 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
308 {"3c905 Boomerang 100baseT4",
309 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
310 {"3c905B Cyclone 100baseTx",
311 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
312
313 {"3c905B Cyclone 10/100/BNC",
314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
315 {"3c905B-FX Cyclone 100baseFx",
316 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
317 {"3c905C Tornado",
318 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
319 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
320 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
321 {"3c980 Cyclone",
322 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
323
324 {"3c980C Python-T",
325 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
326 {"3cSOHO100-TX Hurricane",
327 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
328 {"3c555 Laptop Hurricane",
329 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
330 {"3c556 Laptop Tornado",
331 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
332 HAS_HWCKSM, 128, },
333 {"3c556B Laptop Hurricane",
334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
335 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
336
337 {"3c575 [Megahertz] 10/100 LAN CardBus",
338 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
339 {"3c575 Boomerang CardBus",
340 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
341 {"3CCFE575BT Cyclone CardBus",
342 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
343 INVERT_LED_PWR|HAS_HWCKSM, 128, },
344 {"3CCFE575CT Tornado CardBus",
345 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
346 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
347 {"3CCFE656 Cyclone CardBus",
348 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
349 INVERT_LED_PWR|HAS_HWCKSM, 128, },
350
351 {"3CCFEM656B Cyclone+Winmodem CardBus",
352 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
353 INVERT_LED_PWR|HAS_HWCKSM, 128, },
354 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
355 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
356 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
357 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
359 {"3c920 Tornado",
360 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
361 {"3c982 Hydra Dual Port A",
362 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
363
364 {"3c982 Hydra Dual Port B",
365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
366 {"3c905B-T4",
367 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
368 {"3c920B-EMB-WNM Tornado",
369 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
370
371 {NULL,}, /* NULL terminated list. */
372 };
373
374
375 static struct pci_device_id vortex_pci_tbl[] = {
376 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
377 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
378 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
379 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
380 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
381
382 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
383 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
384 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
385 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
386 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
387
388 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
389 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
390 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
391 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
392 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
393
394 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
395 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
396 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
397 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
398 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
399 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
400
401 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
402 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
403 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
404 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
405 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
406
407 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
408 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
409 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
410 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
411 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
412
413 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
414 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
415 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
416 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
417 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
418
419 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
420 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
421
422 {0,} /* 0 terminated list. */
423 };
424 MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
425
426
427 /* Operational definitions.
428 These are not used by other compilation units and thus are not
429 exported in a ".h" file.
430
431 First the windows. There are eight register windows, with the command
432 and status registers available in each.
433 */
434 #define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
435 #define EL3_CMD 0x0e
436 #define EL3_STATUS 0x0e
437
438 /* The top five bits written to EL3_CMD are a command, the lower
439 11 bits are the parameter, if applicable.
440 Note that 11 parameters bits was fine for ethernet, but the new chip
441 can handle FDDI length frames (~4500 octets) and now parameters count
442 32-bit 'Dwords' rather than octets. */
443
444 enum vortex_cmd {
445 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
446 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
447 UpStall = 6<<11, UpUnstall = (6<<11)+1,
448 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
449 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
450 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
451 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
452 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
453 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
454 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
455
456 /* The SetRxFilter command accepts the following classes: */
457 enum RxFilter {
458 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
459
460 /* Bits in the general status register. */
461 enum vortex_status {
462 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
463 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
464 IntReq = 0x0040, StatsFull = 0x0080,
465 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
466 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
467 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
468 };
469
470 /* Register window 1 offsets, the window used in normal operation.
471 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
472 enum Window1 {
473 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
474 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
475 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
476 };
477 enum Window0 {
478 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
479 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
480 IntrStatus=0x0E, /* Valid in all windows. */
481 };
482 enum Win0_EEPROM_bits {
483 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
484 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
485 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
486 };
487 /* EEPROM locations. */
488 enum eeprom_offset {
489 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
490 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
491 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
492 DriverTune=13, Checksum=15};
493
494 enum Window2 { /* Window 2. */
495 Wn2_ResetOptions=12,
496 };
497 enum Window3 { /* Window 3: MAC/config bits. */
498 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
499 };
500
501 #define BFEXT(value, offset, bitcount) \
502 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
503
504 #define BFINS(lhs, rhs, offset, bitcount) \
505 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
506 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
507
508 #define RAM_SIZE(v) BFEXT(v, 0, 3)
509 #define RAM_WIDTH(v) BFEXT(v, 3, 1)
510 #define RAM_SPEED(v) BFEXT(v, 4, 2)
511 #define ROM_SIZE(v) BFEXT(v, 6, 2)
512 #define RAM_SPLIT(v) BFEXT(v, 16, 2)
513 #define XCVR(v) BFEXT(v, 20, 4)
514 #define AUTOSELECT(v) BFEXT(v, 24, 1)
515
516 enum Window4 { /* Window 4: Xcvr/media bits. */
517 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
518 };
519 enum Win4_Media_bits {
520 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
521 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
522 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
523 Media_LnkBeat = 0x0800,
524 };
525 enum Window7 { /* Window 7: Bus Master control. */
526 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
527 Wn7_MasterStatus = 12,
528 };
529 /* Boomerang bus master control registers. */
530 enum MasterCtrl {
531 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
532 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
533 };
534
535 /* The Rx and Tx descriptor lists.
536 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
537 alignment contraint on tx_ring[] and rx_ring[]. */
538 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
539 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
540 struct boom_rx_desc {
541 __le32 next; /* Last entry points to 0. */
542 __le32 status;
543 __le32 addr; /* Up to 63 addr/len pairs possible. */
544 __le32 length; /* Set LAST_FRAG to indicate last pair. */
545 };
546 /* Values for the Rx status entry. */
547 enum rx_desc_status {
548 RxDComplete=0x00008000, RxDError=0x4000,
549 /* See boomerang_rx() for actual error bits */
550 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
551 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
552 };
553
554 #ifdef MAX_SKB_FRAGS
555 #define DO_ZEROCOPY 1
556 #else
557 #define DO_ZEROCOPY 0
558 #endif
559
560 struct boom_tx_desc {
561 __le32 next; /* Last entry points to 0. */
562 __le32 status; /* bits 0:12 length, others see below. */
563 #if DO_ZEROCOPY
564 struct {
565 __le32 addr;
566 __le32 length;
567 } frag[1+MAX_SKB_FRAGS];
568 #else
569 __le32 addr;
570 __le32 length;
571 #endif
572 };
573
574 /* Values for the Tx status entry. */
575 enum tx_desc_status {
576 CRCDisable=0x2000, TxDComplete=0x8000,
577 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
578 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
579 };
580
581 /* Chip features we care about in vp->capabilities, read from the EEPROM. */
582 enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
583
584 struct vortex_extra_stats {
585 unsigned long tx_deferred;
586 unsigned long tx_max_collisions;
587 unsigned long tx_multiple_collisions;
588 unsigned long tx_single_collisions;
589 unsigned long rx_bad_ssd;
590 };
591
592 struct vortex_private {
593 /* The Rx and Tx rings should be quad-word-aligned. */
594 struct boom_rx_desc* rx_ring;
595 struct boom_tx_desc* tx_ring;
596 dma_addr_t rx_ring_dma;
597 dma_addr_t tx_ring_dma;
598 /* The addresses of transmit- and receive-in-place skbuffs. */
599 struct sk_buff* rx_skbuff[RX_RING_SIZE];
600 struct sk_buff* tx_skbuff[TX_RING_SIZE];
601 unsigned int cur_rx, cur_tx; /* The next free ring entry */
602 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
603 struct net_device_stats stats; /* Generic stats */
604 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
605 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
606 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
607
608 /* PCI configuration space information. */
609 struct device *gendev;
610 void __iomem *ioaddr; /* IO address space */
611 void __iomem *cb_fn_base; /* CardBus function status addr space. */
612
613 /* Some values here only for performance evaluation and path-coverage */
614 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
615 int card_idx;
616
617 /* The remainder are related to chip state, mostly media selection. */
618 struct timer_list timer; /* Media selection timer. */
619 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
620 int options; /* User-settable misc. driver options. */
621 unsigned int media_override:4, /* Passed-in media type. */
622 default_media:4, /* Read from the EEPROM/Wn3_Config. */
623 full_duplex:1, autoselect:1,
624 bus_master:1, /* Vortex can only do a fragment bus-m. */
625 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
626 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
627 partner_flow_ctrl:1, /* Partner supports flow control */
628 has_nway:1,
629 enable_wol:1, /* Wake-on-LAN is enabled */
630 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
631 open:1,
632 medialock:1,
633 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
634 large_frames:1; /* accept large frames */
635 int drv_flags;
636 u16 status_enable;
637 u16 intr_enable;
638 u16 available_media; /* From Wn3_Options. */
639 u16 capabilities, info1, info2; /* Various, from EEPROM. */
640 u16 advertising; /* NWay media advertisement */
641 unsigned char phys[2]; /* MII device addresses. */
642 u16 deferred; /* Resend these interrupts when we
643 * bale from the ISR */
644 u16 io_size; /* Size of PCI region (for release_region) */
645 spinlock_t lock; /* Serialise access to device & its vortex_private */
646 struct mii_if_info mii; /* MII lib hooks/info */
647 };
648
649 #ifdef CONFIG_PCI
650 #define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
651 #else
652 #define DEVICE_PCI(dev) NULL
653 #endif
654
655 #define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
656
657 #ifdef CONFIG_EISA
658 #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
659 #else
660 #define DEVICE_EISA(dev) NULL
661 #endif
662
663 #define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
664
665 /* The action to take with a media selection timer tick.
666 Note that we deviate from the 3Com order by checking 10base2 before AUI.
667 */
668 enum xcvr_types {
669 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
670 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
671 };
672
673 static const struct media_table {
674 char *name;
675 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
676 mask:8, /* The transceiver-present bit in Wn3_Config.*/
677 next:8; /* The media type to try next. */
678 int wait; /* Time before we check media status. */
679 } media_tbl[] = {
680 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
681 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
682 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
683 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
684 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
685 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
686 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
687 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
688 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
689 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
690 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
691 };
692
693 static struct {
694 const char str[ETH_GSTRING_LEN];
695 } ethtool_stats_keys[] = {
696 { "tx_deferred" },
697 { "tx_max_collisions" },
698 { "tx_multiple_collisions" },
699 { "tx_single_collisions" },
700 { "rx_bad_ssd" },
701 };
702
703 /* number of ETHTOOL_GSTATS u64's */
704 #define VORTEX_NUM_STATS 5
705
706 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
707 int chip_idx, int card_idx);
708 static int vortex_up(struct net_device *dev);
709 static void vortex_down(struct net_device *dev, int final);
710 static int vortex_open(struct net_device *dev);
711 static void mdio_sync(void __iomem *ioaddr, int bits);
712 static int mdio_read(struct net_device *dev, int phy_id, int location);
713 static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
714 static void vortex_timer(unsigned long arg);
715 static void rx_oom_timer(unsigned long arg);
716 static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
717 static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
718 static int vortex_rx(struct net_device *dev);
719 static int boomerang_rx(struct net_device *dev);
720 static irqreturn_t vortex_interrupt(int irq, void *dev_id);
721 static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
722 static int vortex_close(struct net_device *dev);
723 static void dump_tx_ring(struct net_device *dev);
724 static void update_stats(void __iomem *ioaddr, struct net_device *dev);
725 static struct net_device_stats *vortex_get_stats(struct net_device *dev);
726 static void set_rx_mode(struct net_device *dev);
727 #ifdef CONFIG_PCI
728 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
729 #endif
730 static void vortex_tx_timeout(struct net_device *dev);
731 static void acpi_set_WOL(struct net_device *dev);
732 static const struct ethtool_ops vortex_ethtool_ops;
733 static void set_8021q_mode(struct net_device *dev, int enable);
734
735 /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
736 /* Option count limit only -- unlimited interfaces are supported. */
737 #define MAX_UNITS 8
738 static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
739 static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
740 static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
741 static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
742 static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
743 static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
744 static int global_options = -1;
745 static int global_full_duplex = -1;
746 static int global_enable_wol = -1;
747 static int global_use_mmio = -1;
748
749 /* Variables to work-around the Compaq PCI BIOS32 problem. */
750 static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
751 static struct net_device *compaq_net_device;
752
753 static int vortex_cards_found;
754
755 module_param(debug, int, 0);
756 module_param(global_options, int, 0);
757 module_param_array(options, int, NULL, 0);
758 module_param(global_full_duplex, int, 0);
759 module_param_array(full_duplex, int, NULL, 0);
760 module_param_array(hw_checksums, int, NULL, 0);
761 module_param_array(flow_ctrl, int, NULL, 0);
762 module_param(global_enable_wol, int, 0);
763 module_param_array(enable_wol, int, NULL, 0);
764 module_param(rx_copybreak, int, 0);
765 module_param(max_interrupt_work, int, 0);
766 module_param(compaq_ioaddr, int, 0);
767 module_param(compaq_irq, int, 0);
768 module_param(compaq_device_id, int, 0);
769 module_param(watchdog, int, 0);
770 module_param(global_use_mmio, int, 0);
771 module_param_array(use_mmio, int, NULL, 0);
772 MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
773 MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
774 MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
775 MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
776 MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
777 MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
778 MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
779 MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
780 MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
781 MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
782 MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
783 MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
784 MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
785 MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
786 MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
787 MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
788 MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
789
790 #ifdef CONFIG_NET_POLL_CONTROLLER
791 static void poll_vortex(struct net_device *dev)
792 {
793 struct vortex_private *vp = netdev_priv(dev);
794 unsigned long flags;
795 local_irq_save_nort(flags);
796 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
797 local_irq_restore_nort(flags);
798 }
799 #endif
800
801 #ifdef CONFIG_PM
802
803 static int vortex_suspend(struct pci_dev *pdev, pm_message_t state)
804 {
805 struct net_device *dev = pci_get_drvdata(pdev);
806
807 if (dev && dev->priv) {
808 if (netif_running(dev)) {
809 netif_device_detach(dev);
810 vortex_down(dev, 1);
811 }
812 pci_save_state(pdev);
813 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
814 free_irq(dev->irq, dev);
815 pci_disable_device(pdev);
816 pci_set_power_state(pdev, pci_choose_state(pdev, state));
817 }
818 return 0;
819 }
820
821 static int vortex_resume(struct pci_dev *pdev)
822 {
823 struct net_device *dev = pci_get_drvdata(pdev);
824 struct vortex_private *vp = netdev_priv(dev);
825 int err;
826
827 if (dev && vp) {
828 pci_set_power_state(pdev, PCI_D0);
829 pci_restore_state(pdev);
830 err = pci_enable_device(pdev);
831 if (err) {
832 printk(KERN_WARNING "%s: Could not enable device \n",
833 dev->name);
834 return err;
835 }
836 pci_set_master(pdev);
837 if (request_irq(dev->irq, vp->full_bus_master_rx ?
838 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev)) {
839 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
840 pci_disable_device(pdev);
841 return -EBUSY;
842 }
843 if (netif_running(dev)) {
844 err = vortex_up(dev);
845 if (err)
846 return err;
847 else
848 netif_device_attach(dev);
849 }
850 }
851 return 0;
852 }
853
854 #endif /* CONFIG_PM */
855
856 #ifdef CONFIG_EISA
857 static struct eisa_device_id vortex_eisa_ids[] = {
858 { "TCM5920", CH_3C592 },
859 { "TCM5970", CH_3C597 },
860 { "" }
861 };
862 MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
863
864 static int __init vortex_eisa_probe(struct device *device)
865 {
866 void __iomem *ioaddr;
867 struct eisa_device *edev;
868
869 edev = to_eisa_device(device);
870
871 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
872 return -EBUSY;
873
874 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
875
876 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
877 edev->id.driver_data, vortex_cards_found)) {
878 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
879 return -ENODEV;
880 }
881
882 vortex_cards_found++;
883
884 return 0;
885 }
886
887 static int __devexit vortex_eisa_remove(struct device *device)
888 {
889 struct eisa_device *edev;
890 struct net_device *dev;
891 struct vortex_private *vp;
892 void __iomem *ioaddr;
893
894 edev = to_eisa_device(device);
895 dev = eisa_get_drvdata(edev);
896
897 if (!dev) {
898 printk("vortex_eisa_remove called for Compaq device!\n");
899 BUG();
900 }
901
902 vp = netdev_priv(dev);
903 ioaddr = vp->ioaddr;
904
905 unregister_netdev(dev);
906 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
907 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
908
909 free_netdev(dev);
910 return 0;
911 }
912
913 static struct eisa_driver vortex_eisa_driver = {
914 .id_table = vortex_eisa_ids,
915 .driver = {
916 .name = "3c59x",
917 .probe = vortex_eisa_probe,
918 .remove = __devexit_p(vortex_eisa_remove)
919 }
920 };
921
922 #endif /* CONFIG_EISA */
923
924 /* returns count found (>= 0), or negative on error */
925 static int __init vortex_eisa_init(void)
926 {
927 int eisa_found = 0;
928 int orig_cards_found = vortex_cards_found;
929
930 #ifdef CONFIG_EISA
931 int err;
932
933 err = eisa_driver_register (&vortex_eisa_driver);
934 if (!err) {
935 /*
936 * Because of the way EISA bus is probed, we cannot assume
937 * any device have been found when we exit from
938 * eisa_driver_register (the bus root driver may not be
939 * initialized yet). So we blindly assume something was
940 * found, and let the sysfs magic happend...
941 */
942 eisa_found = 1;
943 }
944 #endif
945
946 /* Special code to work-around the Compaq PCI BIOS32 problem. */
947 if (compaq_ioaddr) {
948 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
949 compaq_irq, compaq_device_id, vortex_cards_found++);
950 }
951
952 return vortex_cards_found - orig_cards_found + eisa_found;
953 }
954
955 /* returns count (>= 0), or negative on error */
956 static int __devinit vortex_init_one(struct pci_dev *pdev,
957 const struct pci_device_id *ent)
958 {
959 int rc, unit, pci_bar;
960 struct vortex_chip_info *vci;
961 void __iomem *ioaddr;
962
963 /* wake up and enable device */
964 rc = pci_enable_device(pdev);
965 if (rc < 0)
966 goto out;
967
968 unit = vortex_cards_found;
969
970 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
971 /* Determine the default if the user didn't override us */
972 vci = &vortex_info_tbl[ent->driver_data];
973 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
974 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
975 pci_bar = use_mmio[unit] ? 1 : 0;
976 else
977 pci_bar = global_use_mmio ? 1 : 0;
978
979 ioaddr = pci_iomap(pdev, pci_bar, 0);
980 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
981 ioaddr = pci_iomap(pdev, 0, 0);
982
983 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
984 ent->driver_data, unit);
985 if (rc < 0) {
986 pci_disable_device(pdev);
987 goto out;
988 }
989
990 vortex_cards_found++;
991
992 out:
993 return rc;
994 }
995
996 /*
997 * Start up the PCI/EISA device which is described by *gendev.
998 * Return 0 on success.
999 *
1000 * NOTE: pdev can be NULL, for the case of a Compaq device
1001 */
1002 static int __devinit vortex_probe1(struct device *gendev,
1003 void __iomem *ioaddr, int irq,
1004 int chip_idx, int card_idx)
1005 {
1006 struct vortex_private *vp;
1007 int option;
1008 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1009 int i, step;
1010 struct net_device *dev;
1011 static int printed_version;
1012 int retval, print_info;
1013 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1014 char *print_name = "3c59x";
1015 struct pci_dev *pdev = NULL;
1016 struct eisa_device *edev = NULL;
1017 DECLARE_MAC_BUF(mac);
1018
1019 if (!printed_version) {
1020 printk (version);
1021 printed_version = 1;
1022 }
1023
1024 if (gendev) {
1025 if ((pdev = DEVICE_PCI(gendev))) {
1026 print_name = pci_name(pdev);
1027 }
1028
1029 if ((edev = DEVICE_EISA(gendev))) {
1030 print_name = edev->dev.bus_id;
1031 }
1032 }
1033
1034 dev = alloc_etherdev(sizeof(*vp));
1035 retval = -ENOMEM;
1036 if (!dev) {
1037 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1038 goto out;
1039 }
1040 SET_NETDEV_DEV(dev, gendev);
1041 vp = netdev_priv(dev);
1042
1043 option = global_options;
1044
1045 /* The lower four bits are the media type. */
1046 if (dev->mem_start) {
1047 /*
1048 * The 'options' param is passed in as the third arg to the
1049 * LILO 'ether=' argument for non-modular use
1050 */
1051 option = dev->mem_start;
1052 }
1053 else if (card_idx < MAX_UNITS) {
1054 if (options[card_idx] >= 0)
1055 option = options[card_idx];
1056 }
1057
1058 if (option > 0) {
1059 if (option & 0x8000)
1060 vortex_debug = 7;
1061 if (option & 0x4000)
1062 vortex_debug = 2;
1063 if (option & 0x0400)
1064 vp->enable_wol = 1;
1065 }
1066
1067 print_info = (vortex_debug > 1);
1068 if (print_info)
1069 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1070
1071 printk(KERN_INFO "%s: 3Com %s %s at %p.\n",
1072 print_name,
1073 pdev ? "PCI" : "EISA",
1074 vci->name,
1075 ioaddr);
1076
1077 dev->base_addr = (unsigned long)ioaddr;
1078 dev->irq = irq;
1079 dev->mtu = mtu;
1080 vp->ioaddr = ioaddr;
1081 vp->large_frames = mtu > 1500;
1082 vp->drv_flags = vci->drv_flags;
1083 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1084 vp->io_size = vci->io_size;
1085 vp->card_idx = card_idx;
1086
1087 /* module list only for Compaq device */
1088 if (gendev == NULL) {
1089 compaq_net_device = dev;
1090 }
1091
1092 /* PCI-only startup logic */
1093 if (pdev) {
1094 /* EISA resources already marked, so only PCI needs to do this here */
1095 /* Ignore return value, because Cardbus drivers already allocate for us */
1096 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1097 vp->must_free_region = 1;
1098
1099 /* enable bus-mastering if necessary */
1100 if (vci->flags & PCI_USES_MASTER)
1101 pci_set_master(pdev);
1102
1103 if (vci->drv_flags & IS_VORTEX) {
1104 u8 pci_latency;
1105 u8 new_latency = 248;
1106
1107 /* Check the PCI latency value. On the 3c590 series the latency timer
1108 must be set to the maximum value to avoid data corruption that occurs
1109 when the timer expires during a transfer. This bug exists the Vortex
1110 chip only. */
1111 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1112 if (pci_latency < new_latency) {
1113 printk(KERN_INFO "%s: Overriding PCI latency"
1114 " timer (CFLT) setting of %d, new value is %d.\n",
1115 print_name, pci_latency, new_latency);
1116 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1117 }
1118 }
1119 }
1120
1121 spin_lock_init(&vp->lock);
1122 vp->gendev = gendev;
1123 vp->mii.dev = dev;
1124 vp->mii.mdio_read = mdio_read;
1125 vp->mii.mdio_write = mdio_write;
1126 vp->mii.phy_id_mask = 0x1f;
1127 vp->mii.reg_num_mask = 0x1f;
1128
1129 /* Makes sure rings are at least 16 byte aligned. */
1130 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1131 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1132 &vp->rx_ring_dma);
1133 retval = -ENOMEM;
1134 if (!vp->rx_ring)
1135 goto free_region;
1136
1137 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1138 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1139
1140 /* if we are a PCI driver, we store info in pdev->driver_data
1141 * instead of a module list */
1142 if (pdev)
1143 pci_set_drvdata(pdev, dev);
1144 if (edev)
1145 eisa_set_drvdata(edev, dev);
1146
1147 vp->media_override = 7;
1148 if (option >= 0) {
1149 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1150 if (vp->media_override != 7)
1151 vp->medialock = 1;
1152 vp->full_duplex = (option & 0x200) ? 1 : 0;
1153 vp->bus_master = (option & 16) ? 1 : 0;
1154 }
1155
1156 if (global_full_duplex > 0)
1157 vp->full_duplex = 1;
1158 if (global_enable_wol > 0)
1159 vp->enable_wol = 1;
1160
1161 if (card_idx < MAX_UNITS) {
1162 if (full_duplex[card_idx] > 0)
1163 vp->full_duplex = 1;
1164 if (flow_ctrl[card_idx] > 0)
1165 vp->flow_ctrl = 1;
1166 if (enable_wol[card_idx] > 0)
1167 vp->enable_wol = 1;
1168 }
1169
1170 vp->mii.force_media = vp->full_duplex;
1171 vp->options = option;
1172 /* Read the station address from the EEPROM. */
1173 EL3WINDOW(0);
1174 {
1175 int base;
1176
1177 if (vci->drv_flags & EEPROM_8BIT)
1178 base = 0x230;
1179 else if (vci->drv_flags & EEPROM_OFFSET)
1180 base = EEPROM_Read + 0x30;
1181 else
1182 base = EEPROM_Read;
1183
1184 for (i = 0; i < 0x40; i++) {
1185 int timer;
1186 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1187 /* Pause for at least 162 us. for the read to take place. */
1188 for (timer = 10; timer >= 0; timer--) {
1189 udelay(162);
1190 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1191 break;
1192 }
1193 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1194 }
1195 }
1196 for (i = 0; i < 0x18; i++)
1197 checksum ^= eeprom[i];
1198 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1199 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1200 while (i < 0x21)
1201 checksum ^= eeprom[i++];
1202 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1203 }
1204 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1205 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1206 for (i = 0; i < 3; i++)
1207 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1208 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1209 if (print_info)
1210 printk(" %s", print_mac(mac, dev->dev_addr));
1211 /* Unfortunately an all zero eeprom passes the checksum and this
1212 gets found in the wild in failure cases. Crypto is hard 8) */
1213 if (!is_valid_ether_addr(dev->dev_addr)) {
1214 retval = -EINVAL;
1215 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1216 goto free_ring; /* With every pack */
1217 }
1218 EL3WINDOW(2);
1219 for (i = 0; i < 6; i++)
1220 iowrite8(dev->dev_addr[i], ioaddr + i);
1221
1222 if (print_info)
1223 printk(", IRQ %d\n", dev->irq);
1224 /* Tell them about an invalid IRQ. */
1225 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1226 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1227 dev->irq);
1228
1229 EL3WINDOW(4);
1230 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1231 if (print_info) {
1232 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1233 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1234 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1235 }
1236
1237
1238 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1239 unsigned short n;
1240
1241 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1242 if (!vp->cb_fn_base) {
1243 retval = -ENOMEM;
1244 goto free_ring;
1245 }
1246
1247 if (print_info) {
1248 printk(KERN_INFO "%s: CardBus functions mapped "
1249 "%16.16llx->%p\n",
1250 print_name,
1251 (unsigned long long)pci_resource_start(pdev, 2),
1252 vp->cb_fn_base);
1253 }
1254 EL3WINDOW(2);
1255
1256 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1257 if (vp->drv_flags & INVERT_LED_PWR)
1258 n |= 0x10;
1259 if (vp->drv_flags & INVERT_MII_PWR)
1260 n |= 0x4000;
1261 iowrite16(n, ioaddr + Wn2_ResetOptions);
1262 if (vp->drv_flags & WNO_XCVR_PWR) {
1263 EL3WINDOW(0);
1264 iowrite16(0x0800, ioaddr);
1265 }
1266 }
1267
1268 /* Extract our information from the EEPROM data. */
1269 vp->info1 = eeprom[13];
1270 vp->info2 = eeprom[15];
1271 vp->capabilities = eeprom[16];
1272
1273 if (vp->info1 & 0x8000) {
1274 vp->full_duplex = 1;
1275 if (print_info)
1276 printk(KERN_INFO "Full duplex capable\n");
1277 }
1278
1279 {
1280 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1281 unsigned int config;
1282 EL3WINDOW(3);
1283 vp->available_media = ioread16(ioaddr + Wn3_Options);
1284 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1285 vp->available_media = 0x40;
1286 config = ioread32(ioaddr + Wn3_Config);
1287 if (print_info) {
1288 printk(KERN_DEBUG " Internal config register is %4.4x, "
1289 "transceivers %#x.\n", config, ioread16(ioaddr + Wn3_Options));
1290 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1291 8 << RAM_SIZE(config),
1292 RAM_WIDTH(config) ? "word" : "byte",
1293 ram_split[RAM_SPLIT(config)],
1294 AUTOSELECT(config) ? "autoselect/" : "",
1295 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1296 media_tbl[XCVR(config)].name);
1297 }
1298 vp->default_media = XCVR(config);
1299 if (vp->default_media == XCVR_NWAY)
1300 vp->has_nway = 1;
1301 vp->autoselect = AUTOSELECT(config);
1302 }
1303
1304 if (vp->media_override != 7) {
1305 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1306 print_name, vp->media_override,
1307 media_tbl[vp->media_override].name);
1308 dev->if_port = vp->media_override;
1309 } else
1310 dev->if_port = vp->default_media;
1311
1312 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1313 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1314 int phy, phy_idx = 0;
1315 EL3WINDOW(4);
1316 mii_preamble_required++;
1317 if (vp->drv_flags & EXTRA_PREAMBLE)
1318 mii_preamble_required++;
1319 mdio_sync(ioaddr, 32);
1320 mdio_read(dev, 24, MII_BMSR);
1321 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1322 int mii_status, phyx;
1323
1324 /*
1325 * For the 3c905CX we look at index 24 first, because it bogusly
1326 * reports an external PHY at all indices
1327 */
1328 if (phy == 0)
1329 phyx = 24;
1330 else if (phy <= 24)
1331 phyx = phy - 1;
1332 else
1333 phyx = phy;
1334 mii_status = mdio_read(dev, phyx, MII_BMSR);
1335 if (mii_status && mii_status != 0xffff) {
1336 vp->phys[phy_idx++] = phyx;
1337 if (print_info) {
1338 printk(KERN_INFO " MII transceiver found at address %d,"
1339 " status %4x.\n", phyx, mii_status);
1340 }
1341 if ((mii_status & 0x0040) == 0)
1342 mii_preamble_required++;
1343 }
1344 }
1345 mii_preamble_required--;
1346 if (phy_idx == 0) {
1347 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1348 vp->phys[0] = 24;
1349 } else {
1350 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1351 if (vp->full_duplex) {
1352 /* Only advertise the FD media types. */
1353 vp->advertising &= ~0x02A0;
1354 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1355 }
1356 }
1357 vp->mii.phy_id = vp->phys[0];
1358 }
1359
1360 if (vp->capabilities & CapBusMaster) {
1361 vp->full_bus_master_tx = 1;
1362 if (print_info) {
1363 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1364 (vp->info2 & 1) ? "early" : "whole-frame" );
1365 }
1366 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1367 vp->bus_master = 0; /* AKPM: vortex only */
1368 }
1369
1370 /* The 3c59x-specific entries in the device structure. */
1371 dev->open = vortex_open;
1372 if (vp->full_bus_master_tx) {
1373 dev->hard_start_xmit = boomerang_start_xmit;
1374 /* Actually, it still should work with iommu. */
1375 if (card_idx < MAX_UNITS &&
1376 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1377 hw_checksums[card_idx] == 1)) {
1378 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1379 }
1380 } else {
1381 dev->hard_start_xmit = vortex_start_xmit;
1382 }
1383
1384 if (print_info) {
1385 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1386 print_name,
1387 (dev->features & NETIF_F_SG) ? "en":"dis",
1388 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1389 }
1390
1391 dev->stop = vortex_close;
1392 dev->get_stats = vortex_get_stats;
1393 #ifdef CONFIG_PCI
1394 dev->do_ioctl = vortex_ioctl;
1395 #endif
1396 dev->ethtool_ops = &vortex_ethtool_ops;
1397 dev->set_multicast_list = set_rx_mode;
1398 dev->tx_timeout = vortex_tx_timeout;
1399 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1400 #ifdef CONFIG_NET_POLL_CONTROLLER
1401 dev->poll_controller = poll_vortex;
1402 #endif
1403 if (pdev) {
1404 vp->pm_state_valid = 1;
1405 pci_save_state(VORTEX_PCI(vp));
1406 acpi_set_WOL(dev);
1407 }
1408 retval = register_netdev(dev);
1409 if (retval == 0)
1410 return 0;
1411
1412 free_ring:
1413 pci_free_consistent(pdev,
1414 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1415 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1416 vp->rx_ring,
1417 vp->rx_ring_dma);
1418 free_region:
1419 if (vp->must_free_region)
1420 release_region(dev->base_addr, vci->io_size);
1421 free_netdev(dev);
1422 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1423 out:
1424 return retval;
1425 }
1426
1427 static void
1428 issue_and_wait(struct net_device *dev, int cmd)
1429 {
1430 struct vortex_private *vp = netdev_priv(dev);
1431 void __iomem *ioaddr = vp->ioaddr;
1432 int i;
1433
1434 iowrite16(cmd, ioaddr + EL3_CMD);
1435 for (i = 0; i < 2000; i++) {
1436 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1437 return;
1438 }
1439
1440 /* OK, that didn't work. Do it the slow way. One second */
1441 for (i = 0; i < 100000; i++) {
1442 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1443 if (vortex_debug > 1)
1444 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1445 dev->name, cmd, i * 10);
1446 return;
1447 }
1448 udelay(10);
1449 }
1450 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
1451 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1452 }
1453
1454 static void
1455 vortex_set_duplex(struct net_device *dev)
1456 {
1457 struct vortex_private *vp = netdev_priv(dev);
1458 void __iomem *ioaddr = vp->ioaddr;
1459
1460 printk(KERN_INFO "%s: setting %s-duplex.\n",
1461 dev->name, (vp->full_duplex) ? "full" : "half");
1462
1463 EL3WINDOW(3);
1464 /* Set the full-duplex bit. */
1465 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1466 (vp->large_frames ? 0x40 : 0) |
1467 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1468 0x100 : 0),
1469 ioaddr + Wn3_MAC_Ctrl);
1470 }
1471
1472 static void vortex_check_media(struct net_device *dev, unsigned int init)
1473 {
1474 struct vortex_private *vp = netdev_priv(dev);
1475 unsigned int ok_to_print = 0;
1476
1477 if (vortex_debug > 3)
1478 ok_to_print = 1;
1479
1480 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1481 vp->full_duplex = vp->mii.full_duplex;
1482 vortex_set_duplex(dev);
1483 } else if (init) {
1484 vortex_set_duplex(dev);
1485 }
1486 }
1487
1488 static int
1489 vortex_up(struct net_device *dev)
1490 {
1491 struct vortex_private *vp = netdev_priv(dev);
1492 void __iomem *ioaddr = vp->ioaddr;
1493 unsigned int config;
1494 int i, mii_reg1, mii_reg5, err = 0;
1495
1496 if (VORTEX_PCI(vp)) {
1497 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
1498 if (vp->pm_state_valid)
1499 pci_restore_state(VORTEX_PCI(vp));
1500 err = pci_enable_device(VORTEX_PCI(vp));
1501 if (err) {
1502 printk(KERN_WARNING "%s: Could not enable device \n",
1503 dev->name);
1504 goto err_out;
1505 }
1506 }
1507
1508 /* Before initializing select the active media port. */
1509 EL3WINDOW(3);
1510 config = ioread32(ioaddr + Wn3_Config);
1511
1512 if (vp->media_override != 7) {
1513 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1514 dev->name, vp->media_override,
1515 media_tbl[vp->media_override].name);
1516 dev->if_port = vp->media_override;
1517 } else if (vp->autoselect) {
1518 if (vp->has_nway) {
1519 if (vortex_debug > 1)
1520 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1521 dev->name, dev->if_port);
1522 dev->if_port = XCVR_NWAY;
1523 } else {
1524 /* Find first available media type, starting with 100baseTx. */
1525 dev->if_port = XCVR_100baseTx;
1526 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1527 dev->if_port = media_tbl[dev->if_port].next;
1528 if (vortex_debug > 1)
1529 printk(KERN_INFO "%s: first available media type: %s\n",
1530 dev->name, media_tbl[dev->if_port].name);
1531 }
1532 } else {
1533 dev->if_port = vp->default_media;
1534 if (vortex_debug > 1)
1535 printk(KERN_INFO "%s: using default media %s\n",
1536 dev->name, media_tbl[dev->if_port].name);
1537 }
1538
1539 init_timer(&vp->timer);
1540 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1541 vp->timer.data = (unsigned long)dev;
1542 vp->timer.function = vortex_timer; /* timer handler */
1543 add_timer(&vp->timer);
1544
1545 init_timer(&vp->rx_oom_timer);
1546 vp->rx_oom_timer.data = (unsigned long)dev;
1547 vp->rx_oom_timer.function = rx_oom_timer;
1548
1549 if (vortex_debug > 1)
1550 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1551 dev->name, media_tbl[dev->if_port].name);
1552
1553 vp->full_duplex = vp->mii.force_media;
1554 config = BFINS(config, dev->if_port, 20, 4);
1555 if (vortex_debug > 6)
1556 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
1557 iowrite32(config, ioaddr + Wn3_Config);
1558
1559 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1560 EL3WINDOW(4);
1561 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1562 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1563 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1564 vp->mii.full_duplex = vp->full_duplex;
1565
1566 vortex_check_media(dev, 1);
1567 }
1568 else
1569 vortex_set_duplex(dev);
1570
1571 issue_and_wait(dev, TxReset);
1572 /*
1573 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1574 */
1575 issue_and_wait(dev, RxReset|0x04);
1576
1577
1578 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1579
1580 if (vortex_debug > 1) {
1581 EL3WINDOW(4);
1582 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
1583 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1584 }
1585
1586 /* Set the station address and mask in window 2 each time opened. */
1587 EL3WINDOW(2);
1588 for (i = 0; i < 6; i++)
1589 iowrite8(dev->dev_addr[i], ioaddr + i);
1590 for (; i < 12; i+=2)
1591 iowrite16(0, ioaddr + i);
1592
1593 if (vp->cb_fn_base) {
1594 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1595 if (vp->drv_flags & INVERT_LED_PWR)
1596 n |= 0x10;
1597 if (vp->drv_flags & INVERT_MII_PWR)
1598 n |= 0x4000;
1599 iowrite16(n, ioaddr + Wn2_ResetOptions);
1600 }
1601
1602 if (dev->if_port == XCVR_10base2)
1603 /* Start the thinnet transceiver. We should really wait 50ms...*/
1604 iowrite16(StartCoax, ioaddr + EL3_CMD);
1605 if (dev->if_port != XCVR_NWAY) {
1606 EL3WINDOW(4);
1607 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1608 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1609 }
1610
1611 /* Switch to the stats window, and clear all stats by reading. */
1612 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1613 EL3WINDOW(6);
1614 for (i = 0; i < 10; i++)
1615 ioread8(ioaddr + i);
1616 ioread16(ioaddr + 10);
1617 ioread16(ioaddr + 12);
1618 /* New: On the Vortex we must also clear the BadSSD counter. */
1619 EL3WINDOW(4);
1620 ioread8(ioaddr + 12);
1621 /* ..and on the Boomerang we enable the extra statistics bits. */
1622 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1623
1624 /* Switch to register set 7 for normal use. */
1625 EL3WINDOW(7);
1626
1627 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1628 vp->cur_rx = vp->dirty_rx = 0;
1629 /* Initialize the RxEarly register as recommended. */
1630 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1631 iowrite32(0x0020, ioaddr + PktStatus);
1632 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1633 }
1634 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1635 vp->cur_tx = vp->dirty_tx = 0;
1636 if (vp->drv_flags & IS_BOOMERANG)
1637 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1638 /* Clear the Rx, Tx rings. */
1639 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1640 vp->rx_ring[i].status = 0;
1641 for (i = 0; i < TX_RING_SIZE; i++)
1642 vp->tx_skbuff[i] = NULL;
1643 iowrite32(0, ioaddr + DownListPtr);
1644 }
1645 /* Set receiver mode: presumably accept b-case and phys addr only. */
1646 set_rx_mode(dev);
1647 /* enable 802.1q tagged frames */
1648 set_8021q_mode(dev, 1);
1649 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1650
1651 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1652 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1653 /* Allow status bits to be seen. */
1654 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1655 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1656 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1657 (vp->bus_master ? DMADone : 0);
1658 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1659 (vp->full_bus_master_rx ? 0 : RxComplete) |
1660 StatsFull | HostError | TxComplete | IntReq
1661 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1662 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1663 /* Ack all pending events, and set active indicator mask. */
1664 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1665 ioaddr + EL3_CMD);
1666 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1667 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1668 iowrite32(0x8000, vp->cb_fn_base + 4);
1669 netif_start_queue (dev);
1670 err_out:
1671 return err;
1672 }
1673
1674 static int
1675 vortex_open(struct net_device *dev)
1676 {
1677 struct vortex_private *vp = netdev_priv(dev);
1678 int i;
1679 int retval;
1680
1681 /* Use the now-standard shared IRQ implementation. */
1682 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1683 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1684 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1685 goto err;
1686 }
1687
1688 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1689 if (vortex_debug > 2)
1690 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1691 for (i = 0; i < RX_RING_SIZE; i++) {
1692 struct sk_buff *skb;
1693 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1694 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1695 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1696 skb = dev_alloc_skb(PKT_BUF_SZ);
1697 vp->rx_skbuff[i] = skb;
1698 if (skb == NULL)
1699 break; /* Bad news! */
1700 skb->dev = dev; /* Mark as being used by this device. */
1701 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1702 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1703 }
1704 if (i != RX_RING_SIZE) {
1705 int j;
1706 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1707 for (j = 0; j < i; j++) {
1708 if (vp->rx_skbuff[j]) {
1709 dev_kfree_skb(vp->rx_skbuff[j]);
1710 vp->rx_skbuff[j] = NULL;
1711 }
1712 }
1713 retval = -ENOMEM;
1714 goto err_free_irq;
1715 }
1716 /* Wrap the ring. */
1717 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1718 }
1719
1720 retval = vortex_up(dev);
1721 if (!retval)
1722 goto out;
1723
1724 err_free_irq:
1725 free_irq(dev->irq, dev);
1726 err:
1727 if (vortex_debug > 1)
1728 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1729 out:
1730 return retval;
1731 }
1732
1733 static void
1734 vortex_timer(unsigned long data)
1735 {
1736 struct net_device *dev = (struct net_device *)data;
1737 struct vortex_private *vp = netdev_priv(dev);
1738 void __iomem *ioaddr = vp->ioaddr;
1739 int next_tick = 60*HZ;
1740 int ok = 0;
1741 int media_status, old_window;
1742 unsigned long flags;
1743
1744 if (vortex_debug > 2) {
1745 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1746 dev->name, media_tbl[dev->if_port].name);
1747 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1748 }
1749
1750 spin_lock_irqsave(&vp->lock, flags);
1751 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1752 EL3WINDOW(4);
1753 media_status = ioread16(ioaddr + Wn4_Media);
1754 switch (dev->if_port) {
1755 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1756 if (media_status & Media_LnkBeat) {
1757 netif_carrier_on(dev);
1758 ok = 1;
1759 if (vortex_debug > 1)
1760 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1761 dev->name, media_tbl[dev->if_port].name, media_status);
1762 } else {
1763 netif_carrier_off(dev);
1764 if (vortex_debug > 1) {
1765 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1766 dev->name, media_tbl[dev->if_port].name, media_status);
1767 }
1768 }
1769 break;
1770 case XCVR_MII: case XCVR_NWAY:
1771 {
1772 ok = 1;
1773 vortex_check_media(dev, 0);
1774 }
1775 break;
1776 default: /* Other media types handled by Tx timeouts. */
1777 if (vortex_debug > 1)
1778 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1779 dev->name, media_tbl[dev->if_port].name, media_status);
1780 ok = 1;
1781 }
1782
1783 if (!netif_carrier_ok(dev))
1784 next_tick = 5*HZ;
1785
1786 if (vp->medialock)
1787 goto leave_media_alone;
1788
1789 if (!ok) {
1790 unsigned int config;
1791
1792 do {
1793 dev->if_port = media_tbl[dev->if_port].next;
1794 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1795 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1796 dev->if_port = vp->default_media;
1797 if (vortex_debug > 1)
1798 printk(KERN_DEBUG "%s: Media selection failing, using default "
1799 "%s port.\n",
1800 dev->name, media_tbl[dev->if_port].name);
1801 } else {
1802 if (vortex_debug > 1)
1803 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1804 "%s port.\n",
1805 dev->name, media_tbl[dev->if_port].name);
1806 next_tick = media_tbl[dev->if_port].wait;
1807 }
1808 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1809 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1810
1811 EL3WINDOW(3);
1812 config = ioread32(ioaddr + Wn3_Config);
1813 config = BFINS(config, dev->if_port, 20, 4);
1814 iowrite32(config, ioaddr + Wn3_Config);
1815
1816 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1817 ioaddr + EL3_CMD);
1818 if (vortex_debug > 1)
1819 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1820 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1821 }
1822
1823 leave_media_alone:
1824 if (vortex_debug > 2)
1825 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1826 dev->name, media_tbl[dev->if_port].name);
1827
1828 EL3WINDOW(old_window);
1829 spin_unlock_irqrestore(&vp->lock, flags);
1830 mod_timer(&vp->timer, RUN_AT(next_tick));
1831 if (vp->deferred)
1832 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1833 return;
1834 }
1835
1836 static void vortex_tx_timeout(struct net_device *dev)
1837 {
1838 struct vortex_private *vp = netdev_priv(dev);
1839 void __iomem *ioaddr = vp->ioaddr;
1840
1841 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1842 dev->name, ioread8(ioaddr + TxStatus),
1843 ioread16(ioaddr + EL3_STATUS));
1844 EL3WINDOW(4);
1845 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1846 ioread16(ioaddr + Wn4_NetDiag),
1847 ioread16(ioaddr + Wn4_Media),
1848 ioread32(ioaddr + PktStatus),
1849 ioread16(ioaddr + Wn4_FIFODiag));
1850 /* Slight code bloat to be user friendly. */
1851 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1852 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
1853 " network cable problem?\n", dev->name);
1854 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1855 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
1856 " IRQ blocked by another device?\n", dev->name);
1857 /* Bad idea here.. but we might as well handle a few events. */
1858 {
1859 /*
1860 * Block interrupts because vortex_interrupt does a bare spin_lock()
1861 */
1862 unsigned long flags;
1863 local_irq_save_nort(flags);
1864 if (vp->full_bus_master_tx)
1865 boomerang_interrupt(dev->irq, dev);
1866 else
1867 vortex_interrupt(dev->irq, dev);
1868 local_irq_restore_nort(flags);
1869 }
1870 }
1871
1872 if (vortex_debug > 0)
1873 dump_tx_ring(dev);
1874
1875 issue_and_wait(dev, TxReset);
1876
1877 vp->stats.tx_errors++;
1878 if (vp->full_bus_master_tx) {
1879 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
1880 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1881 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1882 ioaddr + DownListPtr);
1883 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1884 netif_wake_queue (dev);
1885 if (vp->drv_flags & IS_BOOMERANG)
1886 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1887 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1888 } else {
1889 vp->stats.tx_dropped++;
1890 netif_wake_queue(dev);
1891 }
1892
1893 /* Issue Tx Enable */
1894 iowrite16(TxEnable, ioaddr + EL3_CMD);
1895 dev->trans_start = jiffies;
1896
1897 /* Switch to register set 7 for normal use. */
1898 EL3WINDOW(7);
1899 }
1900
1901 /*
1902 * Handle uncommon interrupt sources. This is a separate routine to minimize
1903 * the cache impact.
1904 */
1905 static void
1906 vortex_error(struct net_device *dev, int status)
1907 {
1908 struct vortex_private *vp = netdev_priv(dev);
1909 void __iomem *ioaddr = vp->ioaddr;
1910 int do_tx_reset = 0, reset_mask = 0;
1911 unsigned char tx_status = 0;
1912
1913 if (vortex_debug > 2) {
1914 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
1915 }
1916
1917 if (status & TxComplete) { /* Really "TxError" for us. */
1918 tx_status = ioread8(ioaddr + TxStatus);
1919 /* Presumably a tx-timeout. We must merely re-enable. */
1920 if (vortex_debug > 2
1921 || (tx_status != 0x88 && vortex_debug > 0)) {
1922 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
1923 dev->name, tx_status);
1924 if (tx_status == 0x82) {
1925 printk(KERN_ERR "Probably a duplex mismatch. See "
1926 "Documentation/networking/vortex.txt\n");
1927 }
1928 dump_tx_ring(dev);
1929 }
1930 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
1931 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
1932 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
1933 iowrite8(0, ioaddr + TxStatus);
1934 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1935 do_tx_reset = 1;
1936 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1937 do_tx_reset = 1;
1938 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1939 } else { /* Merely re-enable the transmitter. */
1940 iowrite16(TxEnable, ioaddr + EL3_CMD);
1941 }
1942 }
1943
1944 if (status & RxEarly) { /* Rx early is unused. */
1945 vortex_rx(dev);
1946 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1947 }
1948 if (status & StatsFull) { /* Empty statistics. */
1949 static int DoneDidThat;
1950 if (vortex_debug > 4)
1951 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
1952 update_stats(ioaddr, dev);
1953 /* HACK: Disable statistics as an interrupt source. */
1954 /* This occurs when we have the wrong media type! */
1955 if (DoneDidThat == 0 &&
1956 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1957 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
1958 "stats as an interrupt source.\n", dev->name);
1959 EL3WINDOW(5);
1960 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1961 vp->intr_enable &= ~StatsFull;
1962 EL3WINDOW(7);
1963 DoneDidThat++;
1964 }
1965 }
1966 if (status & IntReq) { /* Restore all interrupt sources. */
1967 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1968 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1969 }
1970 if (status & HostError) {
1971 u16 fifo_diag;
1972 EL3WINDOW(4);
1973 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1974 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
1975 dev->name, fifo_diag);
1976 /* Adapter failure requires Tx/Rx reset and reinit. */
1977 if (vp->full_bus_master_tx) {
1978 int bus_status = ioread32(ioaddr + PktStatus);
1979 /* 0x80000000 PCI master abort. */
1980 /* 0x40000000 PCI target abort. */
1981 if (vortex_debug)
1982 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1983
1984 /* In this case, blow the card away */
1985 /* Must not enter D3 or we can't legally issue the reset! */
1986 vortex_down(dev, 0);
1987 issue_and_wait(dev, TotalReset | 0xff);
1988 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
1989 } else if (fifo_diag & 0x0400)
1990 do_tx_reset = 1;
1991 if (fifo_diag & 0x3000) {
1992 /* Reset Rx fifo and upload logic */
1993 issue_and_wait(dev, RxReset|0x07);
1994 /* Set the Rx filter to the current state. */
1995 set_rx_mode(dev);
1996 /* enable 802.1q VLAN tagged frames */
1997 set_8021q_mode(dev, 1);
1998 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
1999 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2000 }
2001 }
2002
2003 if (do_tx_reset) {
2004 issue_and_wait(dev, TxReset|reset_mask);
2005 iowrite16(TxEnable, ioaddr + EL3_CMD);
2006 if (!vp->full_bus_master_tx)
2007 netif_wake_queue(dev);
2008 }
2009 }
2010
2011 static int
2012 vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2013 {
2014 struct vortex_private *vp = netdev_priv(dev);
2015 void __iomem *ioaddr = vp->ioaddr;
2016
2017 /* Put out the doubleword header... */
2018 iowrite32(skb->len, ioaddr + TX_FIFO);
2019 if (vp->bus_master) {
2020 /* Set the bus-master controller to transfer the packet. */
2021 int len = (skb->len + 3) & ~3;
2022 iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
2023 ioaddr + Wn7_MasterAddr);
2024 iowrite16(len, ioaddr + Wn7_MasterLen);
2025 vp->tx_skb = skb;
2026 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2027 /* netif_wake_queue() will be called at the DMADone interrupt. */
2028 } else {
2029 /* ... and the packet rounded to a doubleword. */
2030 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2031 dev_kfree_skb (skb);
2032 if (ioread16(ioaddr + TxFree) > 1536) {
2033 netif_start_queue (dev); /* AKPM: redundant? */
2034 } else {
2035 /* Interrupt us when the FIFO has room for max-sized packet. */
2036 netif_stop_queue(dev);
2037 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2038 }
2039 }
2040
2041 dev->trans_start = jiffies;
2042
2043 /* Clear the Tx status stack. */
2044 {
2045 int tx_status;
2046 int i = 32;
2047
2048 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2049 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2050 if (vortex_debug > 2)
2051 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2052 dev->name, tx_status);
2053 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2054 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2055 if (tx_status & 0x30) {
2056 issue_and_wait(dev, TxReset);
2057 }
2058 iowrite16(TxEnable, ioaddr + EL3_CMD);
2059 }
2060 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2061 }
2062 }
2063 return 0;
2064 }
2065
2066 static int
2067 boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2068 {
2069 struct vortex_private *vp = netdev_priv(dev);
2070 void __iomem *ioaddr = vp->ioaddr;
2071 /* Calculate the next Tx descriptor entry. */
2072 int entry = vp->cur_tx % TX_RING_SIZE;
2073 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2074 unsigned long flags;
2075
2076 if (vortex_debug > 6) {
2077 printk(KERN_DEBUG "boomerang_start_xmit()\n");
2078 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2079 dev->name, vp->cur_tx);
2080 }
2081
2082 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2083 if (vortex_debug > 0)
2084 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2085 dev->name);
2086 netif_stop_queue(dev);
2087 return 1;
2088 }
2089
2090 vp->tx_skbuff[entry] = skb;
2091
2092 vp->tx_ring[entry].next = 0;
2093 #if DO_ZEROCOPY
2094 if (skb->ip_summed != CHECKSUM_PARTIAL)
2095 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2096 else
2097 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2098
2099 if (!skb_shinfo(skb)->nr_frags) {
2100 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2101 skb->len, PCI_DMA_TODEVICE));
2102 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2103 } else {
2104 int i;
2105
2106 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2107 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2108 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2109
2110 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2111 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2112
2113 vp->tx_ring[entry].frag[i+1].addr =
2114 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2115 (void*)page_address(frag->page) + frag->page_offset,
2116 frag->size, PCI_DMA_TODEVICE));
2117
2118 if (i == skb_shinfo(skb)->nr_frags-1)
2119 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2120 else
2121 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2122 }
2123 }
2124 #else
2125 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2126 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2127 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2128 #endif
2129
2130 spin_lock_irqsave(&vp->lock, flags);
2131 /* Wait for the stall to complete. */
2132 issue_and_wait(dev, DownStall);
2133 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2134 if (ioread32(ioaddr + DownListPtr) == 0) {
2135 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2136 vp->queued_packet++;
2137 }
2138
2139 vp->cur_tx++;
2140 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2141 netif_stop_queue (dev);
2142 } else { /* Clear previous interrupt enable. */
2143 #if defined(tx_interrupt_mitigation)
2144 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2145 * were selected, this would corrupt DN_COMPLETE. No?
2146 */
2147 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2148 #endif
2149 }
2150 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2151 spin_unlock_irqrestore(&vp->lock, flags);
2152 dev->trans_start = jiffies;
2153 return 0;
2154 }
2155
2156 /* The interrupt handler does all of the Rx thread work and cleans up
2157 after the Tx thread. */
2158
2159 /*
2160 * This is the ISR for the vortex series chips.
2161 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2162 */
2163
2164 static irqreturn_t
2165 vortex_interrupt(int irq, void *dev_id)
2166 {
2167 struct net_device *dev = dev_id;
2168 struct vortex_private *vp = netdev_priv(dev);
2169 void __iomem *ioaddr;
2170 int status;
2171 int work_done = max_interrupt_work;
2172 int handled = 0;
2173
2174 ioaddr = vp->ioaddr;
2175 spin_lock(&vp->lock);
2176
2177 status = ioread16(ioaddr + EL3_STATUS);
2178
2179 if (vortex_debug > 6)
2180 printk("vortex_interrupt(). status=0x%4x\n", status);
2181
2182 if ((status & IntLatch) == 0)
2183 goto handler_exit; /* No interrupt: shared IRQs cause this */
2184 handled = 1;
2185
2186 if (status & IntReq) {
2187 status |= vp->deferred;
2188 vp->deferred = 0;
2189 }
2190
2191 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2192 goto handler_exit;
2193
2194 if (vortex_debug > 4)
2195 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2196 dev->name, status, ioread8(ioaddr + Timer));
2197
2198 do {
2199 if (vortex_debug > 5)
2200 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2201 dev->name, status);
2202 if (status & RxComplete)
2203 vortex_rx(dev);
2204
2205 if (status & TxAvailable) {
2206 if (vortex_debug > 5)
2207 printk(KERN_DEBUG " TX room bit was handled.\n");
2208 /* There's room in the FIFO for a full-sized packet. */
2209 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2210 netif_wake_queue (dev);
2211 }
2212
2213 if (status & DMADone) {
2214 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2215 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2216 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2217 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2218 if (ioread16(ioaddr + TxFree) > 1536) {
2219 /*
2220 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2221 * insufficient FIFO room, the TxAvailable test will succeed and call
2222 * netif_wake_queue()
2223 */
2224 netif_wake_queue(dev);
2225 } else { /* Interrupt when FIFO has room for max-sized packet. */
2226 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2227 netif_stop_queue(dev);
2228 }
2229 }
2230 }
2231 /* Check for all uncommon interrupts at once. */
2232 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2233 if (status == 0xffff)
2234 break;
2235 vortex_error(dev, status);
2236 }
2237
2238 if (--work_done < 0) {
2239 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2240 "%4.4x.\n", dev->name, status);
2241 /* Disable all pending interrupts. */
2242 do {
2243 vp->deferred |= status;
2244 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2245 ioaddr + EL3_CMD);
2246 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2247 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2248 /* The timer will reenable interrupts. */
2249 mod_timer(&vp->timer, jiffies + 1*HZ);
2250 break;
2251 }
2252 /* Acknowledge the IRQ. */
2253 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2254 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2255
2256 if (vortex_debug > 4)
2257 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2258 dev->name, status);
2259 handler_exit:
2260 spin_unlock(&vp->lock);
2261 return IRQ_RETVAL(handled);
2262 }
2263
2264 /*
2265 * This is the ISR for the boomerang series chips.
2266 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2267 */
2268
2269 static irqreturn_t
2270 boomerang_interrupt(int irq, void *dev_id)
2271 {
2272 struct net_device *dev = dev_id;
2273 struct vortex_private *vp = netdev_priv(dev);
2274 void __iomem *ioaddr;
2275 int status;
2276 int work_done = max_interrupt_work;
2277
2278 ioaddr = vp->ioaddr;
2279
2280 /*
2281 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2282 * and boomerang_start_xmit
2283 */
2284 spin_lock(&vp->lock);
2285
2286 status = ioread16(ioaddr + EL3_STATUS);
2287
2288 if (vortex_debug > 6)
2289 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2290
2291 if ((status & IntLatch) == 0)
2292 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2293
2294 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2295 if (vortex_debug > 1)
2296 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2297 goto handler_exit;
2298 }
2299
2300 if (status & IntReq) {
2301 status |= vp->deferred;
2302 vp->deferred = 0;
2303 }
2304
2305 if (vortex_debug > 4)
2306 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2307 dev->name, status, ioread8(ioaddr + Timer));
2308 do {
2309 if (vortex_debug > 5)
2310 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2311 dev->name, status);
2312 if (status & UpComplete) {
2313 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2314 if (vortex_debug > 5)
2315 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2316 boomerang_rx(dev);
2317 }
2318
2319 if (status & DownComplete) {
2320 unsigned int dirty_tx = vp->dirty_tx;
2321
2322 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2323 while (vp->cur_tx - dirty_tx > 0) {
2324 int entry = dirty_tx % TX_RING_SIZE;
2325 #if 1 /* AKPM: the latter is faster, but cyclone-only */
2326 if (ioread32(ioaddr + DownListPtr) ==
2327 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2328 break; /* It still hasn't been processed. */
2329 #else
2330 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2331 break; /* It still hasn't been processed. */
2332 #endif
2333
2334 if (vp->tx_skbuff[entry]) {
2335 struct sk_buff *skb = vp->tx_skbuff[entry];
2336 #if DO_ZEROCOPY
2337 int i;
2338 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2339 pci_unmap_single(VORTEX_PCI(vp),
2340 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2341 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2342 PCI_DMA_TODEVICE);
2343 #else
2344 pci_unmap_single(VORTEX_PCI(vp),
2345 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2346 #endif
2347 dev_kfree_skb_irq(skb);
2348 vp->tx_skbuff[entry] = NULL;
2349 } else {
2350 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2351 }
2352 /* vp->stats.tx_packets++; Counted below. */
2353 dirty_tx++;
2354 }
2355 vp->dirty_tx = dirty_tx;
2356 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2357 if (vortex_debug > 6)
2358 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2359 netif_wake_queue (dev);
2360 }
2361 }
2362
2363 /* Check for all uncommon interrupts at once. */
2364 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2365 vortex_error(dev, status);
2366
2367 if (--work_done < 0) {
2368 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2369 "%4.4x.\n", dev->name, status);
2370 /* Disable all pending interrupts. */
2371 do {
2372 vp->deferred |= status;
2373 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2374 ioaddr + EL3_CMD);
2375 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2376 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2377 /* The timer will reenable interrupts. */
2378 mod_timer(&vp->timer, jiffies + 1*HZ);
2379 break;
2380 }
2381 /* Acknowledge the IRQ. */
2382 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2383 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2384 iowrite32(0x8000, vp->cb_fn_base + 4);
2385
2386 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2387
2388 if (vortex_debug > 4)
2389 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2390 dev->name, status);
2391 handler_exit:
2392 spin_unlock(&vp->lock);
2393 return IRQ_HANDLED;
2394 }
2395
2396 static int vortex_rx(struct net_device *dev)
2397 {
2398 struct vortex_private *vp = netdev_priv(dev);
2399 void __iomem *ioaddr = vp->ioaddr;
2400 int i;
2401 short rx_status;
2402
2403 if (vortex_debug > 5)
2404 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2405 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2406 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2407 if (rx_status & 0x4000) { /* Error, update stats. */
2408 unsigned char rx_error = ioread8(ioaddr + RxErrors);
2409 if (vortex_debug > 2)
2410 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2411 vp->stats.rx_errors++;
2412 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2413 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2414 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2415 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2416 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2417 } else {
2418 /* The packet length: up to 4.5K!. */
2419 int pkt_len = rx_status & 0x1fff;
2420 struct sk_buff *skb;
2421
2422 skb = dev_alloc_skb(pkt_len + 5);
2423 if (vortex_debug > 4)
2424 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2425 pkt_len, rx_status);
2426 if (skb != NULL) {
2427 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2428 /* 'skb_put()' points to the start of sk_buff data area. */
2429 if (vp->bus_master &&
2430 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2431 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2432 pkt_len, PCI_DMA_FROMDEVICE);
2433 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2434 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2435 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2436 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2437 ;
2438 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2439 } else {
2440 ioread32_rep(ioaddr + RX_FIFO,
2441 skb_put(skb, pkt_len),
2442 (pkt_len + 3) >> 2);
2443 }
2444 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2445 skb->protocol = eth_type_trans(skb, dev);
2446 netif_rx(skb);
2447 dev->last_rx = jiffies;
2448 vp->stats.rx_packets++;
2449 /* Wait a limited time to go to next packet. */
2450 for (i = 200; i >= 0; i--)
2451 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2452 break;
2453 continue;
2454 } else if (vortex_debug > 0)
2455 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2456 "size %d.\n", dev->name, pkt_len);
2457 vp->stats.rx_dropped++;
2458 }
2459 issue_and_wait(dev, RxDiscard);
2460 }
2461
2462 return 0;
2463 }
2464
2465 static int
2466 boomerang_rx(struct net_device *dev)
2467 {
2468 struct vortex_private *vp = netdev_priv(dev);
2469 int entry = vp->cur_rx % RX_RING_SIZE;
2470 void __iomem *ioaddr = vp->ioaddr;
2471 int rx_status;
2472 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2473
2474 if (vortex_debug > 5)
2475 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2476
2477 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2478 if (--rx_work_limit < 0)
2479 break;
2480 if (rx_status & RxDError) { /* Error, update stats. */
2481 unsigned char rx_error = rx_status >> 16;
2482 if (vortex_debug > 2)
2483 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2484 vp->stats.rx_errors++;
2485 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2486 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2487 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2488 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2489 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2490 } else {
2491 /* The packet length: up to 4.5K!. */
2492 int pkt_len = rx_status & 0x1fff;
2493 struct sk_buff *skb;
2494 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2495
2496 if (vortex_debug > 4)
2497 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2498 pkt_len, rx_status);
2499
2500 /* Check if the packet is long enough to just accept without
2501 copying to a properly sized skbuff. */
2502 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
2503 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2504 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2505 /* 'skb_put()' points to the start of sk_buff data area. */
2506 memcpy(skb_put(skb, pkt_len),
2507 vp->rx_skbuff[entry]->data,
2508 pkt_len);
2509 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2510 vp->rx_copy++;
2511 } else {
2512 /* Pass up the skbuff already on the Rx ring. */
2513 skb = vp->rx_skbuff[entry];
2514 vp->rx_skbuff[entry] = NULL;
2515 skb_put(skb, pkt_len);
2516 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2517 vp->rx_nocopy++;
2518 }
2519 skb->protocol = eth_type_trans(skb, dev);
2520 { /* Use hardware checksum info. */
2521 int csum_bits = rx_status & 0xee000000;
2522 if (csum_bits &&
2523 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2524 csum_bits == (IPChksumValid | UDPChksumValid))) {
2525 skb->ip_summed = CHECKSUM_UNNECESSARY;
2526 vp->rx_csumhits++;
2527 }
2528 }
2529 netif_rx(skb);
2530 dev->last_rx = jiffies;
2531 vp->stats.rx_packets++;
2532 }
2533 entry = (++vp->cur_rx) % RX_RING_SIZE;
2534 }
2535 /* Refill the Rx ring buffers. */
2536 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2537 struct sk_buff *skb;
2538 entry = vp->dirty_rx % RX_RING_SIZE;
2539 if (vp->rx_skbuff[entry] == NULL) {
2540 skb = dev_alloc_skb(PKT_BUF_SZ);
2541 if (skb == NULL) {
2542 static unsigned long last_jif;
2543 if (time_after(jiffies, last_jif + 10 * HZ)) {
2544 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2545 last_jif = jiffies;
2546 }
2547 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2548 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2549 break; /* Bad news! */
2550 }
2551 skb->dev = dev; /* Mark as being used by this device. */
2552 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2553 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2554 vp->rx_skbuff[entry] = skb;
2555 }
2556 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2557 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2558 }
2559 return 0;
2560 }
2561
2562 /*
2563 * If we've hit a total OOM refilling the Rx ring we poll once a second
2564 * for some memory. Otherwise there is no way to restart the rx process.
2565 */
2566 static void
2567 rx_oom_timer(unsigned long arg)
2568 {
2569 struct net_device *dev = (struct net_device *)arg;
2570 struct vortex_private *vp = netdev_priv(dev);
2571
2572 spin_lock_irq(&vp->lock);
2573 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2574 boomerang_rx(dev);
2575 if (vortex_debug > 1) {
2576 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2577 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2578 }
2579 spin_unlock_irq(&vp->lock);
2580 }
2581
2582 static void
2583 vortex_down(struct net_device *dev, int final_down)
2584 {
2585 struct vortex_private *vp = netdev_priv(dev);
2586 void __iomem *ioaddr = vp->ioaddr;
2587
2588 netif_stop_queue (dev);
2589
2590 del_timer_sync(&vp->rx_oom_timer);
2591 del_timer_sync(&vp->timer);
2592
2593 /* Turn off statistics ASAP. We update vp->stats below. */
2594 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2595
2596 /* Disable the receiver and transmitter. */
2597 iowrite16(RxDisable, ioaddr + EL3_CMD);
2598 iowrite16(TxDisable, ioaddr + EL3_CMD);
2599
2600 /* Disable receiving 802.1q tagged frames */
2601 set_8021q_mode(dev, 0);
2602
2603 if (dev->if_port == XCVR_10base2)
2604 /* Turn off thinnet power. Green! */
2605 iowrite16(StopCoax, ioaddr + EL3_CMD);
2606
2607 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2608
2609 update_stats(ioaddr, dev);
2610 if (vp->full_bus_master_rx)
2611 iowrite32(0, ioaddr + UpListPtr);
2612 if (vp->full_bus_master_tx)
2613 iowrite32(0, ioaddr + DownListPtr);
2614
2615 if (final_down && VORTEX_PCI(vp)) {
2616 vp->pm_state_valid = 1;
2617 pci_save_state(VORTEX_PCI(vp));
2618 acpi_set_WOL(dev);
2619 }
2620 }
2621
2622 static int
2623 vortex_close(struct net_device *dev)
2624 {
2625 struct vortex_private *vp = netdev_priv(dev);
2626 void __iomem *ioaddr = vp->ioaddr;
2627 int i;
2628
2629 if (netif_device_present(dev))
2630 vortex_down(dev, 1);
2631
2632 if (vortex_debug > 1) {
2633 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2634 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2635 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2636 " tx_queued %d Rx pre-checksummed %d.\n",
2637 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2638 }
2639
2640 #if DO_ZEROCOPY
2641 if (vp->rx_csumhits &&
2642 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2643 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2644 printk(KERN_WARNING "%s supports hardware checksums, and we're "
2645 "not using them!\n", dev->name);
2646 }
2647 #endif
2648
2649 free_irq(dev->irq, dev);
2650
2651 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2652 for (i = 0; i < RX_RING_SIZE; i++)
2653 if (vp->rx_skbuff[i]) {
2654 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2655 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2656 dev_kfree_skb(vp->rx_skbuff[i]);
2657 vp->rx_skbuff[i] = NULL;
2658 }
2659 }
2660 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2661 for (i = 0; i < TX_RING_SIZE; i++) {
2662 if (vp->tx_skbuff[i]) {
2663 struct sk_buff *skb = vp->tx_skbuff[i];
2664 #if DO_ZEROCOPY
2665 int k;
2666
2667 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2668 pci_unmap_single(VORTEX_PCI(vp),
2669 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2670 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2671 PCI_DMA_TODEVICE);
2672 #else
2673 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2674 #endif
2675 dev_kfree_skb(skb);
2676 vp->tx_skbuff[i] = NULL;
2677 }
2678 }
2679 }
2680
2681 return 0;
2682 }
2683
2684 static void
2685 dump_tx_ring(struct net_device *dev)
2686 {
2687 if (vortex_debug > 0) {
2688 struct vortex_private *vp = netdev_priv(dev);
2689 void __iomem *ioaddr = vp->ioaddr;
2690
2691 if (vp->full_bus_master_tx) {
2692 int i;
2693 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2694
2695 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2696 vp->full_bus_master_tx,
2697 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2698 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2699 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
2700 ioread32(ioaddr + DownListPtr),
2701 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2702 issue_and_wait(dev, DownStall);
2703 for (i = 0; i < TX_RING_SIZE; i++) {
2704 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2705 &vp->tx_ring[i],
2706 #if DO_ZEROCOPY
2707 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2708 #else
2709 le32_to_cpu(vp->tx_ring[i].length),
2710 #endif
2711 le32_to_cpu(vp->tx_ring[i].status));
2712 }
2713 if (!stalled)
2714 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2715 }
2716 }
2717 }
2718
2719 static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2720 {
2721 struct vortex_private *vp = netdev_priv(dev);
2722 void __iomem *ioaddr = vp->ioaddr;
2723 unsigned long flags;
2724
2725 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2726 spin_lock_irqsave (&vp->lock, flags);
2727 update_stats(ioaddr, dev);
2728 spin_unlock_irqrestore (&vp->lock, flags);
2729 }
2730 return &vp->stats;
2731 }
2732
2733 /* Update statistics.
2734 Unlike with the EL3 we need not worry about interrupts changing
2735 the window setting from underneath us, but we must still guard
2736 against a race condition with a StatsUpdate interrupt updating the
2737 table. This is done by checking that the ASM (!) code generated uses
2738 atomic updates with '+='.
2739 */
2740 static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2741 {
2742 struct vortex_private *vp = netdev_priv(dev);
2743 int old_window = ioread16(ioaddr + EL3_CMD);
2744
2745 if (old_window == 0xffff) /* Chip suspended or ejected. */
2746 return;
2747 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2748 /* Switch to the stats window, and read everything. */
2749 EL3WINDOW(6);
2750 vp->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2751 vp->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
2752 vp->stats.tx_window_errors += ioread8(ioaddr + 4);
2753 vp->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2754 vp->stats.tx_packets += ioread8(ioaddr + 6);
2755 vp->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2756 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
2757 /* Don't bother with register 9, an extension of registers 6&7.
2758 If we do use the 6&7 values the atomic update assumption above
2759 is invalid. */
2760 vp->stats.rx_bytes += ioread16(ioaddr + 10);
2761 vp->stats.tx_bytes += ioread16(ioaddr + 12);
2762 /* Extra stats for get_ethtool_stats() */
2763 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
2764 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
2765 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
2766 EL3WINDOW(4);
2767 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
2768
2769 vp->stats.collisions = vp->xstats.tx_multiple_collisions
2770 + vp->xstats.tx_single_collisions
2771 + vp->xstats.tx_max_collisions;
2772
2773 {
2774 u8 up = ioread8(ioaddr + 13);
2775 vp->stats.rx_bytes += (up & 0x0f) << 16;
2776 vp->stats.tx_bytes += (up & 0xf0) << 12;
2777 }
2778
2779 EL3WINDOW(old_window >> 13);
2780 return;
2781 }
2782
2783 static int vortex_nway_reset(struct net_device *dev)
2784 {
2785 struct vortex_private *vp = netdev_priv(dev);
2786 void __iomem *ioaddr = vp->ioaddr;
2787 unsigned long flags;
2788 int rc;
2789
2790 spin_lock_irqsave(&vp->lock, flags);
2791 EL3WINDOW(4);
2792 rc = mii_nway_restart(&vp->mii);
2793 spin_unlock_irqrestore(&vp->lock, flags);
2794 return rc;
2795 }
2796
2797 static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2798 {
2799 struct vortex_private *vp = netdev_priv(dev);
2800 void __iomem *ioaddr = vp->ioaddr;
2801 unsigned long flags;
2802 int rc;
2803
2804 spin_lock_irqsave(&vp->lock, flags);
2805 EL3WINDOW(4);
2806 rc = mii_ethtool_gset(&vp->mii, cmd);
2807 spin_unlock_irqrestore(&vp->lock, flags);
2808 return rc;
2809 }
2810
2811 static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2812 {
2813 struct vortex_private *vp = netdev_priv(dev);
2814 void __iomem *ioaddr = vp->ioaddr;
2815 unsigned long flags;
2816 int rc;
2817
2818 spin_lock_irqsave(&vp->lock, flags);
2819 EL3WINDOW(4);
2820 rc = mii_ethtool_sset(&vp->mii, cmd);
2821 spin_unlock_irqrestore(&vp->lock, flags);
2822 return rc;
2823 }
2824
2825 static u32 vortex_get_msglevel(struct net_device *dev)
2826 {
2827 return vortex_debug;
2828 }
2829
2830 static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2831 {
2832 vortex_debug = dbg;
2833 }
2834
2835 static int vortex_get_sset_count(struct net_device *dev, int sset)
2836 {
2837 switch (sset) {
2838 case ETH_SS_STATS:
2839 return VORTEX_NUM_STATS;
2840 default:
2841 return -EOPNOTSUPP;
2842 }
2843 }
2844
2845 static void vortex_get_ethtool_stats(struct net_device *dev,
2846 struct ethtool_stats *stats, u64 *data)
2847 {
2848 struct vortex_private *vp = netdev_priv(dev);
2849 void __iomem *ioaddr = vp->ioaddr;
2850 unsigned long flags;
2851
2852 spin_lock_irqsave(&vp->lock, flags);
2853 update_stats(ioaddr, dev);
2854 spin_unlock_irqrestore(&vp->lock, flags);
2855
2856 data[0] = vp->xstats.tx_deferred;
2857 data[1] = vp->xstats.tx_max_collisions;
2858 data[2] = vp->xstats.tx_multiple_collisions;
2859 data[3] = vp->xstats.tx_single_collisions;
2860 data[4] = vp->xstats.rx_bad_ssd;
2861 }
2862
2863
2864 static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2865 {
2866 switch (stringset) {
2867 case ETH_SS_STATS:
2868 memcpy(data, ðtool_stats_keys, sizeof(ethtool_stats_keys));
2869 break;
2870 default:
2871 WARN_ON(1);
2872 break;
2873 }
2874 }
2875
2876 static void vortex_get_drvinfo(struct net_device *dev,
2877 struct ethtool_drvinfo *info)
2878 {
2879 struct vortex_private *vp = netdev_priv(dev);
2880
2881 strcpy(info->driver, DRV_NAME);
2882 if (VORTEX_PCI(vp)) {
2883 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2884 } else {
2885 if (VORTEX_EISA(vp))
2886 sprintf(info->bus_info, vp->gendev->bus_id);
2887 else
2888 sprintf(info->bus_info, "EISA 0x%lx %d",
2889 dev->base_addr, dev->irq);
2890 }
2891 }
2892
2893 static const struct ethtool_ops vortex_ethtool_ops = {
2894 .get_drvinfo = vortex_get_drvinfo,
2895 .get_strings = vortex_get_strings,
2896 .get_msglevel = vortex_get_msglevel,
2897 .set_msglevel = vortex_set_msglevel,
2898 .get_ethtool_stats = vortex_get_ethtool_stats,
2899 .get_sset_count = vortex_get_sset_count,
2900 .get_settings = vortex_get_settings,
2901 .set_settings = vortex_set_settings,
2902 .get_link = ethtool_op_get_link,
2903 .nway_reset = vortex_nway_reset,
2904 };
2905
2906 #ifdef CONFIG_PCI
2907 /*
2908 * Must power the device up to do MDIO operations
2909 */
2910 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2911 {
2912 int err;
2913 struct vortex_private *vp = netdev_priv(dev);
2914 void __iomem *ioaddr = vp->ioaddr;
2915 unsigned long flags;
2916 pci_power_t state = 0;
2917
2918 if(VORTEX_PCI(vp))
2919 state = VORTEX_PCI(vp)->current_state;
2920
2921 /* The kernel core really should have pci_get_power_state() */
2922
2923 if(state != 0)
2924 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2925 spin_lock_irqsave(&vp->lock, flags);
2926 EL3WINDOW(4);
2927 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2928 spin_unlock_irqrestore(&vp->lock, flags);
2929 if(state != 0)
2930 pci_set_power_state(VORTEX_PCI(vp), state);
2931
2932 return err;
2933 }
2934 #endif
2935
2936
2937 /* Pre-Cyclone chips have no documented multicast filter, so the only
2938 multicast setting is to receive all multicast frames. At least
2939 the chip has a very clean way to set the mode, unlike many others. */
2940 static void set_rx_mode(struct net_device *dev)
2941 {
2942 struct vortex_private *vp = netdev_priv(dev);
2943 void __iomem *ioaddr = vp->ioaddr;
2944 int new_mode;
2945
2946 if (dev->flags & IFF_PROMISC) {
2947 if (vortex_debug > 3)
2948 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
2949 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2950 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2951 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2952 } else
2953 new_mode = SetRxFilter | RxStation | RxBroadcast;
2954
2955 iowrite16(new_mode, ioaddr + EL3_CMD);
2956 }
2957
2958 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
2959 /* Setup the card so that it can receive frames with an 802.1q VLAN tag.
2960 Note that this must be done after each RxReset due to some backwards
2961 compatibility logic in the Cyclone and Tornado ASICs */
2962
2963 /* The Ethernet Type used for 802.1q tagged frames */
2964 #define VLAN_ETHER_TYPE 0x8100
2965
2966 static void set_8021q_mode(struct net_device *dev, int enable)
2967 {
2968 struct vortex_private *vp = netdev_priv(dev);
2969 void __iomem *ioaddr = vp->ioaddr;
2970 int old_window = ioread16(ioaddr + EL3_CMD);
2971 int mac_ctrl;
2972
2973 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
2974 /* cyclone and tornado chipsets can recognize 802.1q
2975 * tagged frames and treat them correctly */
2976
2977 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
2978 if (enable)
2979 max_pkt_size += 4; /* 802.1Q VLAN tag */
2980
2981 EL3WINDOW(3);
2982 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
2983
2984 /* set VlanEtherType to let the hardware checksumming
2985 treat tagged frames correctly */
2986 EL3WINDOW(7);
2987 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
2988 } else {
2989 /* on older cards we have to enable large frames */
2990
2991 vp->large_frames = dev->mtu > 1500 || enable;
2992
2993 EL3WINDOW(3);
2994 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
2995 if (vp->large_frames)
2996 mac_ctrl |= 0x40;
2997 else
2998 mac_ctrl &= ~0x40;
2999 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
3000 }
3001
3002 EL3WINDOW(old_window);
3003 }
3004 #else
3005
3006 static void set_8021q_mode(struct net_device *dev, int enable)
3007 {
3008 }
3009
3010
3011 #endif
3012
3013 /* MII transceiver control section.
3014 Read and write the MII registers using software-generated serial
3015 MDIO protocol. See the MII specifications or DP83840A data sheet
3016 for details. */
3017
3018 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3019 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3020 "overclocking" issues. */
3021 #define mdio_delay() ioread32(mdio_addr)
3022
3023 #define MDIO_SHIFT_CLK 0x01
3024 #define MDIO_DIR_WRITE 0x04
3025 #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3026 #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3027 #define MDIO_DATA_READ 0x02
3028 #define MDIO_ENB_IN 0x00
3029
3030 /* Generate the preamble required for initial synchronization and
3031 a few older transceivers. */
3032 static void mdio_sync(void __iomem *ioaddr, int bits)
3033 {
3034 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3035
3036 /* Establish sync by sending at least 32 logic ones. */
3037 while (-- bits >= 0) {
3038 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
3039 mdio_delay();
3040 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
3041 mdio_delay();
3042 }
3043 }
3044
3045 static int mdio_read(struct net_device *dev, int phy_id, int location)
3046 {
3047 int i;
3048 struct vortex_private *vp = netdev_priv(dev);
3049 void __iomem *ioaddr = vp->ioaddr;
3050 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3051 unsigned int retval = 0;
3052 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3053
3054 if (mii_preamble_required)
3055 mdio_sync(ioaddr, 32);
3056
3057 /* Shift the read command bits out. */
3058 for (i = 14; i >= 0; i--) {
3059 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3060 iowrite16(dataval, mdio_addr);
3061 mdio_delay();
3062 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
3063 mdio_delay();
3064 }
3065 /* Read the two transition, 16 data, and wire-idle bits. */
3066 for (i = 19; i > 0; i--) {
3067 iowrite16(MDIO_ENB_IN, mdio_addr);
3068 mdio_delay();
3069 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3070 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3071 mdio_delay();
3072 }
3073 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3074 }
3075
3076 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3077 {
3078 struct vortex_private *vp = netdev_priv(dev);
3079 void __iomem *ioaddr = vp->ioaddr;
3080 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3081 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3082 int i;
3083
3084 if (mii_preamble_required)
3085 mdio_sync(ioaddr, 32);
3086
3087 /* Shift the command bits out. */
3088 for (i = 31; i >= 0; i--) {
3089 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3090 iowrite16(dataval, mdio_addr);
3091 mdio_delay();
3092 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
3093 mdio_delay();
3094 }
3095 /* Leave the interface idle. */
3096 for (i = 1; i >= 0; i--) {
3097 iowrite16(MDIO_ENB_IN, mdio_addr);
3098 mdio_delay();
3099 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3100 mdio_delay();
3101 }
3102 return;
3103 }
3104
3105 /* ACPI: Advanced Configuration and Power Interface. */
3106 /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3107 static void acpi_set_WOL(struct net_device *dev)
3108 {
3109 struct vortex_private *vp = netdev_priv(dev);
3110 void __iomem *ioaddr = vp->ioaddr;
3111
3112 if (vp->enable_wol) {
3113 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3114 EL3WINDOW(7);
3115 iowrite16(2, ioaddr + 0x0c);
3116 /* The RxFilter must accept the WOL frames. */
3117 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3118 iowrite16(RxEnable, ioaddr + EL3_CMD);
3119
3120 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3121 printk(KERN_INFO "%s: WOL not supported.\n",
3122 pci_name(VORTEX_PCI(vp)));
3123
3124 vp->enable_wol = 0;
3125 return;
3126 }
3127
3128 /* Change the power state to D3; RxEnable doesn't take effect. */
3129 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3130 }
3131 }
3132
3133
3134 static void __devexit vortex_remove_one(struct pci_dev *pdev)
3135 {
3136 struct net_device *dev = pci_get_drvdata(pdev);
3137 struct vortex_private *vp;
3138
3139 if (!dev) {
3140 printk("vortex_remove_one called for Compaq device!\n");
3141 BUG();
3142 }
3143
3144 vp = netdev_priv(dev);
3145
3146 if (vp->cb_fn_base)
3147 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3148
3149 unregister_netdev(dev);
3150
3151 if (VORTEX_PCI(vp)) {
3152 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3153 if (vp->pm_state_valid)
3154 pci_restore_state(VORTEX_PCI(vp));
3155 pci_disable_device(VORTEX_PCI(vp));
3156 }
3157 /* Should really use issue_and_wait() here */
3158 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3159 vp->ioaddr + EL3_CMD);
3160
3161 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
3162
3163 pci_free_consistent(pdev,
3164 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3165 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3166 vp->rx_ring,
3167 vp->rx_ring_dma);
3168 if (vp->must_free_region)
3169 release_region(dev->base_addr, vp->io_size);
3170 free_netdev(dev);
3171 }
3172
3173
3174 static struct pci_driver vortex_driver = {
3175 .name = "3c59x",
3176 .probe = vortex_init_one,
3177 .remove = __devexit_p(vortex_remove_one),
3178 .id_table = vortex_pci_tbl,
3179 #ifdef CONFIG_PM
3180 .suspend = vortex_suspend,
3181 .resume = vortex_resume,
3182 #endif
3183 };
3184
3185
3186 static int vortex_have_pci;
3187 static int vortex_have_eisa;
3188
3189
3190 static int __init vortex_init(void)
3191 {
3192 int pci_rc, eisa_rc;
3193
3194 pci_rc = pci_register_driver(&vortex_driver);
3195 eisa_rc = vortex_eisa_init();
3196
3197 if (pci_rc == 0)
3198 vortex_have_pci = 1;
3199 if (eisa_rc > 0)
3200 vortex_have_eisa = 1;
3201
3202 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3203 }
3204
3205
3206 static void __exit vortex_eisa_cleanup(void)
3207 {
3208 struct vortex_private *vp;
3209 void __iomem *ioaddr;
3210
3211 #ifdef CONFIG_EISA
3212 /* Take care of the EISA devices */
3213 eisa_driver_unregister(&vortex_eisa_driver);
3214 #endif
3215
3216 if (compaq_net_device) {
3217 vp = compaq_net_device->priv;
3218 ioaddr = ioport_map(compaq_net_device->base_addr,
3219 VORTEX_TOTAL_SIZE);
3220
3221 unregister_netdev(compaq_net_device);
3222 iowrite16(TotalReset, ioaddr + EL3_CMD);
3223 release_region(compaq_net_device->base_addr,
3224 VORTEX_TOTAL_SIZE);
3225
3226 free_netdev(compaq_net_device);
3227 }
3228 }
3229
3230
3231 static void __exit vortex_cleanup(void)
3232 {
3233 if (vortex_have_pci)
3234 pci_unregister_driver(&vortex_driver);
3235 if (vortex_have_eisa)
3236 vortex_eisa_cleanup();
3237 }
3238
3239
3240 module_init(vortex_init);
3241 module_exit(vortex_cleanup);
3242
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