Linux kernel & device driver programming

Cross-Referenced Linux and Device Driver Code

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Version: [ 2.6.11.8 ] [ 2.6.25 ] [ 2.6.25.8 ] [ 2.6.31.13 ] Architecture: [ i386 ]
  1 /*
  2  *  drivers/mtd/nandids.c
  3  *
  4  *  Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de)
  5  *
  6  * $Id: nand_ids.c,v 1.16 2005/11/07 11:14:31 gleixner Exp $
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License version 2 as
 10  * published by the Free Software Foundation.
 11  *
 12  */
 13 #include <linux/module.h>
 14 #include <linux/mtd/nand.h>
 15 /*
 16 *       Chip ID list
 17 *
 18 *       Name. ID code, pagesize, chipsize in MegaByte, eraseblock size,
 19 *       options
 20 *
 21 *       Pagesize; 0, 256, 512
 22 *       0       get this information from the extended chip ID
 23 +       256     256 Byte page size
 24 *       512     512 Byte page size
 25 */
 26 struct nand_flash_dev nand_flash_ids[] = {
 27 
 28 #ifdef CONFIG_MTD_NAND_MUSEUM_IDS
 29         {"NAND 1MiB 5V 8-bit",          0x6e, 256, 1, 0x1000, 0},
 30         {"NAND 2MiB 5V 8-bit",          0x64, 256, 2, 0x1000, 0},
 31         {"NAND 4MiB 5V 8-bit",          0x6b, 512, 4, 0x2000, 0},
 32         {"NAND 1MiB 3,3V 8-bit",        0xe8, 256, 1, 0x1000, 0},
 33         {"NAND 1MiB 3,3V 8-bit",        0xec, 256, 1, 0x1000, 0},
 34         {"NAND 2MiB 3,3V 8-bit",        0xea, 256, 2, 0x1000, 0},
 35         {"NAND 4MiB 3,3V 8-bit",        0xd5, 512, 4, 0x2000, 0},
 36         {"NAND 4MiB 3,3V 8-bit",        0xe3, 512, 4, 0x2000, 0},
 37         {"NAND 4MiB 3,3V 8-bit",        0xe5, 512, 4, 0x2000, 0},
 38         {"NAND 8MiB 3,3V 8-bit",        0xd6, 512, 8, 0x2000, 0},
 39 
 40         {"NAND 8MiB 1,8V 8-bit",        0x39, 512, 8, 0x2000, 0},
 41         {"NAND 8MiB 3,3V 8-bit",        0xe6, 512, 8, 0x2000, 0},
 42         {"NAND 8MiB 1,8V 16-bit",       0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
 43         {"NAND 8MiB 3,3V 16-bit",       0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
 44 #endif
 45 
 46         {"NAND 16MiB 1,8V 8-bit",       0x33, 512, 16, 0x4000, 0},
 47         {"NAND 16MiB 3,3V 8-bit",       0x73, 512, 16, 0x4000, 0},
 48         {"NAND 16MiB 1,8V 16-bit",      0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
 49         {"NAND 16MiB 3,3V 16-bit",      0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
 50 
 51         {"NAND 32MiB 1,8V 8-bit",       0x35, 512, 32, 0x4000, 0},
 52         {"NAND 32MiB 3,3V 8-bit",       0x75, 512, 32, 0x4000, 0},
 53         {"NAND 32MiB 1,8V 16-bit",      0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
 54         {"NAND 32MiB 3,3V 16-bit",      0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
 55 
 56         {"NAND 64MiB 1,8V 8-bit",       0x36, 512, 64, 0x4000, 0},
 57         {"NAND 64MiB 3,3V 8-bit",       0x76, 512, 64, 0x4000, 0},
 58         {"NAND 64MiB 1,8V 16-bit",      0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
 59         {"NAND 64MiB 3,3V 16-bit",      0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
 60 
 61         {"NAND 128MiB 1,8V 8-bit",      0x78, 512, 128, 0x4000, 0},
 62         {"NAND 128MiB 1,8V 8-bit",      0x39, 512, 128, 0x4000, 0},
 63         {"NAND 128MiB 3,3V 8-bit",      0x79, 512, 128, 0x4000, 0},
 64         {"NAND 128MiB 1,8V 16-bit",     0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
 65         {"NAND 128MiB 1,8V 16-bit",     0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
 66         {"NAND 128MiB 3,3V 16-bit",     0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
 67         {"NAND 128MiB 3,3V 16-bit",     0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
 68 
 69         {"NAND 256MiB 3,3V 8-bit",      0x71, 512, 256, 0x4000, 0},
 70 
 71         /*
 72          * These are the new chips with large page size. The pagesize and the
 73          * erasesize is determined from the extended id bytes
 74          */
 75 #define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR)
 76 #define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
 77 
 78         /*512 Megabit */
 79         {"NAND 64MiB 1,8V 8-bit",       0xA2, 0,  64, 0, LP_OPTIONS},
 80         {"NAND 64MiB 3,3V 8-bit",       0xF2, 0,  64, 0, LP_OPTIONS},
 81         {"NAND 64MiB 1,8V 16-bit",      0xB2, 0,  64, 0, LP_OPTIONS16},
 82         {"NAND 64MiB 3,3V 16-bit",      0xC2, 0,  64, 0, LP_OPTIONS16},
 83 
 84         /* 1 Gigabit */
 85         {"NAND 128MiB 1,8V 8-bit",      0xA1, 0, 128, 0, LP_OPTIONS},
 86         {"NAND 128MiB 3,3V 8-bit",      0xF1, 0, 128, 0, LP_OPTIONS},
 87         {"NAND 128MiB 1,8V 16-bit",     0xB1, 0, 128, 0, LP_OPTIONS16},
 88         {"NAND 128MiB 3,3V 16-bit",     0xC1, 0, 128, 0, LP_OPTIONS16},
 89 
 90         /* 2 Gigabit */
 91         {"NAND 256MiB 1,8V 8-bit",      0xAA, 0, 256, 0, LP_OPTIONS},
 92         {"NAND 256MiB 3,3V 8-bit",      0xDA, 0, 256, 0, LP_OPTIONS},
 93         {"NAND 256MiB 1,8V 16-bit",     0xBA, 0, 256, 0, LP_OPTIONS16},
 94         {"NAND 256MiB 3,3V 16-bit",     0xCA, 0, 256, 0, LP_OPTIONS16},
 95 
 96         /* 4 Gigabit */
 97         {"NAND 512MiB 1,8V 8-bit",      0xAC, 0, 512, 0, LP_OPTIONS},
 98         {"NAND 512MiB 3,3V 8-bit",      0xDC, 0, 512, 0, LP_OPTIONS},
 99         {"NAND 512MiB 1,8V 16-bit",     0xBC, 0, 512, 0, LP_OPTIONS16},
100         {"NAND 512MiB 3,3V 16-bit",     0xCC, 0, 512, 0, LP_OPTIONS16},
101 
102         /* 8 Gigabit */
103         {"NAND 1GiB 1,8V 8-bit",        0xA3, 0, 1024, 0, LP_OPTIONS},
104         {"NAND 1GiB 3,3V 8-bit",        0xD3, 0, 1024, 0, LP_OPTIONS},
105         {"NAND 1GiB 1,8V 16-bit",       0xB3, 0, 1024, 0, LP_OPTIONS16},
106         {"NAND 1GiB 3,3V 16-bit",       0xC3, 0, 1024, 0, LP_OPTIONS16},
107 
108         /* 16 Gigabit */
109         {"NAND 2GiB 1,8V 8-bit",        0xA5, 0, 2048, 0, LP_OPTIONS},
110         {"NAND 2GiB 3,3V 8-bit",        0xD5, 0, 2048, 0, LP_OPTIONS},
111         {"NAND 2GiB 1,8V 16-bit",       0xB5, 0, 2048, 0, LP_OPTIONS16},
112         {"NAND 2GiB 3,3V 16-bit",       0xC5, 0, 2048, 0, LP_OPTIONS16},
113 
114         /*
115          * Renesas AND 1 Gigabit. Those chips do not support extended id and
116          * have a strange page/block layout !  The chosen minimum erasesize is
117          * 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page
118          * planes 1 block = 2 pages, but due to plane arrangement the blocks
119          * 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7 Anyway JFFS2 would
120          * increase the eraseblock size so we chose a combined one which can be
121          * erased in one go There are more speed improvements for reads and
122          * writes possible, but not implemented now
123          */
124         {"AND 128MiB 3,3V 8-bit",       0x01, 2048, 128, 0x4000,
125          NAND_IS_AND | NAND_NO_AUTOINCR |NAND_NO_READRDY | NAND_4PAGE_ARRAY |
126          BBT_AUTO_REFRESH
127         },
128 
129         {NULL,}
130 };
131 
132 /*
133 *       Manufacturer ID list
134 */
135 struct nand_manufacturers nand_manuf_ids[] = {
136         {NAND_MFR_TOSHIBA, "Toshiba"},
137         {NAND_MFR_SAMSUNG, "Samsung"},
138         {NAND_MFR_FUJITSU, "Fujitsu"},
139         {NAND_MFR_NATIONAL, "National"},
140         {NAND_MFR_RENESAS, "Renesas"},
141         {NAND_MFR_STMICRO, "ST Micro"},
142         {NAND_MFR_HYNIX, "Hynix"},
143         {NAND_MFR_MICRON, "Micron"},
144         {NAND_MFR_AMD, "AMD"},
145         {0x0, "Unknown"}
146 };
147 
148 EXPORT_SYMBOL(nand_manuf_ids);
149 EXPORT_SYMBOL(nand_flash_ids);
150 
151 MODULE_LICENSE("GPL");
152 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
153 MODULE_DESCRIPTION("Nand device & manufacturer IDs");
154 
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