1 /*
2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 */
11
12 /*
13 * PCI registers
14 */
15
16 #define PCI_SDHCI_IFPIO 0x00
17 #define PCI_SDHCI_IFDMA 0x01
18 #define PCI_SDHCI_IFVENDOR 0x02
19
20 #define PCI_SLOT_INFO 0x40 /* 8 bits */
21 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
22 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
23
24 /*
25 * Controller registers
26 */
27
28 #define SDHCI_DMA_ADDRESS 0x00
29
30 #define SDHCI_BLOCK_SIZE 0x04
31 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
32
33 #define SDHCI_BLOCK_COUNT 0x06
34
35 #define SDHCI_ARGUMENT 0x08
36
37 #define SDHCI_TRANSFER_MODE 0x0C
38 #define SDHCI_TRNS_DMA 0x01
39 #define SDHCI_TRNS_BLK_CNT_EN 0x02
40 #define SDHCI_TRNS_ACMD12 0x04
41 #define SDHCI_TRNS_READ 0x10
42 #define SDHCI_TRNS_MULTI 0x20
43
44 #define SDHCI_COMMAND 0x0E
45 #define SDHCI_CMD_RESP_MASK 0x03
46 #define SDHCI_CMD_CRC 0x08
47 #define SDHCI_CMD_INDEX 0x10
48 #define SDHCI_CMD_DATA 0x20
49
50 #define SDHCI_CMD_RESP_NONE 0x00
51 #define SDHCI_CMD_RESP_LONG 0x01
52 #define SDHCI_CMD_RESP_SHORT 0x02
53 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
54
55 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
56
57 #define SDHCI_RESPONSE 0x10
58
59 #define SDHCI_BUFFER 0x20
60
61 #define SDHCI_PRESENT_STATE 0x24
62 #define SDHCI_CMD_INHIBIT 0x00000001
63 #define SDHCI_DATA_INHIBIT 0x00000002
64 #define SDHCI_DOING_WRITE 0x00000100
65 #define SDHCI_DOING_READ 0x00000200
66 #define SDHCI_SPACE_AVAILABLE 0x00000400
67 #define SDHCI_DATA_AVAILABLE 0x00000800
68 #define SDHCI_CARD_PRESENT 0x00010000
69 #define SDHCI_WRITE_PROTECT 0x00080000
70
71 #define SDHCI_HOST_CONTROL 0x28
72 #define SDHCI_CTRL_LED 0x01
73 #define SDHCI_CTRL_4BITBUS 0x02
74 #define SDHCI_CTRL_HISPD 0x04
75
76 #define SDHCI_POWER_CONTROL 0x29
77 #define SDHCI_POWER_ON 0x01
78 #define SDHCI_POWER_180 0x0A
79 #define SDHCI_POWER_300 0x0C
80 #define SDHCI_POWER_330 0x0E
81
82 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
83
84 #define SDHCI_WAKE_UP_CONTROL 0x2B
85
86 #define SDHCI_CLOCK_CONTROL 0x2C
87 #define SDHCI_DIVIDER_SHIFT 8
88 #define SDHCI_CLOCK_CARD_EN 0x0004
89 #define SDHCI_CLOCK_INT_STABLE 0x0002
90 #define SDHCI_CLOCK_INT_EN 0x0001
91
92 #define SDHCI_TIMEOUT_CONTROL 0x2E
93
94 #define SDHCI_SOFTWARE_RESET 0x2F
95 #define SDHCI_RESET_ALL 0x01
96 #define SDHCI_RESET_CMD 0x02
97 #define SDHCI_RESET_DATA 0x04
98
99 #define SDHCI_INT_STATUS 0x30
100 #define SDHCI_INT_ENABLE 0x34
101 #define SDHCI_SIGNAL_ENABLE 0x38
102 #define SDHCI_INT_RESPONSE 0x00000001
103 #define SDHCI_INT_DATA_END 0x00000002
104 #define SDHCI_INT_DMA_END 0x00000008
105 #define SDHCI_INT_SPACE_AVAIL 0x00000010
106 #define SDHCI_INT_DATA_AVAIL 0x00000020
107 #define SDHCI_INT_CARD_INSERT 0x00000040
108 #define SDHCI_INT_CARD_REMOVE 0x00000080
109 #define SDHCI_INT_CARD_INT 0x00000100
110 #define SDHCI_INT_ERROR 0x00008000
111 #define SDHCI_INT_TIMEOUT 0x00010000
112 #define SDHCI_INT_CRC 0x00020000
113 #define SDHCI_INT_END_BIT 0x00040000
114 #define SDHCI_INT_INDEX 0x00080000
115 #define SDHCI_INT_DATA_TIMEOUT 0x00100000
116 #define SDHCI_INT_DATA_CRC 0x00200000
117 #define SDHCI_INT_DATA_END_BIT 0x00400000
118 #define SDHCI_INT_BUS_POWER 0x00800000
119 #define SDHCI_INT_ACMD12ERR 0x01000000
120
121 #define SDHCI_INT_NORMAL_MASK 0x00007FFF
122 #define SDHCI_INT_ERROR_MASK 0xFFFF8000
123
124 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
125 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
126 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
127 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
128 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
129 SDHCI_INT_DATA_END_BIT)
130
131 #define SDHCI_ACMD12_ERR 0x3C
132
133 /* 3E-3F reserved */
134
135 #define SDHCI_CAPABILITIES 0x40
136 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
137 #define SDHCI_TIMEOUT_CLK_SHIFT 0
138 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
139 #define SDHCI_CLOCK_BASE_MASK 0x00003F00
140 #define SDHCI_CLOCK_BASE_SHIFT 8
141 #define SDHCI_MAX_BLOCK_MASK 0x00030000
142 #define SDHCI_MAX_BLOCK_SHIFT 16
143 #define SDHCI_CAN_DO_HISPD 0x00200000
144 #define SDHCI_CAN_DO_DMA 0x00400000
145 #define SDHCI_CAN_VDD_330 0x01000000
146 #define SDHCI_CAN_VDD_300 0x02000000
147 #define SDHCI_CAN_VDD_180 0x04000000
148
149 /* 44-47 reserved for more caps */
150
151 #define SDHCI_MAX_CURRENT 0x48
152
153 /* 4C-4F reserved for more max current */
154
155 /* 50-FB reserved */
156
157 #define SDHCI_SLOT_INT_STATUS 0xFC
158
159 #define SDHCI_HOST_VERSION 0xFE
160 #define SDHCI_VENDOR_VER_MASK 0xFF00
161 #define SDHCI_VENDOR_VER_SHIFT 8
162 #define SDHCI_SPEC_VER_MASK 0x00FF
163 #define SDHCI_SPEC_VER_SHIFT 0
164
165 struct sdhci_chip;
166
167 struct sdhci_host {
168 struct sdhci_chip *chip;
169 struct mmc_host *mmc; /* MMC structure */
170
171 spinlock_t lock; /* Mutex */
172
173 int flags; /* Host attributes */
174 #define SDHCI_USE_DMA (1<<0) /* Host is DMA capable */
175 #define SDHCI_REQ_USE_DMA (1<<1) /* Use DMA for this req. */
176
177 unsigned int max_clk; /* Max possible freq (MHz) */
178 unsigned int timeout_clk; /* Timeout freq (KHz) */
179
180 unsigned int clock; /* Current clock (MHz) */
181 unsigned short power; /* Current voltage */
182
183 struct mmc_request *mrq; /* Current request */
184 struct mmc_command *cmd; /* Current command */
185 struct mmc_data *data; /* Current data request */
186 int data_early:1; /* Data finished before cmd */
187
188 struct scatterlist *cur_sg; /* We're working on this */
189 int num_sg; /* Entries left */
190 int offset; /* Offset into current sg */
191 int remain; /* Bytes left in current */
192
193 char slot_descr[20]; /* Name for reservations */
194
195 int irq; /* Device IRQ */
196 int bar; /* PCI BAR index */
197 unsigned long addr; /* Bus address */
198 void __iomem * ioaddr; /* Mapped address */
199
200 struct tasklet_struct card_tasklet; /* Tasklet structures */
201 struct tasklet_struct finish_tasklet;
202
203 struct timer_list timer; /* Timer for timeouts */
204 };
205
206 struct sdhci_chip {
207 struct pci_dev *pdev;
208
209 unsigned long quirks;
210
211 int index; /* Index for chip0, chip1 ...*/
212 int num_slots; /* Slots on controller */
213 struct sdhci_host *hosts[0]; /* Pointers to hosts */
214 };
215
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