1 #define EM_GPIO_0 (1 << 0)
2 #define EM_GPIO_1 (1 << 1)
3 #define EM_GPIO_2 (1 << 2)
4 #define EM_GPIO_3 (1 << 3)
5 #define EM_GPIO_4 (1 << 4)
6 #define EM_GPIO_5 (1 << 5)
7 #define EM_GPIO_6 (1 << 6)
8 #define EM_GPIO_7 (1 << 7)
9
10 #define EM_GPO_0 (1 << 0)
11 #define EM_GPO_1 (1 << 1)
12 #define EM_GPO_2 (1 << 2)
13 #define EM_GPO_3 (1 << 3)
14
15 /* em2800 registers */
16 #define EM2800_R08_AUDIOSRC 0x08
17
18 /* em28xx registers */
19
20 #define EM28XX_R00_CHIPCFG 0x00
21
22 /* em28xx Chip Configuration 0x00 */
23 #define EM28XX_CHIPCFG_VENDOR_AUDIO 0x80
24 #define EM28XX_CHIPCFG_I2S_VOLUME_CAPABLE 0x40
25 #define EM28XX_CHIPCFG_I2S_5_SAMPRATES 0x30
26 #define EM28XX_CHIPCFG_I2S_3_SAMPRATES 0x20
27 #define EM28XX_CHIPCFG_AC97 0x10
28 #define EM28XX_CHIPCFG_AUDIOMASK 0x30
29
30 #define EM28XX_R01_CHIPCFG2 0x01
31
32 /* em28xx Chip Configuration 2 0x01 */
33 #define EM28XX_CHIPCFG2_TS_PRESENT 0x10
34 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_MASK 0x0c /* bits 3-2 */
35 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_1MF 0x00
36 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_2MF 0x04
37 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_4MF 0x08
38 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_8MF 0x0c
39 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK 0x03 /* bits 0-1 */
40 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_188 0x00
41 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_376 0x01
42 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_564 0x02
43 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_752 0x03
44
45
46 /* GPIO/GPO registers */
47 #define EM2880_R04_GPO 0x04 /* em2880-em2883 only */
48 #define EM28XX_R08_GPIO 0x08 /* em2820 or upper */
49
50 #define EM28XX_R06_I2C_CLK 0x06
51
52 /* em28xx I2C Clock Register (0x06) */
53 #define EM28XX_I2C_CLK_ACK_LAST_READ 0x80
54 #define EM28XX_I2C_CLK_WAIT_ENABLE 0x40
55 #define EM28XX_I2C_EEPROM_ON_BOARD 0x08
56 #define EM28XX_I2C_EEPROM_KEY_VALID 0x04
57 #define EM2874_I2C_SECONDARY_BUS_SELECT 0x04 /* em2874 has two i2c busses */
58 #define EM28XX_I2C_FREQ_1_5_MHZ 0x03 /* bus frequency (bits [1-0]) */
59 #define EM28XX_I2C_FREQ_25_KHZ 0x02
60 #define EM28XX_I2C_FREQ_400_KHZ 0x01
61 #define EM28XX_I2C_FREQ_100_KHZ 0x00
62
63
64 #define EM28XX_R0A_CHIPID 0x0a
65 #define EM28XX_R0C_USBSUSP 0x0c /* */
66
67 #define EM28XX_R0E_AUDIOSRC 0x0e
68 #define EM28XX_R0F_XCLK 0x0f
69
70 /* em28xx XCLK Register (0x0f) */
71 #define EM28XX_XCLK_AUDIO_UNMUTE 0x80 /* otherwise audio muted */
72 #define EM28XX_XCLK_I2S_MSB_TIMING 0x40 /* otherwise standard timing */
73 #define EM28XX_XCLK_IR_RC5_MODE 0x20 /* otherwise NEC mode */
74 #define EM28XX_XCLK_IR_NEC_CHK_PARITY 0x10
75 #define EM28XX_XCLK_FREQUENCY_30MHZ 0x00 /* Freq. select (bits [3-0]) */
76 #define EM28XX_XCLK_FREQUENCY_15MHZ 0x01
77 #define EM28XX_XCLK_FREQUENCY_10MHZ 0x02
78 #define EM28XX_XCLK_FREQUENCY_7_5MHZ 0x03
79 #define EM28XX_XCLK_FREQUENCY_6MHZ 0x04
80 #define EM28XX_XCLK_FREQUENCY_5MHZ 0x05
81 #define EM28XX_XCLK_FREQUENCY_4_3MHZ 0x06
82 #define EM28XX_XCLK_FREQUENCY_12MHZ 0x07
83 #define EM28XX_XCLK_FREQUENCY_20MHZ 0x08
84 #define EM28XX_XCLK_FREQUENCY_20MHZ_2 0x09
85 #define EM28XX_XCLK_FREQUENCY_48MHZ 0x0a
86 #define EM28XX_XCLK_FREQUENCY_24MHZ 0x0b
87
88 #define EM28XX_R10_VINMODE 0x10
89 #define EM28XX_R11_VINCTRL 0x11
90 #define EM28XX_R12_VINENABLE 0x12 /* */
91
92 #define EM28XX_R14_GAMMA 0x14
93 #define EM28XX_R15_RGAIN 0x15
94 #define EM28XX_R16_GGAIN 0x16
95 #define EM28XX_R17_BGAIN 0x17
96 #define EM28XX_R18_ROFFSET 0x18
97 #define EM28XX_R19_GOFFSET 0x19
98 #define EM28XX_R1A_BOFFSET 0x1a
99
100 #define EM28XX_R1B_OFLOW 0x1b
101 #define EM28XX_R1C_HSTART 0x1c
102 #define EM28XX_R1D_VSTART 0x1d
103 #define EM28XX_R1E_CWIDTH 0x1e
104 #define EM28XX_R1F_CHEIGHT 0x1f
105
106 #define EM28XX_R20_YGAIN 0x20
107 #define EM28XX_R21_YOFFSET 0x21
108 #define EM28XX_R22_UVGAIN 0x22
109 #define EM28XX_R23_UOFFSET 0x23
110 #define EM28XX_R24_VOFFSET 0x24
111 #define EM28XX_R25_SHARPNESS 0x25
112
113 #define EM28XX_R26_COMPR 0x26
114 #define EM28XX_R27_OUTFMT 0x27
115
116 /* em28xx Output Format Register (0x27) */
117 #define EM28XX_OUTFMT_RGB_8_RGRG 0x00
118 #define EM28XX_OUTFMT_RGB_8_GRGR 0x01
119 #define EM28XX_OUTFMT_RGB_8_GBGB 0x02
120 #define EM28XX_OUTFMT_RGB_8_BGBG 0x03
121 #define EM28XX_OUTFMT_RGB_16_656 0x04
122 #define EM28XX_OUTFMT_RGB_8_BAYER 0x08 /* Pattern in Reg 0x10[1-0] */
123 #define EM28XX_OUTFMT_YUV211 0x10
124 #define EM28XX_OUTFMT_YUV422_Y0UY1V 0x14
125 #define EM28XX_OUTFMT_YUV422_Y1UY0V 0x15
126 #define EM28XX_OUTFMT_YUV411 0x18
127
128
129 #define EM28XX_R28_XMIN 0x28
130 #define EM28XX_R29_XMAX 0x29
131 #define EM28XX_R2A_YMIN 0x2a
132 #define EM28XX_R2B_YMAX 0x2b
133
134 #define EM28XX_R30_HSCALELOW 0x30
135 #define EM28XX_R31_HSCALEHIGH 0x31
136 #define EM28XX_R32_VSCALELOW 0x32
137 #define EM28XX_R33_VSCALEHIGH 0x33
138
139 #define EM28XX_R40_AC97LSB 0x40
140 #define EM28XX_R41_AC97MSB 0x41
141 #define EM28XX_R42_AC97ADDR 0x42
142 #define EM28XX_R43_AC97BUSY 0x43
143
144 #define EM28XX_R45_IR 0x45
145 /* 0x45 bit 7 - parity bit
146 bits 6-0 - count
147 0x46 IR brand
148 0x47 IR data
149 */
150
151 /* em2874 registers */
152 #define EM2874_R50_IR_CONFIG 0x50
153 #define EM2874_R51_IR 0x51
154 #define EM2874_R5F_TS_ENABLE 0x5f
155 #define EM2874_R80_GPIO 0x80
156
157 /* em2874 IR config register (0x50) */
158 #define EM2874_IR_NEC 0x00
159 #define EM2874_IR_RC5 0x04
160 #define EM2874_IR_RC5_MODE_0 0x08
161 #define EM2874_IR_RC5_MODE_6A 0x0b
162
163 /* em2874 Transport Stream Enable Register (0x5f) */
164 #define EM2874_TS1_CAPTURE_ENABLE (1 << 0)
165 #define EM2874_TS1_FILTER_ENABLE (1 << 1)
166 #define EM2874_TS1_NULL_DISCARD (1 << 2)
167 #define EM2874_TS2_CAPTURE_ENABLE (1 << 4)
168 #define EM2874_TS2_FILTER_ENABLE (1 << 5)
169 #define EM2874_TS2_NULL_DISCARD (1 << 6)
170
171 /* register settings */
172 #define EM2800_AUDIO_SRC_TUNER 0x0d
173 #define EM2800_AUDIO_SRC_LINE 0x0c
174 #define EM28XX_AUDIO_SRC_TUNER 0xc0
175 #define EM28XX_AUDIO_SRC_LINE 0x80
176
177 /* FIXME: Need to be populated with the other chip ID's */
178 enum em28xx_chip_id {
179 CHIP_ID_EM2710 = 17,
180 CHIP_ID_EM2820 = 18, /* Also used by some em2710 */
181 CHIP_ID_EM2840 = 20,
182 CHIP_ID_EM2750 = 33,
183 CHIP_ID_EM2860 = 34,
184 CHIP_ID_EM2870 = 35,
185 CHIP_ID_EM2883 = 36,
186 CHIP_ID_EM2874 = 65,
187 };
188
189 /*
190 * Registers used by em202 and other AC97 chips
191 */
192
193 /* Standard AC97 registers */
194 #define AC97_RESET 0x00
195
196 /* Output volumes */
197 #define AC97_MASTER_VOL 0x02
198 #define AC97_LINE_LEVEL_VOL 0x04 /* Some devices use for headphones */
199 #define AC97_MASTER_MONO_VOL 0x06
200
201 /* Input volumes */
202 #define AC97_PC_BEEP_VOL 0x0a
203 #define AC97_PHONE_VOL 0x0c
204 #define AC97_MIC_VOL 0x0e
205 #define AC97_LINEIN_VOL 0x10
206 #define AC97_CD_VOL 0x12
207 #define AC97_VIDEO_VOL 0x14
208 #define AC97_AUX_VOL 0x16
209 #define AC97_PCM_OUT_VOL 0x18
210
211 /* capture registers */
212 #define AC97_RECORD_SELECT 0x1a
213 #define AC97_RECORD_GAIN 0x1c
214
215 /* control registers */
216 #define AC97_GENERAL_PURPOSE 0x20
217 #define AC97_3D_CTRL 0x22
218 #define AC97_AUD_INT_AND_PAG 0x24
219 #define AC97_POWER_DOWN_CTRL 0x26
220 #define AC97_EXT_AUD_ID 0x28
221 #define AC97_EXT_AUD_CTRL 0x2a
222
223 /* Supported rate varies for each AC97 device
224 if write an unsupported value, it will return the closest one
225 */
226 #define AC97_PCM_OUT_FRONT_SRATE 0x2c
227 #define AC97_PCM_OUT_SURR_SRATE 0x2e
228 #define AC97_PCM_OUT_LFE_SRATE 0x30
229 #define AC97_PCM_IN_SRATE 0x32
230
231 /* For devices with more than 2 channels, extra output volumes */
232 #define AC97_LFE_MASTER_VOL 0x36
233 #define AC97_SURR_MASTER_VOL 0x38
234
235 /* Digital SPDIF output control */
236 #define AC97_SPDIF_OUT_CTRL 0x3a
237
238 /* Vendor ID identifier */
239 #define AC97_VENDOR_ID1 0x7c
240 #define AC97_VENDOR_ID2 0x7e
241
242 /* EMP202 vendor registers */
243 #define EM202_EXT_MODEM_CTRL 0x3e
244 #define EM202_GPIO_CONF 0x4c
245 #define EM202_GPIO_POLARITY 0x4e
246 #define EM202_GPIO_STICKY 0x50
247 #define EM202_GPIO_MASK 0x52
248 #define EM202_GPIO_STATUS 0x54
249 #define EM202_SPDIF_OUT_SEL 0x6a
250 #define EM202_ANTIPOP 0x72
251 #define EM202_EAPD_GPIO_ACCESS 0x74
252
|
This page was automatically generated by the
LXR engine.
|