1 /*
2 Driver for VES1893 and VES1993 QPSK Demodulators
3
4 Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
5 Copyright (C) 2001 Ronny Strutz <3des@elitedvb.de>
6 Copyright (C) 2002 Dennis Noermann <dennis.noermann@noernet.de>
7 Copyright (C) 2002-2003 Andreas Oberritter <obi@linuxtv.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/string.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32
33 #include "dvb_frontend.h"
34 #include "ves1x93.h"
35
36
37 struct ves1x93_state {
38
39 struct i2c_adapter* i2c;
40
41 struct dvb_frontend_ops ops;
42
43 /* configuration settings */
44 const struct ves1x93_config* config;
45
46 struct dvb_frontend frontend;
47
48 /* previous uncorrected block counter */
49 fe_spectral_inversion_t inversion;
50 u8 *init_1x93_tab;
51 u8 *init_1x93_wtab;
52 u8 tab_size;
53 u8 demod_type;
54 };
55
56 static int debug = 0;
57 #define dprintk if (debug) printk
58
59 #define DEMOD_VES1893 0
60 #define DEMOD_VES1993 1
61
62 static u8 init_1893_tab [] = {
63 0x01, 0xa4, 0x35, 0x80, 0x2a, 0x0b, 0x55, 0xc4,
64 0x09, 0x69, 0x00, 0x86, 0x4c, 0x28, 0x7f, 0x00,
65 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
66 0x80, 0x00, 0x21, 0xb0, 0x14, 0x00, 0xdc, 0x00,
67 0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
68 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
69 0x00, 0x55, 0x00, 0x00, 0x7f, 0x00
70 };
71
72
73 static u8 init_1993_tab [] = {
74 0x00, 0x9c, 0x35, 0x80, 0x6a, 0x09, 0x72, 0x8c,
75 0x09, 0x6b, 0x00, 0x00, 0x4c, 0x08, 0x00, 0x00,
76 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
77 0x80, 0x40, 0x21, 0xb0, 0x00, 0x00, 0x00, 0x10,
78 0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
79 0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
80 0x00, 0x55, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03,
81 0x00, 0x00, 0x0e, 0x80, 0x00
82 };
83
84 static u8 init_1893_wtab[] =
85 {
86 1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0,
87 0,1,0,0,0,0,0,0, 1,0,1,1,0,0,0,1,
88 1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0,
89 1,1,1,0,1,1
90 };
91
92
93 static u8 init_1993_wtab[] =
94 {
95 1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0,
96 0,1,0,0,0,0,0,0, 1,1,1,1,0,0,0,1,
97 1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0,
98 1,1,1,0,1,1,1,1, 1,1,1,1,1
99 };
100
101 static int ves1x93_writereg (struct ves1x93_state* state, u8 reg, u8 data)
102 {
103 u8 buf [] = { 0x00, reg, data };
104 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 3 };
105 int err;
106
107 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
108 dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __FUNCTION__, err, reg, data);
109 return -EREMOTEIO;
110 }
111
112 return 0;
113 }
114
115
116 static u8 ves1x93_readreg (struct ves1x93_state* state, u8 reg)
117 {
118 int ret;
119 u8 b0 [] = { 0x00, reg };
120 u8 b1 [] = { 0 };
121 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 },
122 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
123
124 ret = i2c_transfer (state->i2c, msg, 2);
125
126 if (ret != 2) return ret;
127
128 return b1[0];
129 }
130
131 static int ves1x93_clr_bit (struct ves1x93_state* state)
132 {
133 msleep(10);
134 ves1x93_writereg (state, 0, state->init_1x93_tab[0] & 0xfe);
135 ves1x93_writereg (state, 0, state->init_1x93_tab[0]);
136 msleep(50);
137 return 0;
138 }
139
140 static int ves1x93_set_inversion (struct ves1x93_state* state, fe_spectral_inversion_t inversion)
141 {
142 u8 val;
143
144 /*
145 * inversion on/off are interchanged because i and q seem to
146 * be swapped on the hardware
147 */
148
149 switch (inversion) {
150 case INVERSION_OFF:
151 val = 0xc0;
152 break;
153 case INVERSION_ON:
154 val = 0x80;
155 break;
156 case INVERSION_AUTO:
157 val = 0x00;
158 break;
159 default:
160 return -EINVAL;
161 }
162
163 return ves1x93_writereg (state, 0x0c, (state->init_1x93_tab[0x0c] & 0x3f) | val);
164 }
165
166
167 static int ves1x93_set_fec (struct ves1x93_state* state, fe_code_rate_t fec)
168 {
169 if (fec == FEC_AUTO)
170 return ves1x93_writereg (state, 0x0d, 0x08);
171 else if (fec < FEC_1_2 || fec > FEC_8_9)
172 return -EINVAL;
173 else
174 return ves1x93_writereg (state, 0x0d, fec - FEC_1_2);
175 }
176
177
178 static fe_code_rate_t ves1x93_get_fec (struct ves1x93_state* state)
179 {
180 return FEC_1_2 + ((ves1x93_readreg (state, 0x0d) >> 4) & 0x7);
181 }
182
183
184 static int ves1x93_set_symbolrate (struct ves1x93_state* state, u32 srate)
185 {
186 u32 BDR;
187 u32 ratio;
188 u8 ADCONF, FCONF, FNR;
189 u32 BDRI;
190 u32 tmp;
191 u32 FIN;
192
193 dprintk("%s: srate == %d\n", __FUNCTION__, (unsigned int) srate);
194
195 if (srate > state->config->xin/2)
196 srate = state->config->xin/2;
197
198 if (srate < 500000)
199 srate = 500000;
200
201 #define MUL (1UL<<26)
202
203 FIN = (state->config->xin + 6000) >> 4;
204
205 tmp = srate << 6;
206 ratio = tmp / FIN;
207
208 tmp = (tmp % FIN) << 8;
209 ratio = (ratio << 8) + tmp / FIN;
210
211 tmp = (tmp % FIN) << 8;
212 ratio = (ratio << 8) + tmp / FIN;
213
214 FNR = 0xff;
215
216 if (ratio < MUL/3) FNR = 0;
217 if (ratio < (MUL*11)/50) FNR = 1;
218 if (ratio < MUL/6) FNR = 2;
219 if (ratio < MUL/9) FNR = 3;
220 if (ratio < MUL/12) FNR = 4;
221 if (ratio < (MUL*11)/200) FNR = 5;
222 if (ratio < MUL/24) FNR = 6;
223 if (ratio < (MUL*27)/1000) FNR = 7;
224 if (ratio < MUL/48) FNR = 8;
225 if (ratio < (MUL*137)/10000) FNR = 9;
226
227 if (FNR == 0xff) {
228 ADCONF = 0x89;
229 FCONF = 0x80;
230 FNR = 0;
231 } else {
232 ADCONF = 0x81;
233 FCONF = 0x88 | (FNR >> 1) | ((FNR & 0x01) << 5);
234 /*FCONF = 0x80 | ((FNR & 0x01) << 5) | (((FNR > 1) & 0x03) << 3) | ((FNR >> 1) & 0x07);*/
235 }
236
237 BDR = (( (ratio << (FNR >> 1)) >> 4) + 1) >> 1;
238 BDRI = ( ((FIN << 8) / ((srate << (FNR >> 1)) >> 2)) + 1) >> 1;
239
240 dprintk("FNR= %d\n", FNR);
241 dprintk("ratio= %08x\n", (unsigned int) ratio);
242 dprintk("BDR= %08x\n", (unsigned int) BDR);
243 dprintk("BDRI= %02x\n", (unsigned int) BDRI);
244
245 if (BDRI > 0xff)
246 BDRI = 0xff;
247
248 ves1x93_writereg (state, 0x06, 0xff & BDR);
249 ves1x93_writereg (state, 0x07, 0xff & (BDR >> 8));
250 ves1x93_writereg (state, 0x08, 0x0f & (BDR >> 16));
251
252 ves1x93_writereg (state, 0x09, BDRI);
253 ves1x93_writereg (state, 0x20, ADCONF);
254 ves1x93_writereg (state, 0x21, FCONF);
255
256 if (srate < 6000000)
257 ves1x93_writereg (state, 0x05, state->init_1x93_tab[0x05] | 0x80);
258 else
259 ves1x93_writereg (state, 0x05, state->init_1x93_tab[0x05] & 0x7f);
260
261 /* ves1993 hates this, will lose lock */
262 if (state->demod_type != DEMOD_VES1993)
263 ves1x93_clr_bit (state);
264
265 return 0;
266 }
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282 static int ves1x93_init (struct dvb_frontend* fe)
283 {
284 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
285 int i;
286 int val;
287
288 dprintk("%s: init chip\n", __FUNCTION__);
289
290 for (i = 0; i < state->tab_size; i++) {
291 if (state->init_1x93_wtab[i]) {
292 val = state->init_1x93_tab[i];
293
294 if (state->config->invert_pwm && (i == 0x05)) val |= 0x20; /* invert PWM */
295 ves1x93_writereg (state, i, val);
296 }
297 }
298
299 if (state->config->pll_init) {
300 ves1x93_writereg(state, 0x00, 0x11);
301 state->config->pll_init(fe);
302 ves1x93_writereg(state, 0x00, 0x01);
303 }
304
305 return 0;
306 }
307
308 static int ves1x93_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage)
309 {
310 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
311
312 switch (voltage) {
313 case SEC_VOLTAGE_13:
314 return ves1x93_writereg (state, 0x1f, 0x20);
315 case SEC_VOLTAGE_18:
316 return ves1x93_writereg (state, 0x1f, 0x30);
317 case SEC_VOLTAGE_OFF:
318 return ves1x93_writereg (state, 0x1f, 0x00);
319 default:
320 return -EINVAL;
321 }
322 }
323
324 static int ves1x93_read_status(struct dvb_frontend* fe, fe_status_t* status)
325 {
326 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
327
328 u8 sync = ves1x93_readreg (state, 0x0e);
329
330 /*
331 * The ves1893 sometimes returns sync values that make no sense,
332 * because, e.g., the SIGNAL bit is 0, while some of the higher
333 * bits are 1 (and how can there be a CARRIER w/o a SIGNAL?).
334 * Tests showed that the the VITERBI and SYNC bits are returned
335 * reliably, while the SIGNAL and CARRIER bits ar sometimes wrong.
336 * If such a case occurs, we read the value again, until we get a
337 * valid value.
338 */
339 int maxtry = 10; /* just for safety - let's not get stuck here */
340 while ((sync & 0x03) != 0x03 && (sync & 0x0c) && maxtry--) {
341 msleep(10);
342 sync = ves1x93_readreg (state, 0x0e);
343 }
344
345 *status = 0;
346
347 if (sync & 1)
348 *status |= FE_HAS_SIGNAL;
349
350 if (sync & 2)
351 *status |= FE_HAS_CARRIER;
352
353 if (sync & 4)
354 *status |= FE_HAS_VITERBI;
355
356 if (sync & 8)
357 *status |= FE_HAS_SYNC;
358
359 if ((sync & 0x1f) == 0x1f)
360 *status |= FE_HAS_LOCK;
361
362 return 0;
363 }
364
365
366 static int ves1x93_read_ber(struct dvb_frontend* fe, u32* ber)
367 {
368 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
369
370 *ber = ves1x93_readreg (state, 0x15);
371 *ber |= (ves1x93_readreg (state, 0x16) << 8);
372 *ber |= ((ves1x93_readreg (state, 0x17) & 0x0F) << 16);
373 *ber *= 10;
374
375 return 0;
376 }
377
378 static int ves1x93_read_signal_strength(struct dvb_frontend* fe, u16* strength)
379 {
380 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
381
382 u8 signal = ~ves1x93_readreg (state, 0x0b);
383 *strength = (signal << 8) | signal;
384
385 return 0;
386 }
387
388 static int ves1x93_read_snr(struct dvb_frontend* fe, u16* snr)
389 {
390 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
391
392 u8 _snr = ~ves1x93_readreg (state, 0x1c);
393 *snr = (_snr << 8) | _snr;
394
395 return 0;
396 }
397
398 static int ves1x93_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
399 {
400 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
401
402 *ucblocks = ves1x93_readreg (state, 0x18) & 0x7f;
403
404 if (*ucblocks == 0x7f)
405 *ucblocks = 0xffffffff; /* counter overflow... */
406
407 ves1x93_writereg (state, 0x18, 0x00); /* reset the counter */
408 ves1x93_writereg (state, 0x18, 0x80); /* dto. */
409
410 return 0;
411 }
412
413 static int ves1x93_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
414 {
415 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
416
417 ves1x93_writereg(state, 0x00, 0x11);
418 state->config->pll_set(fe, p);
419 ves1x93_writereg(state, 0x00, 0x01);
420 ves1x93_set_inversion (state, p->inversion);
421 ves1x93_set_fec (state, p->u.qpsk.fec_inner);
422 ves1x93_set_symbolrate (state, p->u.qpsk.symbol_rate);
423 state->inversion = p->inversion;
424
425 return 0;
426 }
427
428 static int ves1x93_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
429 {
430 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
431 int afc;
432
433 afc = ((int)((char)(ves1x93_readreg (state, 0x0a) << 1)))/2;
434 afc = (afc * (int)(p->u.qpsk.symbol_rate/1000/8))/16;
435
436 p->frequency -= afc;
437
438 /*
439 * inversion indicator is only valid
440 * if auto inversion was used
441 */
442 if (state->inversion == INVERSION_AUTO)
443 p->inversion = (ves1x93_readreg (state, 0x0f) & 2) ?
444 INVERSION_OFF : INVERSION_ON;
445 p->u.qpsk.fec_inner = ves1x93_get_fec (state);
446 /* XXX FIXME: timing offset !! */
447
448 return 0;
449 }
450
451 static int ves1x93_sleep(struct dvb_frontend* fe)
452 {
453 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
454
455 return ves1x93_writereg (state, 0x00, 0x08);
456 }
457
458 static void ves1x93_release(struct dvb_frontend* fe)
459 {
460 struct ves1x93_state* state = (struct ves1x93_state*) fe->demodulator_priv;
461 kfree(state);
462 }
463
464 static struct dvb_frontend_ops ves1x93_ops;
465
466 struct dvb_frontend* ves1x93_attach(const struct ves1x93_config* config,
467 struct i2c_adapter* i2c)
468 {
469 struct ves1x93_state* state = NULL;
470 u8 identity;
471
472 /* allocate memory for the internal state */
473 state = (struct ves1x93_state*) kmalloc(sizeof(struct ves1x93_state), GFP_KERNEL);
474 if (state == NULL) goto error;
475
476 /* setup the state */
477 state->config = config;
478 state->i2c = i2c;
479 memcpy(&state->ops, &ves1x93_ops, sizeof(struct dvb_frontend_ops));
480 state->inversion = INVERSION_OFF;
481
482 /* check if the demod is there + identify it */
483 identity = ves1x93_readreg(state, 0x1e);
484 switch (identity) {
485 case 0xdc: /* VES1893A rev1 */
486 printk("ves1x93: Detected ves1893a rev1\n");
487 state->demod_type = DEMOD_VES1893;
488 state->init_1x93_tab = init_1893_tab;
489 state->init_1x93_wtab = init_1893_wtab;
490 state->tab_size = sizeof(init_1893_tab);
491 break;
492
493 case 0xdd: /* VES1893A rev2 */
494 printk("ves1x93: Detected ves1893a rev2\n");
495 state->demod_type = DEMOD_VES1893;
496 state->init_1x93_tab = init_1893_tab;
497 state->init_1x93_wtab = init_1893_wtab;
498 state->tab_size = sizeof(init_1893_tab);
499 break;
500
501 case 0xde: /* VES1993 */
502 printk("ves1x93: Detected ves1993\n");
503 state->demod_type = DEMOD_VES1993;
504 state->init_1x93_tab = init_1993_tab;
505 state->init_1x93_wtab = init_1993_wtab;
506 state->tab_size = sizeof(init_1993_tab);
507 break;
508
509 default:
510 goto error;
511 }
512
513 /* create dvb_frontend */
514 state->frontend.ops = &state->ops;
515 state->frontend.demodulator_priv = state;
516 return &state->frontend;
517
518 error:
519 if (state) kfree(state);
520 return NULL;
521 }
522
523 static struct dvb_frontend_ops ves1x93_ops = {
524
525 .info = {
526 .name = "VLSI VES1x93 DVB-S",
527 .type = FE_QPSK,
528 .frequency_min = 950000,
529 .frequency_max = 2150000,
530 .frequency_stepsize = 125, /* kHz for QPSK frontends */
531 .frequency_tolerance = 29500,
532 .symbol_rate_min = 1000000,
533 .symbol_rate_max = 45000000,
534 /* .symbol_rate_tolerance = ???,*/
535 .caps = FE_CAN_INVERSION_AUTO |
536 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
537 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
538 FE_CAN_QPSK
539 },
540
541 .release = ves1x93_release,
542
543 .init = ves1x93_init,
544 .sleep = ves1x93_sleep,
545
546 .set_frontend = ves1x93_set_frontend,
547 .get_frontend = ves1x93_get_frontend,
548
549 .read_status = ves1x93_read_status,
550 .read_ber = ves1x93_read_ber,
551 .read_signal_strength = ves1x93_read_signal_strength,
552 .read_snr = ves1x93_read_snr,
553 .read_ucblocks = ves1x93_read_ucblocks,
554
555 .set_voltage = ves1x93_set_voltage,
556 };
557
558 module_param(debug, int, 0644);
559
560 MODULE_DESCRIPTION("VLSI VES1x93 DVB-S Demodulator driver");
561 MODULE_AUTHOR("Ralph Metzler");
562 MODULE_LICENSE("GPL");
563
564 EXPORT_SYMBOL(ves1x93_attach);
565
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