1 /*
2 Driver for Zarlink VP310/MT312 Satellite Channel Decoder
3
4 Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 References:
22 http://products.zarlink.com/product_profiles/MT312.htm
23 http://products.zarlink.com/product_profiles/SL1935.htm
24 */
25
26 #include <linux/delay.h>
27 #include <linux/errno.h>
28 #include <linux/init.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32
33 #include "dvb_frontend.h"
34 #include "mt312_priv.h"
35 #include "mt312.h"
36
37
38 struct mt312_state {
39
40 struct i2c_adapter* i2c;
41
42 struct dvb_frontend_ops ops;
43
44 /* configuration settings */
45 const struct mt312_config* config;
46
47 struct dvb_frontend frontend;
48
49 u8 id;
50 u8 frequency;
51 };
52
53 static int debug;
54 #define dprintk(args...) \
55 do { \
56 if (debug) printk(KERN_DEBUG "mt312: " args); \
57 } while (0)
58
59 #define MT312_SYS_CLK 90000000UL /* 90 MHz */
60 #define MT312_LPOWER_SYS_CLK 60000000UL /* 60 MHz */
61 #define MT312_PLL_CLK 10000000UL /* 10 MHz */
62
63 static int mt312_read(struct mt312_state* state, const enum mt312_reg_addr reg,
64 void *buf, const size_t count)
65 {
66 int ret;
67 struct i2c_msg msg[2];
68 u8 regbuf[1] = { reg };
69
70 msg[0].addr = state->config->demod_address;
71 msg[0].flags = 0;
72 msg[0].buf = regbuf;
73 msg[0].len = 1;
74 msg[1].addr = state->config->demod_address;
75 msg[1].flags = I2C_M_RD;
76 msg[1].buf = buf;
77 msg[1].len = count;
78
79 ret = i2c_transfer(state->i2c, msg, 2);
80
81 if (ret != 2) {
82 printk(KERN_ERR "%s: ret == %d\n", __FUNCTION__, ret);
83 return -EREMOTEIO;
84 }
85
86 if(debug) {
87 int i;
88 dprintk("R(%d):", reg & 0x7f);
89 for (i = 0; i < count; i++)
90 printk(" %02x", ((const u8 *) buf)[i]);
91 printk("\n");
92 }
93
94 return 0;
95 }
96
97 static int mt312_write(struct mt312_state* state, const enum mt312_reg_addr reg,
98 const void *src, const size_t count)
99 {
100 int ret;
101 u8 buf[count + 1];
102 struct i2c_msg msg;
103
104 if(debug) {
105 int i;
106 dprintk("W(%d):", reg & 0x7f);
107 for (i = 0; i < count; i++)
108 printk(" %02x", ((const u8 *) src)[i]);
109 printk("\n");
110 }
111
112 buf[0] = reg;
113 memcpy(&buf[1], src, count);
114
115 msg.addr = state->config->demod_address;
116 msg.flags = 0;
117 msg.buf = buf;
118 msg.len = count + 1;
119
120 ret = i2c_transfer(state->i2c, &msg, 1);
121
122 if (ret != 1) {
123 dprintk("%s: ret == %d\n", __FUNCTION__, ret);
124 return -EREMOTEIO;
125 }
126
127 return 0;
128 }
129
130 static inline int mt312_readreg(struct mt312_state* state,
131 const enum mt312_reg_addr reg, u8 * val)
132 {
133 return mt312_read(state, reg, val, 1);
134 }
135
136 static inline int mt312_writereg(struct mt312_state* state,
137 const enum mt312_reg_addr reg, const u8 val)
138 {
139 return mt312_write(state, reg, &val, 1);
140 }
141
142 static inline u32 mt312_div(u32 a, u32 b)
143 {
144 return (a + (b / 2)) / b;
145 }
146
147 static int mt312_reset(struct mt312_state* state, const u8 full)
148 {
149 return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
150 }
151
152 static int mt312_get_inversion(struct mt312_state* state,
153 fe_spectral_inversion_t *i)
154 {
155 int ret;
156 u8 vit_mode;
157
158 if ((ret = mt312_readreg(state, VIT_MODE, &vit_mode)) < 0)
159 return ret;
160
161 if (vit_mode & 0x80) /* auto inversion was used */
162 *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
163
164 return 0;
165 }
166
167 static int mt312_get_symbol_rate(struct mt312_state* state, u32 *sr)
168 {
169 int ret;
170 u8 sym_rate_h;
171 u8 dec_ratio;
172 u16 sym_rat_op;
173 u16 monitor;
174 u8 buf[2];
175
176 if ((ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h)) < 0)
177 return ret;
178
179 if (sym_rate_h & 0x80) { /* symbol rate search was used */
180 if ((ret = mt312_writereg(state, MON_CTRL, 0x03)) < 0)
181 return ret;
182
183 if ((ret = mt312_read(state, MONITOR_H, buf, sizeof(buf))) < 0)
184 return ret;
185
186 monitor = (buf[0] << 8) | buf[1];
187
188 dprintk(KERN_DEBUG "sr(auto) = %u\n",
189 mt312_div(monitor * 15625, 4));
190 } else {
191 if ((ret = mt312_writereg(state, MON_CTRL, 0x05)) < 0)
192 return ret;
193
194 if ((ret = mt312_read(state, MONITOR_H, buf, sizeof(buf))) < 0)
195 return ret;
196
197 dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
198
199 if ((ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf))) < 0)
200 return ret;
201
202 sym_rat_op = (buf[0] << 8) | buf[1];
203
204 dprintk(KERN_DEBUG "sym_rat_op=%d dec_ratio=%d\n",
205 sym_rat_op, dec_ratio);
206 dprintk(KERN_DEBUG "*sr(manual) = %lu\n",
207 (((MT312_PLL_CLK * 8192) / (sym_rat_op + 8192)) *
208 2) - dec_ratio);
209 }
210
211 return 0;
212 }
213
214 static int mt312_get_code_rate(struct mt312_state* state, fe_code_rate_t *cr)
215 {
216 const fe_code_rate_t fec_tab[8] =
217 { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
218 FEC_AUTO, FEC_AUTO };
219
220 int ret;
221 u8 fec_status;
222
223 if ((ret = mt312_readreg(state, FEC_STATUS, &fec_status)) < 0)
224 return ret;
225
226 *cr = fec_tab[(fec_status >> 4) & 0x07];
227
228 return 0;
229 }
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245 static int mt312_initfe(struct dvb_frontend* fe)
246 {
247 struct mt312_state *state = (struct mt312_state*) fe->demodulator_priv;
248 int ret;
249 u8 buf[2];
250
251 /* wake up */
252 if ((ret = mt312_writereg(state, CONFIG, (state->frequency == 60 ? 0x88 : 0x8c))) < 0)
253 return ret;
254
255 /* wait at least 150 usec */
256 udelay(150);
257
258 /* full reset */
259 if ((ret = mt312_reset(state, 1)) < 0)
260 return ret;
261
262 // Per datasheet, write correct values. 09/28/03 ACCJr.
263 // If we don't do this, we won't get FE_HAS_VITERBI in the VP310.
264 {
265 u8 buf_def[8]={0x14, 0x12, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00};
266
267 if ((ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def))) < 0)
268 return ret;
269 }
270
271 /* SYS_CLK */
272 buf[0] = mt312_div((state->frequency == 60 ? MT312_LPOWER_SYS_CLK : MT312_SYS_CLK) * 2, 1000000);
273
274 /* DISEQC_RATIO */
275 buf[1] = mt312_div(MT312_PLL_CLK, 15000 * 4);
276
277 if ((ret = mt312_write(state, SYS_CLK, buf, sizeof(buf))) < 0)
278 return ret;
279
280 if ((ret = mt312_writereg(state, SNR_THS_HIGH, 0x32)) < 0)
281 return ret;
282
283 if ((ret = mt312_writereg(state, OP_CTRL, 0x53)) < 0)
284 return ret;
285
286 /* TS_SW_LIM */
287 buf[0] = 0x8c;
288 buf[1] = 0x98;
289
290 if ((ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf))) < 0)
291 return ret;
292
293 if ((ret = mt312_writereg(state, CS_SW_LIM, 0x69)) < 0)
294 return ret;
295
296 if (state->config->pll_init) {
297 mt312_writereg(state, GPP_CTRL, 0x40);
298 state->config->pll_init(fe);
299 mt312_writereg(state, GPP_CTRL, 0x00);
300 }
301
302 return 0;
303 }
304
305 static int mt312_send_master_cmd(struct dvb_frontend* fe,
306 struct dvb_diseqc_master_cmd *c)
307 {
308 struct mt312_state *state = (struct mt312_state*) fe->demodulator_priv;
309 int ret;
310 u8 diseqc_mode;
311
312 if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
313 return -EINVAL;
314
315 if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0)
316 return ret;
317
318 if ((ret =
319 mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len)) < 0)
320 return ret;
321
322 if ((ret =
323 mt312_writereg(state, DISEQC_MODE,
324 (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
325 | 0x04)) < 0)
326 return ret;
327
328 /* set DISEQC_MODE[2:0] to zero if a return message is expected */
329 if (c->msg[0] & 0x02)
330 if ((ret =
331 mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40))) < 0)
332 return ret;
333
334 return 0;
335 }
336
337 static int mt312_send_burst(struct dvb_frontend* fe, const fe_sec_mini_cmd_t c)
338 {
339 struct mt312_state *state = (struct mt312_state*) fe->demodulator_priv;
340 const u8 mini_tab[2] = { 0x02, 0x03 };
341
342 int ret;
343 u8 diseqc_mode;
344
345 if (c > SEC_MINI_B)
346 return -EINVAL;
347
348 if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0)
349 return ret;
350
351 if ((ret =
352 mt312_writereg(state, DISEQC_MODE,
353 (diseqc_mode & 0x40) | mini_tab[c])) < 0)
354 return ret;
355
356 return 0;
357 }
358
359 static int mt312_set_tone(struct dvb_frontend* fe, const fe_sec_tone_mode_t t)
360 {
361 struct mt312_state *state = (struct mt312_state*) fe->demodulator_priv;
362 const u8 tone_tab[2] = { 0x01, 0x00 };
363
364 int ret;
365 u8 diseqc_mode;
366
367 if (t > SEC_TONE_OFF)
368 return -EINVAL;
369
370 if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0)
371 return ret;
372
373 if ((ret =
374 mt312_writereg(state, DISEQC_MODE,
375 (diseqc_mode & 0x40) | tone_tab[t])) < 0)
376 return ret;
377
378 return 0;
379 }
380
381 static int mt312_set_voltage(struct dvb_frontend* fe, const fe_sec_voltage_t v)
382 {
383 struct mt312_state *state = (struct mt312_state*) fe->demodulator_priv;
384 const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
385
386 if (v > SEC_VOLTAGE_OFF)
387 return -EINVAL;
388
389 return mt312_writereg(state, DISEQC_MODE, volt_tab[v]);
390 }
391
392 static int mt312_read_status(struct dvb_frontend* fe, fe_status_t *s)
393 {
394 struct mt312_state *state = (struct mt312_state*) fe->demodulator_priv;
395 int ret;
396 u8 status[3];
397
398 *s = 0;
399
400 if ((ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status))) < 0)
401 return ret;
402
403 dprintk(KERN_DEBUG "QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x, FEC_STATUS: 0x%02x\n", status[0], status[1], status[2]);
404
405 if (status[0] & 0xc0)
406 *s |= FE_HAS_SIGNAL; /* signal noise ratio */
407 if (status[0] & 0x04)
408 *s |= FE_HAS_CARRIER; /* qpsk carrier lock */
409 if (status[2] & 0x02)
410 *s |= FE_HAS_VITERBI; /* viterbi lock */
411 if (status[2] & 0x04)
412 *s |= FE_HAS_SYNC; /* byte align lock */
413 if (status[0] & 0x01)
414 *s |= FE_HAS_LOCK; /* qpsk lock */
415
416 return 0;
417 }
418
419 static int mt312_read_ber(struct dvb_frontend* fe, u32 *ber)
420 {
421 struct mt312_state *state = (struct mt312_state*) fe->demodulator_priv;
422 int ret;
423 u8 buf[3];
424
425 if ((ret = mt312_read(state, RS_BERCNT_H, buf, 3)) < 0)
426 return ret;
427
428 *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
429
430 return 0;
431 }
432
433 static int mt312_read_signal_strength(struct dvb_frontend* fe, u16 *signal_strength)
434 {
435 struct mt312_state *state = (struct mt312_state*) fe->demodulator_priv;
436 int ret;
437 u8 buf[3];
438 u16 agc;
439 s16 err_db;
440
441 if ((ret = mt312_read(state, AGC_H, buf, sizeof(buf))) < 0)
442 return ret;
443
444 agc = (buf[0] << 6) | (buf[1] >> 2);
445 err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
446
447 *signal_strength = agc;
448
449 dprintk(KERN_DEBUG "agc=%08x err_db=%hd\n", agc, err_db);
450
451 return 0;
452 }
453
454 static int mt312_read_snr(struct dvb_frontend* fe, u16 *snr)
455 {
456 struct mt312_state *state = (struct mt312_state*) fe->demodulator_priv;
457 int ret;
458 u8 buf[2];
459
460 if ((ret = mt312_read(state, M_SNR_H, &buf, sizeof(buf))) < 0)
461 return ret;
462
463 *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
464
465 return 0;
466 }
467
468 static int mt312_read_ucblocks(struct dvb_frontend* fe, u32 *ubc)
469 {
470 struct mt312_state *state = (struct mt312_state*) fe->demodulator_priv;
471 int ret;
472 u8 buf[2];
473
474 if ((ret = mt312_read(state, RS_UBC_H, &buf, sizeof(buf))) < 0)
475 return ret;
476
477 *ubc = (buf[0] << 8) | buf[1];
478
479 return 0;
480 }
481
482 static int mt312_set_frontend(struct dvb_frontend* fe,
483 struct dvb_frontend_parameters *p)
484 {
485 struct mt312_state *state = (struct mt312_state*) fe->demodulator_priv;
486 int ret;
487 u8 buf[5], config_val;
488 u16 sr;
489
490 const u8 fec_tab[10] =
491 { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
492 const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
493
494 dprintk("%s: Freq %d\n", __FUNCTION__, p->frequency);
495
496 if ((p->frequency < fe->ops->info.frequency_min)
497 || (p->frequency > fe->ops->info.frequency_max))
498 return -EINVAL;
499
500 if ((p->inversion < INVERSION_OFF)
501 || (p->inversion > INVERSION_ON))
502 return -EINVAL;
503
504 if ((p->u.qpsk.symbol_rate < fe->ops->info.symbol_rate_min)
505 || (p->u.qpsk.symbol_rate > fe->ops->info.symbol_rate_max))
506 return -EINVAL;
507
508 if ((p->u.qpsk.fec_inner < FEC_NONE)
509 || (p->u.qpsk.fec_inner > FEC_AUTO))
510 return -EINVAL;
511
512 if ((p->u.qpsk.fec_inner == FEC_4_5)
513 || (p->u.qpsk.fec_inner == FEC_8_9))
514 return -EINVAL;
515
516 switch (state->id) {
517 case ID_VP310:
518 // For now we will do this only for the VP310.
519 // It should be better for the mt312 as well, but tunning will be slower. ACCJr 09/29/03
520 if ((ret = mt312_readreg(state, CONFIG, &config_val) < 0))
521 return ret;
522 if (p->u.qpsk.symbol_rate >= 30000000) //Note that 30MS/s should use 90MHz
523 {
524 if ((config_val & 0x0c) == 0x08) { //We are running 60MHz
525 state->frequency = 90;
526 if ((ret = mt312_initfe(fe)) < 0)
527 return ret;
528 }
529 }
530 else
531 {
532 if ((config_val & 0x0c) == 0x0C) { //We are running 90MHz
533 state->frequency = 60;
534 if ((ret = mt312_initfe(fe)) < 0)
535 return ret;
536 }
537 }
538 break;
539
540 case ID_MT312:
541 break;
542
543 default:
544 return -EINVAL;
545 }
546
547 mt312_writereg(state, GPP_CTRL, 0x40);
548 state->config->pll_set(fe, p);
549 mt312_writereg(state, GPP_CTRL, 0x00);
550
551 /* sr = (u16)(sr * 256.0 / 1000000.0) */
552 sr = mt312_div(p->u.qpsk.symbol_rate * 4, 15625);
553
554 /* SYM_RATE */
555 buf[0] = (sr >> 8) & 0x3f;
556 buf[1] = (sr >> 0) & 0xff;
557
558 /* VIT_MODE */
559 buf[2] = inv_tab[p->inversion] | fec_tab[p->u.qpsk.fec_inner];
560
561 /* QPSK_CTRL */
562 buf[3] = 0x40; /* swap I and Q before QPSK demodulation */
563
564 if (p->u.qpsk.symbol_rate < 10000000)
565 buf[3] |= 0x04; /* use afc mode */
566
567 /* GO */
568 buf[4] = 0x01;
569
570 if ((ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf))) < 0)
571 return ret;
572
573 mt312_reset(state, 0);
574
575 return 0;
576 }
577
578 static int mt312_get_frontend(struct dvb_frontend* fe,
579 struct dvb_frontend_parameters *p)
580 {
581 struct mt312_state *state = (struct mt312_state*) fe->demodulator_priv;
582 int ret;
583
584 if ((ret = mt312_get_inversion(state, &p->inversion)) < 0)
585 return ret;
586
587 if ((ret = mt312_get_symbol_rate(state, &p->u.qpsk.symbol_rate)) < 0)
588 return ret;
589
590 if ((ret = mt312_get_code_rate(state, &p->u.qpsk.fec_inner)) < 0)
591 return ret;
592
593 return 0;
594 }
595
596 static int mt312_sleep(struct dvb_frontend* fe)
597 {
598 struct mt312_state *state = (struct mt312_state*) fe->demodulator_priv;
599 int ret;
600 u8 config;
601
602 /* reset all registers to defaults */
603 if ((ret = mt312_reset(state, 1)) < 0)
604 return ret;
605
606 if ((ret = mt312_readreg(state, CONFIG, &config)) < 0)
607 return ret;
608
609 /* enter standby */
610 if ((ret = mt312_writereg(state, CONFIG, config & 0x7f)) < 0)
611 return ret;
612
613 return 0;
614 }
615
616 static int mt312_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
617 {
618 fesettings->min_delay_ms = 50;
619 fesettings->step_size = 0;
620 fesettings->max_drift = 0;
621 return 0;
622 }
623
624 static void mt312_release(struct dvb_frontend* fe)
625 {
626 struct mt312_state* state = (struct mt312_state*) fe->demodulator_priv;
627 kfree(state);
628 }
629
630 static struct dvb_frontend_ops vp310_mt312_ops;
631
632 struct dvb_frontend* vp310_attach(const struct mt312_config* config,
633 struct i2c_adapter* i2c)
634 {
635 struct mt312_state* state = NULL;
636
637 /* allocate memory for the internal state */
638 state = (struct mt312_state*) kmalloc(sizeof(struct mt312_state), GFP_KERNEL);
639 if (state == NULL)
640 goto error;
641
642 /* setup the state */
643 state->config = config;
644 state->i2c = i2c;
645 memcpy(&state->ops, &vp310_mt312_ops, sizeof(struct dvb_frontend_ops));
646 strcpy(state->ops.info.name, "Zarlink VP310 DVB-S");
647
648 /* check if the demod is there */
649 if (mt312_readreg(state, ID, &state->id) < 0)
650 goto error;
651 if (state->id != ID_VP310) {
652 goto error;
653 }
654
655 /* create dvb_frontend */
656 state->frequency = 90;
657 state->frontend.ops = &state->ops;
658 state->frontend.demodulator_priv = state;
659 return &state->frontend;
660
661 error:
662 if (state)
663 kfree(state);
664 return NULL;
665 }
666
667 struct dvb_frontend* mt312_attach(const struct mt312_config* config,
668 struct i2c_adapter* i2c)
669 {
670 struct mt312_state* state = NULL;
671
672 /* allocate memory for the internal state */
673 state = (struct mt312_state*) kmalloc(sizeof(struct mt312_state), GFP_KERNEL);
674 if (state == NULL)
675 goto error;
676
677 /* setup the state */
678 state->config = config;
679 state->i2c = i2c;
680 memcpy(&state->ops, &vp310_mt312_ops, sizeof(struct dvb_frontend_ops));
681 strcpy(state->ops.info.name, "Zarlink MT312 DVB-S");
682
683 /* check if the demod is there */
684 if (mt312_readreg(state, ID, &state->id) < 0)
685 goto error;
686 if (state->id != ID_MT312) {
687 goto error;
688 }
689
690 /* create dvb_frontend */
691 state->frequency = 60;
692 state->frontend.ops = &state->ops;
693 state->frontend.demodulator_priv = state;
694 return &state->frontend;
695
696 error:
697 if (state)
698 kfree(state);
699 return NULL;
700 }
701
702 static struct dvb_frontend_ops vp310_mt312_ops = {
703
704 .info = {
705 .name = "Zarlink ???? DVB-S",
706 .type = FE_QPSK,
707 .frequency_min = 950000,
708 .frequency_max = 2150000,
709 .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128,
710 .symbol_rate_min = MT312_SYS_CLK / 128,
711 .symbol_rate_max = MT312_SYS_CLK / 2,
712 .caps =
713 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
714 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
715 FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |
716 FE_CAN_RECOVER
717 },
718
719 .release = mt312_release,
720
721 .init = mt312_initfe,
722 .sleep = mt312_sleep,
723
724 .set_frontend = mt312_set_frontend,
725 .get_frontend = mt312_get_frontend,
726 .get_tune_settings = mt312_get_tune_settings,
727
728 .read_status = mt312_read_status,
729 .read_ber = mt312_read_ber,
730 .read_signal_strength = mt312_read_signal_strength,
731 .read_snr = mt312_read_snr,
732 .read_ucblocks = mt312_read_ucblocks,
733
734 .diseqc_send_master_cmd = mt312_send_master_cmd,
735 .diseqc_send_burst = mt312_send_burst,
736 .set_tone = mt312_set_tone,
737 .set_voltage = mt312_set_voltage,
738 };
739
740 module_param(debug, int, 0644);
741 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
742
743 MODULE_DESCRIPTION("Zarlink VP310/MT312 DVB-S Demodulator driver");
744 MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
745 MODULE_LICENSE("GPL");
746
747 EXPORT_SYMBOL(mt312_attach);
748 EXPORT_SYMBOL(vp310_attach);
749
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