1 #ifndef DIBX000_COMMON_H
2 #define DIBX000_COMMON_H
3
4 enum dibx000_i2c_interface {
5 DIBX000_I2C_INTERFACE_TUNER = 0,
6 DIBX000_I2C_INTERFACE_GPIO_1_2 = 1,
7 DIBX000_I2C_INTERFACE_GPIO_3_4 = 2
8 };
9
10 struct dibx000_i2c_master {
11 #define DIB3000MC 1
12 #define DIB7000 2
13 #define DIB7000P 11
14 #define DIB7000MC 12
15 u16 device_rev;
16
17 enum dibx000_i2c_interface selected_interface;
18
19 // struct i2c_adapter tuner_i2c_adap;
20 struct i2c_adapter gated_tuner_i2c_adap;
21
22 struct i2c_adapter *i2c_adap;
23 u8 i2c_addr;
24
25 u16 base_reg;
26 };
27
28 extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, u16 device_rev, struct i2c_adapter *i2c_adap, u8 i2c_addr);
29 extern struct i2c_adapter * dibx000_get_i2c_adapter(struct dibx000_i2c_master *mst, enum dibx000_i2c_interface intf, int gating);
30 extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst);
31
32 #define BAND_LBAND 0x01
33 #define BAND_UHF 0x02
34 #define BAND_VHF 0x04
35 #define BAND_SBAND 0x08
36 #define BAND_FM 0x10
37
38 #define BAND_OF_FREQUENCY(freq_kHz) ( (freq_kHz) <= 115000 ? BAND_FM : \
39 (freq_kHz) <= 250000 ? BAND_VHF : \
40 (freq_kHz) <= 863000 ? BAND_UHF : \
41 (freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND )
42
43 struct dibx000_agc_config {
44 /* defines the capabilities of this AGC-setting - using the BAND_-defines*/
45 u8 band_caps;
46
47 u16 setup;
48
49 u16 inv_gain;
50 u16 time_stabiliz;
51
52 u8 alpha_level;
53 u16 thlock;
54
55 u8 wbd_inv;
56 u16 wbd_ref;
57 u8 wbd_sel;
58 u8 wbd_alpha;
59
60 u16 agc1_max;
61 u16 agc1_min;
62 u16 agc2_max;
63 u16 agc2_min;
64
65 u8 agc1_pt1;
66 u8 agc1_pt2;
67 u8 agc1_pt3;
68
69 u8 agc1_slope1;
70 u8 agc1_slope2;
71
72 u8 agc2_pt1;
73 u8 agc2_pt2;
74
75 u8 agc2_slope1;
76 u8 agc2_slope2;
77
78 u8 alpha_mant;
79 u8 alpha_exp;
80
81 u8 beta_mant;
82 u8 beta_exp;
83
84 u8 perform_agc_softsplit;
85
86 struct {
87 u16 min;
88 u16 max;
89 u16 min_thres;
90 u16 max_thres;
91 } split;
92 };
93
94 struct dibx000_bandwidth_config {
95 u32 internal;
96 u32 sampling;
97
98 u8 pll_prediv;
99 u8 pll_ratio;
100 u8 pll_range;
101 u8 pll_reset;
102 u8 pll_bypass;
103
104 u8 enable_refdiv;
105 u8 bypclk_div;
106 u8 IO_CLK_en_core;
107 u8 ADClkSrc;
108 u8 modulo;
109
110 u16 sad_cfg;
111
112 u32 ifreq;
113 u32 timf;
114
115 u32 xtal_hz;
116 };
117
118 enum dibx000_adc_states {
119 DIBX000_SLOW_ADC_ON = 0,
120 DIBX000_SLOW_ADC_OFF,
121 DIBX000_ADC_ON,
122 DIBX000_ADC_OFF,
123 DIBX000_VBG_ENABLE,
124 DIBX000_VBG_DISABLE,
125 };
126
127 #define BANDWIDTH_TO_KHZ(v) ( (v) == BANDWIDTH_8_MHZ ? 8000 : \
128 (v) == BANDWIDTH_7_MHZ ? 7000 : \
129 (v) == BANDWIDTH_6_MHZ ? 6000 : 8000 )
130
131 #define BANDWIDTH_TO_INDEX(v) ( \
132 (v) == 8000 ? BANDWIDTH_8_MHZ : \
133 (v) == 7000 ? BANDWIDTH_7_MHZ : \
134 (v) == 6000 ? BANDWIDTH_6_MHZ : BANDWIDTH_8_MHZ )
135
136 /* Chip output mode. */
137 #define OUTMODE_HIGH_Z 0
138 #define OUTMODE_MPEG2_PAR_GATED_CLK 1
139 #define OUTMODE_MPEG2_PAR_CONT_CLK 2
140 #define OUTMODE_MPEG2_SERIAL 7
141 #define OUTMODE_DIVERSITY 4
142 #define OUTMODE_MPEG2_FIFO 5
143 #define OUTMODE_ANALOG_ADC 6
144
145 #endif
146
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