1 #ifndef __THERM_PMAC_7_2_H__
2 #define __THERM_PMAC_7_2_H__
3
4 typedef unsigned short fu16;
5 typedef int fs32;
6 typedef short fs16;
7
8 struct mpu_data
9 {
10 u8 signature; /* 0x00 - EEPROM sig. */
11 u8 bytes_used; /* 0x01 - Bytes used in eeprom (160 ?) */
12 u8 size; /* 0x02 - EEPROM size (256 ?) */
13 u8 version; /* 0x03 - EEPROM version */
14 u32 data_revision; /* 0x04 - Dataset revision */
15 u8 processor_bin_code[3]; /* 0x08 - Processor BIN code */
16 u8 bin_code_expansion; /* 0x0b - ??? (padding ?) */
17 u8 processor_num; /* 0x0c - Number of CPUs on this MPU */
18 u8 input_mul_bus_div; /* 0x0d - Clock input multiplier/bus divider */
19 u8 reserved1[2]; /* 0x0e - */
20 u32 input_clk_freq_high; /* 0x10 - Input clock frequency high */
21 u8 cpu_nb_target_cycles; /* 0x14 - ??? */
22 u8 cpu_statlat; /* 0x15 - ??? */
23 u8 cpu_snooplat; /* 0x16 - ??? */
24 u8 cpu_snoopacc; /* 0x17 - ??? */
25 u8 nb_paamwin; /* 0x18 - ??? */
26 u8 nb_statlat; /* 0x19 - ??? */
27 u8 nb_snooplat; /* 0x1a - ??? */
28 u8 nb_snoopwin; /* 0x1b - ??? */
29 u8 api_bus_mode; /* 0x1c - ??? */
30 u8 reserved2[3]; /* 0x1d - */
31 u32 input_clk_freq_low; /* 0x20 - Input clock frequency low */
32 u8 processor_card_slot; /* 0x24 - Processor card slot number */
33 u8 reserved3[2]; /* 0x25 - */
34 u8 padjmax; /* 0x27 - Max power adjustment (Not in OF!) */
35 u8 ttarget; /* 0x28 - Target temperature */
36 u8 tmax; /* 0x29 - Max temperature */
37 u8 pmaxh; /* 0x2a - Max power */
38 u8 tguardband; /* 0x2b - Guardband temp ??? Hist. len in OSX */
39 fs32 pid_gp; /* 0x2c - PID proportional gain */
40 fs32 pid_gr; /* 0x30 - PID reset gain */
41 fs32 pid_gd; /* 0x34 - PID derivative gain */
42 fu16 voph; /* 0x38 - Vop High */
43 fu16 vopl; /* 0x3a - Vop Low */
44 fs16 nactual_die; /* 0x3c - nActual Die */
45 fs16 nactual_heatsink; /* 0x3e - nActual Heatsink */
46 fs16 nactual_system; /* 0x40 - nActual System */
47 u16 calibration_flags; /* 0x42 - Calibration flags */
48 fu16 mdiode; /* 0x44 - Diode M value (scaling factor) */
49 fs16 bdiode; /* 0x46 - Diode B value (offset) */
50 fs32 theta_heat_sink; /* 0x48 - Theta heat sink */
51 u16 rminn_intake_fan; /* 0x4c - Intake fan min RPM */
52 u16 rmaxn_intake_fan; /* 0x4e - Intake fan max RPM */
53 u16 rminn_exhaust_fan; /* 0x50 - Exhaust fan min RPM */
54 u16 rmaxn_exhaust_fan; /* 0x52 - Exhaust fan max RPM */
55 u8 processor_part_num[8]; /* 0x54 - Processor part number XX pumps min/max */
56 u32 processor_lot_num; /* 0x5c - Processor lot number */
57 u8 orig_card_sernum[0x10]; /* 0x60 - Card original serial number */
58 u8 curr_card_sernum[0x10]; /* 0x70 - Card current serial number */
59 u8 mlb_sernum[0x18]; /* 0x80 - MLB serial number */
60 u32 checksum1; /* 0x98 - */
61 u32 checksum2; /* 0x9c - */
62 }; /* Total size = 0xa0 */
63
64 /* Display a 16.16 fixed point value */
65 #define FIX32TOPRINT(f) ((f) >> 16),((((f) & 0xffff) * 1000) >> 16)
66
67 /*
68 * Maximum number of seconds to be in critical state (after a
69 * normal shutdown attempt). If the machine isn't down after
70 * this counter elapses, we force an immediate machine power
71 * off.
72 */
73 #define MAX_CRITICAL_STATE 30
74 static char * critical_overtemp_path = "/sbin/critical_overtemp";
75
76 /*
77 * This option is "weird" :) Basically, if you define this to 1
78 * the control loop for the RPMs fans (not PWMs) will apply the
79 * correction factor obtained from the PID to the _actual_ RPM
80 * speed read from the FCU.
81 * If you define the below constant to 0, then it will be
82 * applied to the setpoint RPM speed, that is basically the
83 * speed we proviously "asked" for.
84 *
85 * I'm not sure which of these Apple's algorithm is supposed
86 * to use
87 */
88 #define RPM_PID_USE_ACTUAL_SPEED 0
89
90 /*
91 * i2c IDs. Currently, we hard code those and assume that
92 * the FCU is on U3 bus 1 while all sensors are on U3 bus
93 * 0. This appear to be safe enough for this first version
94 * of the driver, though I would accept any clean patch
95 * doing a better use of the device-tree without turning the
96 * while i2c registration mechanism into a racy mess
97 *
98 * Note: Xserve changed this. We have some bits on the K2 bus,
99 * which I arbitrarily set to 0x200. Ultimately, we really want
100 * too lookup these in the device-tree though
101 */
102 #define FAN_CTRLER_ID 0x15e
103 #define SUPPLY_MONITOR_ID 0x58
104 #define SUPPLY_MONITORB_ID 0x5a
105 #define DRIVES_DALLAS_ID 0x94
106 #define BACKSIDE_MAX_ID 0x98
107 #define XSERVE_DIMMS_LM87 0x25a
108 #define XSERVE_SLOTS_LM75 0x290
109
110 /*
111 * Some MAX6690, DS1775, LM87 register definitions
112 */
113 #define MAX6690_INT_TEMP 0
114 #define MAX6690_EXT_TEMP 1
115 #define DS1775_TEMP 0
116 #define LM87_INT_TEMP 0x27
117
118 /*
119 * Scaling factors for the AD7417 ADC converters (except
120 * for the CPU diode which is obtained from the EEPROM).
121 * Those values are obtained from the property list of
122 * the darwin driver
123 */
124 #define ADC_12V_CURRENT_SCALE 0x0320 /* _AD2 */
125 #define ADC_CPU_VOLTAGE_SCALE 0x00a0 /* _AD3 */
126 #define ADC_CPU_CURRENT_SCALE 0x1f40 /* _AD4 */
127
128 /*
129 * PID factors for the U3/Backside fan control loop. We have 2 sets
130 * of values here, one set for U3 and one set for U3H
131 */
132 #define BACKSIDE_FAN_PWM_DEFAULT_ID 1
133 #define BACKSIDE_FAN_PWM_INDEX 0
134 #define BACKSIDE_PID_U3_G_d 0x02800000
135 #define BACKSIDE_PID_U3H_G_d 0x01400000
136 #define BACKSIDE_PID_RACK_G_d 0x00500000
137 #define BACKSIDE_PID_G_p 0x00500000
138 #define BACKSIDE_PID_RACK_G_p 0x0004cccc
139 #define BACKSIDE_PID_G_r 0x00000000
140 #define BACKSIDE_PID_U3_INPUT_TARGET 0x00410000
141 #define BACKSIDE_PID_U3H_INPUT_TARGET 0x004b0000
142 #define BACKSIDE_PID_RACK_INPUT_TARGET 0x00460000
143 #define BACKSIDE_PID_INTERVAL 5
144 #define BACKSIDE_PID_RACK_INTERVAL 1
145 #define BACKSIDE_PID_OUTPUT_MAX 100
146 #define BACKSIDE_PID_U3_OUTPUT_MIN 20
147 #define BACKSIDE_PID_U3H_OUTPUT_MIN 20
148 #define BACKSIDE_PID_HISTORY_SIZE 2
149
150 struct basckside_pid_params
151 {
152 s32 G_d;
153 s32 G_p;
154 s32 G_r;
155 s32 input_target;
156 s32 output_min;
157 s32 output_max;
158 s32 interval;
159 int additive;
160 };
161
162 struct backside_pid_state
163 {
164 int ticks;
165 struct i2c_client * monitor;
166 s32 sample_history[BACKSIDE_PID_HISTORY_SIZE];
167 s32 error_history[BACKSIDE_PID_HISTORY_SIZE];
168 int cur_sample;
169 s32 last_temp;
170 int pwm;
171 int first;
172 };
173
174 /*
175 * PID factors for the Drive Bay fan control loop
176 */
177 #define DRIVES_FAN_RPM_DEFAULT_ID 2
178 #define DRIVES_FAN_RPM_INDEX 1
179 #define DRIVES_PID_G_d 0x01e00000
180 #define DRIVES_PID_G_p 0x00500000
181 #define DRIVES_PID_G_r 0x00000000
182 #define DRIVES_PID_INPUT_TARGET 0x00280000
183 #define DRIVES_PID_INTERVAL 5
184 #define DRIVES_PID_OUTPUT_MAX 4000
185 #define DRIVES_PID_OUTPUT_MIN 300
186 #define DRIVES_PID_HISTORY_SIZE 2
187
188 struct drives_pid_state
189 {
190 int ticks;
191 struct i2c_client * monitor;
192 s32 sample_history[BACKSIDE_PID_HISTORY_SIZE];
193 s32 error_history[BACKSIDE_PID_HISTORY_SIZE];
194 int cur_sample;
195 s32 last_temp;
196 int rpm;
197 int first;
198 };
199
200 #define SLOTS_FAN_PWM_DEFAULT_ID 2
201 #define SLOTS_FAN_PWM_INDEX 2
202 #define SLOTS_FAN_DEFAULT_PWM 40 /* Do better here ! */
203
204
205 /*
206 * PID factors for the Xserve DIMM control loop
207 */
208 #define DIMM_PID_G_d 0
209 #define DIMM_PID_G_p 0
210 #define DIMM_PID_G_r 0x06553600
211 #define DIMM_PID_INPUT_TARGET 3276800
212 #define DIMM_PID_INTERVAL 1
213 #define DIMM_PID_OUTPUT_MAX 14000
214 #define DIMM_PID_OUTPUT_MIN 4000
215 #define DIMM_PID_HISTORY_SIZE 20
216
217 struct dimm_pid_state
218 {
219 int ticks;
220 struct i2c_client * monitor;
221 s32 sample_history[DIMM_PID_HISTORY_SIZE];
222 s32 error_history[DIMM_PID_HISTORY_SIZE];
223 int cur_sample;
224 s32 last_temp;
225 int first;
226 int output;
227 };
228
229
230 /*
231 * PID factors for the Xserve Slots control loop
232 */
233 #define SLOTS_PID_G_d 0
234 #define SLOTS_PID_G_p 0
235 #define SLOTS_PID_G_r 0x00100000
236 #define SLOTS_PID_INPUT_TARGET 3200000
237 #define SLOTS_PID_INTERVAL 1
238 #define SLOTS_PID_OUTPUT_MAX 100
239 #define SLOTS_PID_OUTPUT_MIN 20
240 #define SLOTS_PID_HISTORY_SIZE 20
241
242 struct slots_pid_state
243 {
244 int ticks;
245 struct i2c_client * monitor;
246 s32 sample_history[SLOTS_PID_HISTORY_SIZE];
247 s32 error_history[SLOTS_PID_HISTORY_SIZE];
248 int cur_sample;
249 s32 last_temp;
250 int first;
251 int pwm;
252 };
253
254
255
256 /* Desktops */
257
258 #define CPUA_INTAKE_FAN_RPM_DEFAULT_ID 3
259 #define CPUA_EXHAUST_FAN_RPM_DEFAULT_ID 4
260 #define CPUB_INTAKE_FAN_RPM_DEFAULT_ID 5
261 #define CPUB_EXHAUST_FAN_RPM_DEFAULT_ID 6
262
263 #define CPUA_INTAKE_FAN_RPM_INDEX 3
264 #define CPUA_EXHAUST_FAN_RPM_INDEX 4
265 #define CPUB_INTAKE_FAN_RPM_INDEX 5
266 #define CPUB_EXHAUST_FAN_RPM_INDEX 6
267
268 #define CPU_INTAKE_SCALE 0x0000f852
269 #define CPU_TEMP_HISTORY_SIZE 2
270 #define CPU_POWER_HISTORY_SIZE 10
271 #define CPU_PID_INTERVAL 1
272 #define CPU_MAX_OVERTEMP 30
273
274 #define CPUA_PUMP_RPM_INDEX 7
275 #define CPUB_PUMP_RPM_INDEX 8
276 #define CPU_PUMP_OUTPUT_MAX 3200
277 #define CPU_PUMP_OUTPUT_MIN 1250
278
279 /* Xserve */
280 #define CPU_A1_FAN_RPM_INDEX 9
281 #define CPU_A2_FAN_RPM_INDEX 10
282 #define CPU_A3_FAN_RPM_INDEX 11
283 #define CPU_B1_FAN_RPM_INDEX 12
284 #define CPU_B2_FAN_RPM_INDEX 13
285 #define CPU_B3_FAN_RPM_INDEX 14
286
287
288 struct cpu_pid_state
289 {
290 int index;
291 struct i2c_client * monitor;
292 struct mpu_data mpu;
293 int overtemp;
294 s32 temp_history[CPU_TEMP_HISTORY_SIZE];
295 int cur_temp;
296 s32 power_history[CPU_POWER_HISTORY_SIZE];
297 s32 error_history[CPU_POWER_HISTORY_SIZE];
298 int cur_power;
299 int count_power;
300 int rpm;
301 int intake_rpm;
302 s32 voltage;
303 s32 current_a;
304 s32 last_temp;
305 s32 last_power;
306 int first;
307 u8 adc_config;
308 s32 pump_min;
309 s32 pump_max;
310 };
311
312 /* Tickle FCU every 10 seconds */
313 #define FCU_TICKLE_TICKS 10
314
315 /*
316 * Driver state
317 */
318 enum {
319 state_detached,
320 state_attaching,
321 state_attached,
322 state_detaching,
323 };
324
325
326 #endif /* __THERM_PMAC_7_2_H__ */
327
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