1 /* $Id: bkm_ax.h,v 1.5.6.3 2001/09/23 22:24:46 kai Exp $
2 *
3 * low level decls for T-Berkom cards A4T and Scitel Quadro (4*S0, passive)
4 *
5 * Author Roland Klabunde
6 * Copyright by Roland Klabunde <R.Klabunde@Berkom.de>
7 *
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
10 *
11 */
12
13 #ifndef __BKM_AX_H__
14 #define __BKM_AX_H__
15
16 /* Supported boards (subtypes) */
17 #define SCT_1 1
18 #define SCT_2 2
19 #define SCT_3 3
20 #define SCT_4 4
21 #define BKM_A4T 5
22
23 #define PLX_ADDR_PLX 0x14 /* Addr PLX configuration */
24 #define PLX_ADDR_ISAC 0x18 /* Addr ISAC */
25 #define PLX_ADDR_HSCX 0x1C /* Addr HSCX */
26 #define PLX_ADDR_ALE 0x20 /* Addr ALE */
27 #define PLX_ADDR_ALEPLUS 0x24 /* Next Addr behind ALE */
28
29 #define PLX_SUBVEN 0x2C /* Offset SubVendor */
30 #define PLX_SUBSYS 0x2E /* Offset SubSystem */
31
32
33 /* Application specific registers I20 (Siemens SZB6120H) */
34 typedef struct {
35 /* Video front end horizontal configuration register */
36 volatile u_int i20VFEHorzCfg; /* Offset 00 */
37 /* Video front end vertical configuration register */
38 volatile u_int i20VFEVertCfg; /* Offset 04 */
39 /* Video front end scaler and pixel format register */
40 volatile u_int i20VFEScaler; /* Offset 08 */
41 /* Video display top register */
42 volatile u_int i20VDispTop; /* Offset 0C */
43 /* Video display bottom register */
44 volatile u_int i20VDispBottom; /* Offset 10 */
45 /* Video stride, status and frame grab register */
46 volatile u_int i20VidFrameGrab;/* Offset 14 */
47 /* Video display configuration register */
48 volatile u_int i20VDispCfg; /* Offset 18 */
49 /* Video masking map top */
50 volatile u_int i20VMaskTop; /* Offset 1C */
51 /* Video masking map bottom */
52 volatile u_int i20VMaskBottom; /* Offset 20 */
53 /* Overlay control register */
54 volatile u_int i20OvlyControl; /* Offset 24 */
55 /* System, PCI and general purpose pins control register */
56 volatile u_int i20SysControl; /* Offset 28 */
57 #define sysRESET 0x01000000 /* bit 24:Softreset (Low) */
58 /* GPIO 4...0: Output fixed for our cfg! */
59 #define sysCFG 0x000000E0 /* GPIO 7,6,5: Input */
60 /* General purpose pins and guest bus control register */
61 volatile u_int i20GuestControl;/* Offset 2C */
62 #define guestWAIT_CFG 0x00005555 /* 4 PCI waits for all */
63 #define guestISDN_INT_E 0x01000000 /* ISDN Int en (low) */
64 #define guestVID_INT_E 0x02000000 /* Video interrupt en (low) */
65 #define guestADI1_INT_R 0x04000000 /* ADI #1 int req (low) */
66 #define guestADI2_INT_R 0x08000000 /* ADI #2 int req (low) */
67 #define guestISDN_RES 0x10000000 /* ISDN reset bit (high) */
68 #define guestADI1_INT_S 0x20000000 /* ADI #1 int pending (low) */
69 #define guestADI2_INT_S 0x40000000 /* ADI #2 int pending (low) */
70 #define guestISDN_INT_S 0x80000000 /* ISAC int pending (low) */
71
72 #define g_A4T_JADE_RES 0x01000000 /* JADE Reset (High) */
73 #define g_A4T_ISAR_RES 0x02000000 /* ISAR Reset (High) */
74 #define g_A4T_ISAC_RES 0x04000000 /* ISAC Reset (High) */
75 #define g_A4T_JADE_BOOTR 0x08000000 /* JADE enable boot SRAM (Low) NOT USED */
76 #define g_A4T_ISAR_BOOTR 0x10000000 /* ISAR enable boot SRAM (Low) NOT USED */
77 #define g_A4T_JADE_INT_S 0x20000000 /* JADE interrupt pnd (Low) */
78 #define g_A4T_ISAR_INT_S 0x40000000 /* ISAR interrupt pnd (Low) */
79 #define g_A4T_ISAC_INT_S 0x80000000 /* ISAC interrupt pnd (Low) */
80
81 volatile u_int i20CodeSource; /* Offset 30 */
82 volatile u_int i20CodeXferCtrl;/* Offset 34 */
83 volatile u_int i20CodeMemPtr; /* Offset 38 */
84
85 volatile u_int i20IntStatus; /* Offset 3C */
86 volatile u_int i20IntCtrl; /* Offset 40 */
87 #define intISDN 0x40000000 /* GIRQ1En (ISAC/ADI) (High) */
88 #define intVID 0x20000000 /* GIRQ0En (VSYNC) (High) */
89 #define intCOD 0x10000000 /* CodRepIrqEn (High) */
90 #define intPCI 0x01000000 /* PCI IntA enable (High) */
91
92 volatile u_int i20I2CCtrl; /* Offset 44 */
93 } I20_REGISTER_FILE, *PI20_REGISTER_FILE;
94
95 /*
96 * Postoffice structure for A4T
97 *
98 */
99 #define PO_OFFSET 0x00000200 /* Postoffice offset from base */
100
101 #define GCS_0 0x00000000 /* Guest bus chip selects */
102 #define GCS_1 0x00100000
103 #define GCS_2 0x00200000
104 #define GCS_3 0x00300000
105
106 #define PO_READ 0x00000000 /* R/W from/to guest bus */
107 #define PO_WRITE 0x00800000
108
109 #define PO_PEND 0x02000000
110
111 #define POSTOFFICE(postoffice) *(volatile unsigned int*)(postoffice)
112
113 /* Wait unlimited (don't worry) */
114 #define __WAITI20__(postoffice) \
115 do { \
116 while ((POSTOFFICE(postoffice) & PO_PEND)) ; \
117 } while (0)
118
119 #endif /* __BKM_AX_H__ */
120
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