1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 *
33 * $Id: mthca_eq.c 1382 2004-12-24 02:21:02Z roland $
34 */
35
36 #include <linux/errno.h>
37 #include <linux/interrupt.h>
38 #include <linux/pci.h>
39
40 #include "mthca_dev.h"
41 #include "mthca_cmd.h"
42 #include "mthca_config_reg.h"
43
44 enum {
45 MTHCA_NUM_ASYNC_EQE = 0x80,
46 MTHCA_NUM_CMD_EQE = 0x80,
47 MTHCA_NUM_SPARE_EQE = 0x80,
48 MTHCA_EQ_ENTRY_SIZE = 0x20
49 };
50
51 /*
52 * Must be packed because start is 64 bits but only aligned to 32 bits.
53 */
54 struct mthca_eq_context {
55 __be32 flags;
56 __be64 start;
57 __be32 logsize_usrpage;
58 __be32 tavor_pd; /* reserved for Arbel */
59 u8 reserved1[3];
60 u8 intr;
61 __be32 arbel_pd; /* lost_count for Tavor */
62 __be32 lkey;
63 u32 reserved2[2];
64 __be32 consumer_index;
65 __be32 producer_index;
66 u32 reserved3[4];
67 } __attribute__((packed));
68
69 #define MTHCA_EQ_STATUS_OK ( 0 << 28)
70 #define MTHCA_EQ_STATUS_OVERFLOW ( 9 << 28)
71 #define MTHCA_EQ_STATUS_WRITE_FAIL (10 << 28)
72 #define MTHCA_EQ_OWNER_SW ( 0 << 24)
73 #define MTHCA_EQ_OWNER_HW ( 1 << 24)
74 #define MTHCA_EQ_FLAG_TR ( 1 << 18)
75 #define MTHCA_EQ_FLAG_OI ( 1 << 17)
76 #define MTHCA_EQ_STATE_ARMED ( 1 << 8)
77 #define MTHCA_EQ_STATE_FIRED ( 2 << 8)
78 #define MTHCA_EQ_STATE_ALWAYS_ARMED ( 3 << 8)
79 #define MTHCA_EQ_STATE_ARBEL ( 8 << 8)
80
81 enum {
82 MTHCA_EVENT_TYPE_COMP = 0x00,
83 MTHCA_EVENT_TYPE_PATH_MIG = 0x01,
84 MTHCA_EVENT_TYPE_COMM_EST = 0x02,
85 MTHCA_EVENT_TYPE_SQ_DRAINED = 0x03,
86 MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
87 MTHCA_EVENT_TYPE_SRQ_LIMIT = 0x14,
88 MTHCA_EVENT_TYPE_CQ_ERROR = 0x04,
89 MTHCA_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
90 MTHCA_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
91 MTHCA_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
92 MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
93 MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
94 MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
95 MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
96 MTHCA_EVENT_TYPE_PORT_CHANGE = 0x09,
97 MTHCA_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
98 MTHCA_EVENT_TYPE_ECC_DETECT = 0x0e,
99 MTHCA_EVENT_TYPE_CMD = 0x0a
100 };
101
102 #define MTHCA_ASYNC_EVENT_MASK ((1ULL << MTHCA_EVENT_TYPE_PATH_MIG) | \
103 (1ULL << MTHCA_EVENT_TYPE_COMM_EST) | \
104 (1ULL << MTHCA_EVENT_TYPE_SQ_DRAINED) | \
105 (1ULL << MTHCA_EVENT_TYPE_CQ_ERROR) | \
106 (1ULL << MTHCA_EVENT_TYPE_WQ_CATAS_ERROR) | \
107 (1ULL << MTHCA_EVENT_TYPE_EEC_CATAS_ERROR) | \
108 (1ULL << MTHCA_EVENT_TYPE_PATH_MIG_FAILED) | \
109 (1ULL << MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
110 (1ULL << MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR) | \
111 (1ULL << MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR) | \
112 (1ULL << MTHCA_EVENT_TYPE_PORT_CHANGE) | \
113 (1ULL << MTHCA_EVENT_TYPE_ECC_DETECT))
114 #define MTHCA_SRQ_EVENT_MASK ((1ULL << MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR) | \
115 (1ULL << MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
116 (1ULL << MTHCA_EVENT_TYPE_SRQ_LIMIT))
117 #define MTHCA_CMD_EVENT_MASK (1ULL << MTHCA_EVENT_TYPE_CMD)
118
119 #define MTHCA_EQ_DB_INC_CI (1 << 24)
120 #define MTHCA_EQ_DB_REQ_NOT (2 << 24)
121 #define MTHCA_EQ_DB_DISARM_CQ (3 << 24)
122 #define MTHCA_EQ_DB_SET_CI (4 << 24)
123 #define MTHCA_EQ_DB_ALWAYS_ARM (5 << 24)
124
125 struct mthca_eqe {
126 u8 reserved1;
127 u8 type;
128 u8 reserved2;
129 u8 subtype;
130 union {
131 u32 raw[6];
132 struct {
133 __be32 cqn;
134 } __attribute__((packed)) comp;
135 struct {
136 u16 reserved1;
137 __be16 token;
138 u32 reserved2;
139 u8 reserved3[3];
140 u8 status;
141 __be64 out_param;
142 } __attribute__((packed)) cmd;
143 struct {
144 __be32 qpn;
145 } __attribute__((packed)) qp;
146 struct {
147 __be32 srqn;
148 } __attribute__((packed)) srq;
149 struct {
150 __be32 cqn;
151 u32 reserved1;
152 u8 reserved2[3];
153 u8 syndrome;
154 } __attribute__((packed)) cq_err;
155 struct {
156 u32 reserved1[2];
157 __be32 port;
158 } __attribute__((packed)) port_change;
159 } event;
160 u8 reserved3[3];
161 u8 owner;
162 } __attribute__((packed));
163
164 #define MTHCA_EQ_ENTRY_OWNER_SW (0 << 7)
165 #define MTHCA_EQ_ENTRY_OWNER_HW (1 << 7)
166
167 static inline u64 async_mask(struct mthca_dev *dev)
168 {
169 return dev->mthca_flags & MTHCA_FLAG_SRQ ?
170 MTHCA_ASYNC_EVENT_MASK | MTHCA_SRQ_EVENT_MASK :
171 MTHCA_ASYNC_EVENT_MASK;
172 }
173
174 static inline void tavor_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
175 {
176 /*
177 * This barrier makes sure that all updates to ownership bits
178 * done by set_eqe_hw() hit memory before the consumer index
179 * is updated. set_eq_ci() allows the HCA to possibly write
180 * more EQ entries, and we want to avoid the exceedingly
181 * unlikely possibility of the HCA writing an entry and then
182 * having set_eqe_hw() overwrite the owner field.
183 */
184 wmb();
185 mthca_write64(MTHCA_EQ_DB_SET_CI | eq->eqn, ci & (eq->nent - 1),
186 dev->kar + MTHCA_EQ_DOORBELL,
187 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
188 }
189
190 static inline void arbel_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
191 {
192 /* See comment in tavor_set_eq_ci() above. */
193 wmb();
194 __raw_writel((__force u32) cpu_to_be32(ci),
195 dev->eq_regs.arbel.eq_set_ci_base + eq->eqn * 8);
196 /* We still want ordering, just not swabbing, so add a barrier */
197 mb();
198 }
199
200 static inline void set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
201 {
202 if (mthca_is_memfree(dev))
203 arbel_set_eq_ci(dev, eq, ci);
204 else
205 tavor_set_eq_ci(dev, eq, ci);
206 }
207
208 static inline void tavor_eq_req_not(struct mthca_dev *dev, int eqn)
209 {
210 mthca_write64(MTHCA_EQ_DB_REQ_NOT | eqn, 0,
211 dev->kar + MTHCA_EQ_DOORBELL,
212 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
213 }
214
215 static inline void arbel_eq_req_not(struct mthca_dev *dev, u32 eqn_mask)
216 {
217 writel(eqn_mask, dev->eq_regs.arbel.eq_arm);
218 }
219
220 static inline void disarm_cq(struct mthca_dev *dev, int eqn, int cqn)
221 {
222 if (!mthca_is_memfree(dev)) {
223 mthca_write64(MTHCA_EQ_DB_DISARM_CQ | eqn, cqn,
224 dev->kar + MTHCA_EQ_DOORBELL,
225 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
226 }
227 }
228
229 static inline struct mthca_eqe *get_eqe(struct mthca_eq *eq, u32 entry)
230 {
231 unsigned long off = (entry & (eq->nent - 1)) * MTHCA_EQ_ENTRY_SIZE;
232 return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
233 }
234
235 static inline struct mthca_eqe* next_eqe_sw(struct mthca_eq *eq)
236 {
237 struct mthca_eqe* eqe;
238 eqe = get_eqe(eq, eq->cons_index);
239 return (MTHCA_EQ_ENTRY_OWNER_HW & eqe->owner) ? NULL : eqe;
240 }
241
242 static inline void set_eqe_hw(struct mthca_eqe *eqe)
243 {
244 eqe->owner = MTHCA_EQ_ENTRY_OWNER_HW;
245 }
246
247 static void port_change(struct mthca_dev *dev, int port, int active)
248 {
249 struct ib_event record;
250
251 mthca_dbg(dev, "Port change to %s for port %d\n",
252 active ? "active" : "down", port);
253
254 record.device = &dev->ib_dev;
255 record.event = active ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
256 record.element.port_num = port;
257
258 ib_dispatch_event(&record);
259 }
260
261 static int mthca_eq_int(struct mthca_dev *dev, struct mthca_eq *eq)
262 {
263 struct mthca_eqe *eqe;
264 int disarm_cqn;
265 int eqes_found = 0;
266 int set_ci = 0;
267
268 while ((eqe = next_eqe_sw(eq))) {
269 /*
270 * Make sure we read EQ entry contents after we've
271 * checked the ownership bit.
272 */
273 rmb();
274
275 switch (eqe->type) {
276 case MTHCA_EVENT_TYPE_COMP:
277 disarm_cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
278 disarm_cq(dev, eq->eqn, disarm_cqn);
279 mthca_cq_completion(dev, disarm_cqn);
280 break;
281
282 case MTHCA_EVENT_TYPE_PATH_MIG:
283 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
284 IB_EVENT_PATH_MIG);
285 break;
286
287 case MTHCA_EVENT_TYPE_COMM_EST:
288 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
289 IB_EVENT_COMM_EST);
290 break;
291
292 case MTHCA_EVENT_TYPE_SQ_DRAINED:
293 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
294 IB_EVENT_SQ_DRAINED);
295 break;
296
297 case MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE:
298 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
299 IB_EVENT_QP_LAST_WQE_REACHED);
300 break;
301
302 case MTHCA_EVENT_TYPE_SRQ_LIMIT:
303 mthca_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff,
304 IB_EVENT_SRQ_LIMIT_REACHED);
305 break;
306
307 case MTHCA_EVENT_TYPE_WQ_CATAS_ERROR:
308 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
309 IB_EVENT_QP_FATAL);
310 break;
311
312 case MTHCA_EVENT_TYPE_PATH_MIG_FAILED:
313 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
314 IB_EVENT_PATH_MIG_ERR);
315 break;
316
317 case MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
318 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
319 IB_EVENT_QP_REQ_ERR);
320 break;
321
322 case MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR:
323 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
324 IB_EVENT_QP_ACCESS_ERR);
325 break;
326
327 case MTHCA_EVENT_TYPE_CMD:
328 mthca_cmd_event(dev,
329 be16_to_cpu(eqe->event.cmd.token),
330 eqe->event.cmd.status,
331 be64_to_cpu(eqe->event.cmd.out_param));
332 break;
333
334 case MTHCA_EVENT_TYPE_PORT_CHANGE:
335 port_change(dev,
336 (be32_to_cpu(eqe->event.port_change.port) >> 28) & 3,
337 eqe->subtype == 0x4);
338 break;
339
340 case MTHCA_EVENT_TYPE_CQ_ERROR:
341 mthca_warn(dev, "CQ %s on CQN %06x\n",
342 eqe->event.cq_err.syndrome == 1 ?
343 "overrun" : "access violation",
344 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
345 mthca_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn),
346 IB_EVENT_CQ_ERR);
347 break;
348
349 case MTHCA_EVENT_TYPE_EQ_OVERFLOW:
350 mthca_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
351 break;
352
353 case MTHCA_EVENT_TYPE_EEC_CATAS_ERROR:
354 case MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR:
355 case MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR:
356 case MTHCA_EVENT_TYPE_ECC_DETECT:
357 default:
358 mthca_warn(dev, "Unhandled event %02x(%02x) on EQ %d\n",
359 eqe->type, eqe->subtype, eq->eqn);
360 break;
361 };
362
363 set_eqe_hw(eqe);
364 ++eq->cons_index;
365 eqes_found = 1;
366 ++set_ci;
367
368 /*
369 * The HCA will think the queue has overflowed if we
370 * don't tell it we've been processing events. We
371 * create our EQs with MTHCA_NUM_SPARE_EQE extra
372 * entries, so we must update our consumer index at
373 * least that often.
374 */
375 if (unlikely(set_ci >= MTHCA_NUM_SPARE_EQE)) {
376 /*
377 * Conditional on hca_type is OK here because
378 * this is a rare case, not the fast path.
379 */
380 set_eq_ci(dev, eq, eq->cons_index);
381 set_ci = 0;
382 }
383 }
384
385 /*
386 * Rely on caller to set consumer index so that we don't have
387 * to test hca_type in our interrupt handling fast path.
388 */
389 return eqes_found;
390 }
391
392 static irqreturn_t mthca_tavor_interrupt(int irq, void *dev_ptr)
393 {
394 struct mthca_dev *dev = dev_ptr;
395 u32 ecr;
396 int i;
397
398 if (dev->eq_table.clr_mask)
399 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int);
400
401 ecr = readl(dev->eq_regs.tavor.ecr_base + 4);
402 if (!ecr)
403 return IRQ_NONE;
404
405 writel(ecr, dev->eq_regs.tavor.ecr_base +
406 MTHCA_ECR_CLR_BASE - MTHCA_ECR_BASE + 4);
407
408 for (i = 0; i < MTHCA_NUM_EQ; ++i)
409 if (ecr & dev->eq_table.eq[i].eqn_mask) {
410 if (mthca_eq_int(dev, &dev->eq_table.eq[i]))
411 tavor_set_eq_ci(dev, &dev->eq_table.eq[i],
412 dev->eq_table.eq[i].cons_index);
413 tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn);
414 }
415
416 return IRQ_HANDLED;
417 }
418
419 static irqreturn_t mthca_tavor_msi_x_interrupt(int irq, void *eq_ptr)
420 {
421 struct mthca_eq *eq = eq_ptr;
422 struct mthca_dev *dev = eq->dev;
423
424 mthca_eq_int(dev, eq);
425 tavor_set_eq_ci(dev, eq, eq->cons_index);
426 tavor_eq_req_not(dev, eq->eqn);
427
428 /* MSI-X vectors always belong to us */
429 return IRQ_HANDLED;
430 }
431
432 static irqreturn_t mthca_arbel_interrupt(int irq, void *dev_ptr)
433 {
434 struct mthca_dev *dev = dev_ptr;
435 int work = 0;
436 int i;
437
438 if (dev->eq_table.clr_mask)
439 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int);
440
441 for (i = 0; i < MTHCA_NUM_EQ; ++i)
442 if (mthca_eq_int(dev, &dev->eq_table.eq[i])) {
443 work = 1;
444 arbel_set_eq_ci(dev, &dev->eq_table.eq[i],
445 dev->eq_table.eq[i].cons_index);
446 }
447
448 arbel_eq_req_not(dev, dev->eq_table.arm_mask);
449
450 return IRQ_RETVAL(work);
451 }
452
453 static irqreturn_t mthca_arbel_msi_x_interrupt(int irq, void *eq_ptr)
454 {
455 struct mthca_eq *eq = eq_ptr;
456 struct mthca_dev *dev = eq->dev;
457
458 mthca_eq_int(dev, eq);
459 arbel_set_eq_ci(dev, eq, eq->cons_index);
460 arbel_eq_req_not(dev, eq->eqn_mask);
461
462 /* MSI-X vectors always belong to us */
463 return IRQ_HANDLED;
464 }
465
466 static int mthca_create_eq(struct mthca_dev *dev,
467 int nent,
468 u8 intr,
469 struct mthca_eq *eq)
470 {
471 int npages;
472 u64 *dma_list = NULL;
473 dma_addr_t t;
474 struct mthca_mailbox *mailbox;
475 struct mthca_eq_context *eq_context;
476 int err = -ENOMEM;
477 int i;
478 u8 status;
479
480 eq->dev = dev;
481 eq->nent = roundup_pow_of_two(max(nent, 2));
482 npages = ALIGN(eq->nent * MTHCA_EQ_ENTRY_SIZE, PAGE_SIZE) / PAGE_SIZE;
483
484 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
485 GFP_KERNEL);
486 if (!eq->page_list)
487 goto err_out;
488
489 for (i = 0; i < npages; ++i)
490 eq->page_list[i].buf = NULL;
491
492 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
493 if (!dma_list)
494 goto err_out_free;
495
496 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
497 if (IS_ERR(mailbox))
498 goto err_out_free;
499 eq_context = mailbox->buf;
500
501 for (i = 0; i < npages; ++i) {
502 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
503 PAGE_SIZE, &t, GFP_KERNEL);
504 if (!eq->page_list[i].buf)
505 goto err_out_free_pages;
506
507 dma_list[i] = t;
508 pci_unmap_addr_set(&eq->page_list[i], mapping, t);
509
510 clear_page(eq->page_list[i].buf);
511 }
512
513 for (i = 0; i < eq->nent; ++i)
514 set_eqe_hw(get_eqe(eq, i));
515
516 eq->eqn = mthca_alloc(&dev->eq_table.alloc);
517 if (eq->eqn == -1)
518 goto err_out_free_pages;
519
520 err = mthca_mr_alloc_phys(dev, dev->driver_pd.pd_num,
521 dma_list, PAGE_SHIFT, npages,
522 0, npages * PAGE_SIZE,
523 MTHCA_MPT_FLAG_LOCAL_WRITE |
524 MTHCA_MPT_FLAG_LOCAL_READ,
525 &eq->mr);
526 if (err)
527 goto err_out_free_eq;
528
529 memset(eq_context, 0, sizeof *eq_context);
530 eq_context->flags = cpu_to_be32(MTHCA_EQ_STATUS_OK |
531 MTHCA_EQ_OWNER_HW |
532 MTHCA_EQ_STATE_ARMED |
533 MTHCA_EQ_FLAG_TR);
534 if (mthca_is_memfree(dev))
535 eq_context->flags |= cpu_to_be32(MTHCA_EQ_STATE_ARBEL);
536
537 eq_context->logsize_usrpage = cpu_to_be32((ffs(eq->nent) - 1) << 24);
538 if (mthca_is_memfree(dev)) {
539 eq_context->arbel_pd = cpu_to_be32(dev->driver_pd.pd_num);
540 } else {
541 eq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
542 eq_context->tavor_pd = cpu_to_be32(dev->driver_pd.pd_num);
543 }
544 eq_context->intr = intr;
545 eq_context->lkey = cpu_to_be32(eq->mr.ibmr.lkey);
546
547 err = mthca_SW2HW_EQ(dev, mailbox, eq->eqn, &status);
548 if (err) {
549 mthca_warn(dev, "SW2HW_EQ failed (%d)\n", err);
550 goto err_out_free_mr;
551 }
552 if (status) {
553 mthca_warn(dev, "SW2HW_EQ returned status 0x%02x\n",
554 status);
555 err = -EINVAL;
556 goto err_out_free_mr;
557 }
558
559 kfree(dma_list);
560 mthca_free_mailbox(dev, mailbox);
561
562 eq->eqn_mask = swab32(1 << eq->eqn);
563 eq->cons_index = 0;
564
565 dev->eq_table.arm_mask |= eq->eqn_mask;
566
567 mthca_dbg(dev, "Allocated EQ %d with %d entries\n",
568 eq->eqn, eq->nent);
569
570 return err;
571
572 err_out_free_mr:
573 mthca_free_mr(dev, &eq->mr);
574
575 err_out_free_eq:
576 mthca_free(&dev->eq_table.alloc, eq->eqn);
577
578 err_out_free_pages:
579 for (i = 0; i < npages; ++i)
580 if (eq->page_list[i].buf)
581 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
582 eq->page_list[i].buf,
583 pci_unmap_addr(&eq->page_list[i],
584 mapping));
585
586 mthca_free_mailbox(dev, mailbox);
587
588 err_out_free:
589 kfree(eq->page_list);
590 kfree(dma_list);
591
592 err_out:
593 return err;
594 }
595
596 static void mthca_free_eq(struct mthca_dev *dev,
597 struct mthca_eq *eq)
598 {
599 struct mthca_mailbox *mailbox;
600 int err;
601 u8 status;
602 int npages = (eq->nent * MTHCA_EQ_ENTRY_SIZE + PAGE_SIZE - 1) /
603 PAGE_SIZE;
604 int i;
605
606 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
607 if (IS_ERR(mailbox))
608 return;
609
610 err = mthca_HW2SW_EQ(dev, mailbox, eq->eqn, &status);
611 if (err)
612 mthca_warn(dev, "HW2SW_EQ failed (%d)\n", err);
613 if (status)
614 mthca_warn(dev, "HW2SW_EQ returned status 0x%02x\n", status);
615
616 dev->eq_table.arm_mask &= ~eq->eqn_mask;
617
618 if (0) {
619 mthca_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
620 for (i = 0; i < sizeof (struct mthca_eq_context) / 4; ++i) {
621 if (i % 4 == 0)
622 printk("[%02x] ", i * 4);
623 printk(" %08x", be32_to_cpup(mailbox->buf + i * 4));
624 if ((i + 1) % 4 == 0)
625 printk("\n");
626 }
627 }
628
629 mthca_free_mr(dev, &eq->mr);
630 for (i = 0; i < npages; ++i)
631 pci_free_consistent(dev->pdev, PAGE_SIZE,
632 eq->page_list[i].buf,
633 pci_unmap_addr(&eq->page_list[i], mapping));
634
635 kfree(eq->page_list);
636 mthca_free_mailbox(dev, mailbox);
637 }
638
639 static void mthca_free_irqs(struct mthca_dev *dev)
640 {
641 int i;
642
643 if (dev->eq_table.have_irq)
644 free_irq(dev->pdev->irq, dev);
645 for (i = 0; i < MTHCA_NUM_EQ; ++i)
646 if (dev->eq_table.eq[i].have_irq)
647 free_irq(dev->eq_table.eq[i].msi_x_vector,
648 dev->eq_table.eq + i);
649 }
650
651 static int mthca_map_reg(struct mthca_dev *dev,
652 unsigned long offset, unsigned long size,
653 void __iomem **map)
654 {
655 unsigned long base = pci_resource_start(dev->pdev, 0);
656
657 if (!request_mem_region(base + offset, size, DRV_NAME))
658 return -EBUSY;
659
660 *map = ioremap(base + offset, size);
661 if (!*map) {
662 release_mem_region(base + offset, size);
663 return -ENOMEM;
664 }
665
666 return 0;
667 }
668
669 static void mthca_unmap_reg(struct mthca_dev *dev, unsigned long offset,
670 unsigned long size, void __iomem *map)
671 {
672 unsigned long base = pci_resource_start(dev->pdev, 0);
673
674 release_mem_region(base + offset, size);
675 iounmap(map);
676 }
677
678 static int mthca_map_eq_regs(struct mthca_dev *dev)
679 {
680 if (mthca_is_memfree(dev)) {
681 /*
682 * We assume that the EQ arm and EQ set CI registers
683 * fall within the first BAR. We can't trust the
684 * values firmware gives us, since those addresses are
685 * valid on the HCA's side of the PCI bus but not
686 * necessarily the host side.
687 */
688 if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
689 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
690 &dev->clr_base)) {
691 mthca_err(dev, "Couldn't map interrupt clear register, "
692 "aborting.\n");
693 return -ENOMEM;
694 }
695
696 /*
697 * Add 4 because we limit ourselves to EQs 0 ... 31,
698 * so we only need the low word of the register.
699 */
700 if (mthca_map_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &
701 dev->fw.arbel.eq_arm_base) + 4, 4,
702 &dev->eq_regs.arbel.eq_arm)) {
703 mthca_err(dev, "Couldn't map EQ arm register, aborting.\n");
704 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
705 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
706 dev->clr_base);
707 return -ENOMEM;
708 }
709
710 if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
711 dev->fw.arbel.eq_set_ci_base,
712 MTHCA_EQ_SET_CI_SIZE,
713 &dev->eq_regs.arbel.eq_set_ci_base)) {
714 mthca_err(dev, "Couldn't map EQ CI register, aborting.\n");
715 mthca_unmap_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &
716 dev->fw.arbel.eq_arm_base) + 4, 4,
717 dev->eq_regs.arbel.eq_arm);
718 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
719 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
720 dev->clr_base);
721 return -ENOMEM;
722 }
723 } else {
724 if (mthca_map_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE,
725 &dev->clr_base)) {
726 mthca_err(dev, "Couldn't map interrupt clear register, "
727 "aborting.\n");
728 return -ENOMEM;
729 }
730
731 if (mthca_map_reg(dev, MTHCA_ECR_BASE,
732 MTHCA_ECR_SIZE + MTHCA_ECR_CLR_SIZE,
733 &dev->eq_regs.tavor.ecr_base)) {
734 mthca_err(dev, "Couldn't map ecr register, "
735 "aborting.\n");
736 mthca_unmap_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE,
737 dev->clr_base);
738 return -ENOMEM;
739 }
740 }
741
742 return 0;
743
744 }
745
746 static void mthca_unmap_eq_regs(struct mthca_dev *dev)
747 {
748 if (mthca_is_memfree(dev)) {
749 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
750 dev->fw.arbel.eq_set_ci_base,
751 MTHCA_EQ_SET_CI_SIZE,
752 dev->eq_regs.arbel.eq_set_ci_base);
753 mthca_unmap_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &
754 dev->fw.arbel.eq_arm_base) + 4, 4,
755 dev->eq_regs.arbel.eq_arm);
756 mthca_unmap_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &
757 dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE,
758 dev->clr_base);
759 } else {
760 mthca_unmap_reg(dev, MTHCA_ECR_BASE,
761 MTHCA_ECR_SIZE + MTHCA_ECR_CLR_SIZE,
762 dev->eq_regs.tavor.ecr_base);
763 mthca_unmap_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE,
764 dev->clr_base);
765 }
766 }
767
768 int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt)
769 {
770 int ret;
771 u8 status;
772
773 /*
774 * We assume that mapping one page is enough for the whole EQ
775 * context table. This is fine with all current HCAs, because
776 * we only use 32 EQs and each EQ uses 32 bytes of context
777 * memory, or 1 KB total.
778 */
779 dev->eq_table.icm_virt = icm_virt;
780 dev->eq_table.icm_page = alloc_page(GFP_HIGHUSER);
781 if (!dev->eq_table.icm_page)
782 return -ENOMEM;
783 dev->eq_table.icm_dma = pci_map_page(dev->pdev, dev->eq_table.icm_page, 0,
784 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
785 if (pci_dma_mapping_error(dev->eq_table.icm_dma)) {
786 __free_page(dev->eq_table.icm_page);
787 return -ENOMEM;
788 }
789
790 ret = mthca_MAP_ICM_page(dev, dev->eq_table.icm_dma, icm_virt, &status);
791 if (!ret && status)
792 ret = -EINVAL;
793 if (ret) {
794 pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE,
795 PCI_DMA_BIDIRECTIONAL);
796 __free_page(dev->eq_table.icm_page);
797 }
798
799 return ret;
800 }
801
802 void mthca_unmap_eq_icm(struct mthca_dev *dev)
803 {
804 u8 status;
805
806 mthca_UNMAP_ICM(dev, dev->eq_table.icm_virt, 1, &status);
807 pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE,
808 PCI_DMA_BIDIRECTIONAL);
809 __free_page(dev->eq_table.icm_page);
810 }
811
812 int mthca_init_eq_table(struct mthca_dev *dev)
813 {
814 int err;
815 u8 status;
816 u8 intr;
817 int i;
818
819 err = mthca_alloc_init(&dev->eq_table.alloc,
820 dev->limits.num_eqs,
821 dev->limits.num_eqs - 1,
822 dev->limits.reserved_eqs);
823 if (err)
824 return err;
825
826 err = mthca_map_eq_regs(dev);
827 if (err)
828 goto err_out_free;
829
830 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
831 dev->eq_table.clr_mask = 0;
832 } else {
833 dev->eq_table.clr_mask =
834 swab32(1 << (dev->eq_table.inta_pin & 31));
835 dev->eq_table.clr_int = dev->clr_base +
836 (dev->eq_table.inta_pin < 32 ? 4 : 0);
837 }
838
839 dev->eq_table.arm_mask = 0;
840
841 intr = dev->eq_table.inta_pin;
842
843 err = mthca_create_eq(dev, dev->limits.num_cqs + MTHCA_NUM_SPARE_EQE,
844 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 128 : intr,
845 &dev->eq_table.eq[MTHCA_EQ_COMP]);
846 if (err)
847 goto err_out_unmap;
848
849 err = mthca_create_eq(dev, MTHCA_NUM_ASYNC_EQE + MTHCA_NUM_SPARE_EQE,
850 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 129 : intr,
851 &dev->eq_table.eq[MTHCA_EQ_ASYNC]);
852 if (err)
853 goto err_out_comp;
854
855 err = mthca_create_eq(dev, MTHCA_NUM_CMD_EQE + MTHCA_NUM_SPARE_EQE,
856 (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 130 : intr,
857 &dev->eq_table.eq[MTHCA_EQ_CMD]);
858 if (err)
859 goto err_out_async;
860
861 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
862 static const char *eq_name[] = {
863 [MTHCA_EQ_COMP] = DRV_NAME " (comp)",
864 [MTHCA_EQ_ASYNC] = DRV_NAME " (async)",
865 [MTHCA_EQ_CMD] = DRV_NAME " (cmd)"
866 };
867
868 for (i = 0; i < MTHCA_NUM_EQ; ++i) {
869 err = request_irq(dev->eq_table.eq[i].msi_x_vector,
870 mthca_is_memfree(dev) ?
871 mthca_arbel_msi_x_interrupt :
872 mthca_tavor_msi_x_interrupt,
873 0, eq_name[i], dev->eq_table.eq + i);
874 if (err)
875 goto err_out_cmd;
876 dev->eq_table.eq[i].have_irq = 1;
877 }
878 } else {
879 err = request_irq(dev->pdev->irq,
880 mthca_is_memfree(dev) ?
881 mthca_arbel_interrupt :
882 mthca_tavor_interrupt,
883 IRQF_SHARED, DRV_NAME, dev);
884 if (err)
885 goto err_out_cmd;
886 dev->eq_table.have_irq = 1;
887 }
888
889 err = mthca_MAP_EQ(dev, async_mask(dev),
890 0, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, &status);
891 if (err)
892 mthca_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
893 dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, err);
894 if (status)
895 mthca_warn(dev, "MAP_EQ for async EQ %d returned status 0x%02x\n",
896 dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, status);
897
898 err = mthca_MAP_EQ(dev, MTHCA_CMD_EVENT_MASK,
899 0, dev->eq_table.eq[MTHCA_EQ_CMD].eqn, &status);
900 if (err)
901 mthca_warn(dev, "MAP_EQ for cmd EQ %d failed (%d)\n",
902 dev->eq_table.eq[MTHCA_EQ_CMD].eqn, err);
903 if (status)
904 mthca_warn(dev, "MAP_EQ for cmd EQ %d returned status 0x%02x\n",
905 dev->eq_table.eq[MTHCA_EQ_CMD].eqn, status);
906
907 for (i = 0; i < MTHCA_NUM_EQ; ++i)
908 if (mthca_is_memfree(dev))
909 arbel_eq_req_not(dev, dev->eq_table.eq[i].eqn_mask);
910 else
911 tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn);
912
913 return 0;
914
915 err_out_cmd:
916 mthca_free_irqs(dev);
917 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_CMD]);
918
919 err_out_async:
920 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_ASYNC]);
921
922 err_out_comp:
923 mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_COMP]);
924
925 err_out_unmap:
926 mthca_unmap_eq_regs(dev);
927
928 err_out_free:
929 mthca_alloc_cleanup(&dev->eq_table.alloc);
930 return err;
931 }
932
933 void mthca_cleanup_eq_table(struct mthca_dev *dev)
934 {
935 u8 status;
936 int i;
937
938 mthca_free_irqs(dev);
939
940 mthca_MAP_EQ(dev, async_mask(dev),
941 1, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, &status);
942 mthca_MAP_EQ(dev, MTHCA_CMD_EVENT_MASK,
943 1, dev->eq_table.eq[MTHCA_EQ_CMD].eqn, &status);
944
945 for (i = 0; i < MTHCA_NUM_EQ; ++i)
946 mthca_free_eq(dev, &dev->eq_table.eq[i]);
947
948 mthca_unmap_eq_regs(dev);
949
950 mthca_alloc_cleanup(&dev->eq_table.alloc);
951 }
952
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