1 /*
2 * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __CXIO_HAL_H__
33 #define __CXIO_HAL_H__
34
35 #include <linux/list.h>
36 #include <linux/mutex.h>
37
38 #include "t3_cpl.h"
39 #include "t3cdev.h"
40 #include "cxgb3_ctl_defs.h"
41 #include "cxio_wr.h"
42
43 #define T3_CTRL_QP_ID FW_RI_SGEEC_START
44 #define T3_CTL_QP_TID FW_RI_TID_START
45 #define T3_CTRL_QP_SIZE_LOG2 8
46 #define T3_CTRL_CQ_ID 0
47
48 /* TBD */
49 #define T3_MAX_NUM_RI (1<<15)
50 #define T3_MAX_NUM_QP (1<<15)
51 #define T3_MAX_NUM_CQ (1<<15)
52 #define T3_MAX_NUM_PD (1<<15)
53 #define T3_MAX_PBL_SIZE 256
54 #define T3_MAX_RQ_SIZE 1024
55 #define T3_MAX_NUM_STAG (1<<15)
56
57 #define T3_STAG_UNSET 0xffffffff
58
59 #define T3_MAX_DEV_NAME_LEN 32
60
61 struct cxio_hal_ctrl_qp {
62 u32 wptr;
63 u32 rptr;
64 struct mutex lock; /* for the wtpr, can sleep */
65 wait_queue_head_t waitq;/* wait for RspQ/CQE msg */
66 union t3_wr *workq; /* the work request queue */
67 dma_addr_t dma_addr; /* pci bus address of the workq */
68 DECLARE_PCI_UNMAP_ADDR(mapping)
69 void __iomem *doorbell;
70 };
71
72 struct cxio_hal_resource {
73 struct kfifo *tpt_fifo;
74 spinlock_t tpt_fifo_lock;
75 struct kfifo *qpid_fifo;
76 spinlock_t qpid_fifo_lock;
77 struct kfifo *cqid_fifo;
78 spinlock_t cqid_fifo_lock;
79 struct kfifo *pdid_fifo;
80 spinlock_t pdid_fifo_lock;
81 };
82
83 struct cxio_qpid_list {
84 struct list_head entry;
85 u32 qpid;
86 };
87
88 struct cxio_ucontext {
89 struct list_head qpids;
90 struct mutex lock;
91 };
92
93 struct cxio_rdev {
94 char dev_name[T3_MAX_DEV_NAME_LEN];
95 struct t3cdev *t3cdev_p;
96 struct rdma_info rnic_info;
97 struct adap_ports port_info;
98 struct cxio_hal_resource *rscp;
99 struct cxio_hal_ctrl_qp ctrl_qp;
100 void *ulp;
101 unsigned long qpshift;
102 u32 qpnr;
103 u32 qpmask;
104 struct cxio_ucontext uctx;
105 struct gen_pool *pbl_pool;
106 struct gen_pool *rqt_pool;
107 struct list_head entry;
108 };
109
110 static inline int cxio_num_stags(struct cxio_rdev *rdev_p)
111 {
112 return min((int)T3_MAX_NUM_STAG, (int)((rdev_p->rnic_info.tpt_top - rdev_p->rnic_info.tpt_base) >> 5));
113 }
114
115 typedef void (*cxio_hal_ev_callback_func_t) (struct cxio_rdev * rdev_p,
116 struct sk_buff * skb);
117
118 #define RSPQ_CQID(rsp) (be32_to_cpu(rsp->cq_ptrid) & 0xffff)
119 #define RSPQ_CQPTR(rsp) ((be32_to_cpu(rsp->cq_ptrid) >> 16) & 0xffff)
120 #define RSPQ_GENBIT(rsp) ((be32_to_cpu(rsp->flags) >> 16) & 1)
121 #define RSPQ_OVERFLOW(rsp) ((be32_to_cpu(rsp->flags) >> 17) & 1)
122 #define RSPQ_AN(rsp) ((be32_to_cpu(rsp->flags) >> 18) & 1)
123 #define RSPQ_SE(rsp) ((be32_to_cpu(rsp->flags) >> 19) & 1)
124 #define RSPQ_NOTIFY(rsp) ((be32_to_cpu(rsp->flags) >> 20) & 1)
125 #define RSPQ_CQBRANCH(rsp) ((be32_to_cpu(rsp->flags) >> 21) & 1)
126 #define RSPQ_CREDIT_THRESH(rsp) ((be32_to_cpu(rsp->flags) >> 22) & 1)
127
128 struct respQ_msg_t {
129 __be32 flags; /* flit 0 */
130 __be32 cq_ptrid;
131 __be64 rsvd; /* flit 1 */
132 struct t3_cqe cqe; /* flits 2-3 */
133 };
134
135 enum t3_cq_opcode {
136 CQ_ARM_AN = 0x2,
137 CQ_ARM_SE = 0x6,
138 CQ_FORCE_AN = 0x3,
139 CQ_CREDIT_UPDATE = 0x7
140 };
141
142 int cxio_rdev_open(struct cxio_rdev *rdev);
143 void cxio_rdev_close(struct cxio_rdev *rdev);
144 int cxio_hal_cq_op(struct cxio_rdev *rdev, struct t3_cq *cq,
145 enum t3_cq_opcode op, u32 credit);
146 int cxio_create_cq(struct cxio_rdev *rdev, struct t3_cq *cq);
147 int cxio_destroy_cq(struct cxio_rdev *rdev, struct t3_cq *cq);
148 int cxio_resize_cq(struct cxio_rdev *rdev, struct t3_cq *cq);
149 void cxio_release_ucontext(struct cxio_rdev *rdev, struct cxio_ucontext *uctx);
150 void cxio_init_ucontext(struct cxio_rdev *rdev, struct cxio_ucontext *uctx);
151 int cxio_create_qp(struct cxio_rdev *rdev, u32 kernel_domain, struct t3_wq *wq,
152 struct cxio_ucontext *uctx);
153 int cxio_destroy_qp(struct cxio_rdev *rdev, struct t3_wq *wq,
154 struct cxio_ucontext *uctx);
155 int cxio_peek_cq(struct t3_wq *wr, struct t3_cq *cq, int opcode);
156 int cxio_register_phys_mem(struct cxio_rdev *rdev, u32 * stag, u32 pdid,
157 enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
158 u8 page_size, __be64 *pbl, u32 *pbl_size,
159 u32 *pbl_addr);
160 int cxio_reregister_phys_mem(struct cxio_rdev *rdev, u32 * stag, u32 pdid,
161 enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
162 u8 page_size, __be64 *pbl, u32 *pbl_size,
163 u32 *pbl_addr);
164 int cxio_dereg_mem(struct cxio_rdev *rdev, u32 stag, u32 pbl_size,
165 u32 pbl_addr);
166 int cxio_allocate_window(struct cxio_rdev *rdev, u32 * stag, u32 pdid);
167 int cxio_deallocate_window(struct cxio_rdev *rdev, u32 stag);
168 int cxio_rdma_init(struct cxio_rdev *rdev, struct t3_rdma_init_attr *attr);
169 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb);
170 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb);
171 u32 cxio_hal_get_pdid(struct cxio_hal_resource *rscp);
172 void cxio_hal_put_pdid(struct cxio_hal_resource *rscp, u32 pdid);
173 int __init cxio_hal_init(void);
174 void __exit cxio_hal_exit(void);
175 void cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count);
176 void cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count);
177 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count);
178 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count);
179 void cxio_flush_hw_cq(struct t3_cq *cq);
180 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
181 u8 *cqe_flushed, u64 *cookie, u32 *credit);
182
183 #define MOD "iw_cxgb3: "
184 #define PDBG(fmt, args...) pr_debug(MOD fmt, ## args)
185
186 #ifdef DEBUG
187 void cxio_dump_tpt(struct cxio_rdev *rev, u32 stag);
188 void cxio_dump_pbl(struct cxio_rdev *rev, u32 pbl_addr, uint len, u8 shift);
189 void cxio_dump_wqe(union t3_wr *wqe);
190 void cxio_dump_wce(struct t3_cqe *wce);
191 void cxio_dump_rqt(struct cxio_rdev *rdev, u32 hwtid, int nents);
192 void cxio_dump_tcb(struct cxio_rdev *rdev, u32 hwtid);
193 #endif
194
195 #endif
196
|
This page was automatically generated by the
LXR engine.
|