1 /*
2 * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __CXIO_HAL_H__
33 #define __CXIO_HAL_H__
34
35 #include <linux/list.h>
36 #include <linux/mutex.h>
37
38 #include "t3_cpl.h"
39 #include "t3cdev.h"
40 #include "cxgb3_ctl_defs.h"
41 #include "cxio_wr.h"
42
43 #define T3_CTRL_QP_ID FW_RI_SGEEC_START
44 #define T3_CTL_QP_TID FW_RI_TID_START
45 #define T3_CTRL_QP_SIZE_LOG2 8
46 #define T3_CTRL_CQ_ID 0
47
48 #define T3_MAX_NUM_RI (1<<15)
49 #define T3_MAX_NUM_QP (1<<15)
50 #define T3_MAX_NUM_CQ (1<<15)
51 #define T3_MAX_NUM_PD (1<<15)
52 #define T3_MAX_PBL_SIZE 256
53 #define T3_MAX_RQ_SIZE 1024
54 #define T3_MAX_QP_DEPTH (T3_MAX_RQ_SIZE-1)
55 #define T3_MAX_CQ_DEPTH 8192
56 #define T3_MAX_NUM_STAG (1<<15)
57 #define T3_MAX_MR_SIZE 0x100000000ULL
58 #define T3_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
59
60 #define T3_STAG_UNSET 0xffffffff
61
62 #define T3_MAX_DEV_NAME_LEN 32
63
64 #define CXIO_FW_MAJ 7
65
66 struct cxio_hal_ctrl_qp {
67 u32 wptr;
68 u32 rptr;
69 struct mutex lock; /* for the wtpr, can sleep */
70 wait_queue_head_t waitq;/* wait for RspQ/CQE msg */
71 union t3_wr *workq; /* the work request queue */
72 dma_addr_t dma_addr; /* pci bus address of the workq */
73 DECLARE_PCI_UNMAP_ADDR(mapping)
74 void __iomem *doorbell;
75 };
76
77 struct cxio_hal_resource {
78 struct kfifo *tpt_fifo;
79 spinlock_t tpt_fifo_lock;
80 struct kfifo *qpid_fifo;
81 spinlock_t qpid_fifo_lock;
82 struct kfifo *cqid_fifo;
83 spinlock_t cqid_fifo_lock;
84 struct kfifo *pdid_fifo;
85 spinlock_t pdid_fifo_lock;
86 };
87
88 struct cxio_qpid_list {
89 struct list_head entry;
90 u32 qpid;
91 };
92
93 struct cxio_ucontext {
94 struct list_head qpids;
95 struct mutex lock;
96 };
97
98 struct cxio_rdev {
99 char dev_name[T3_MAX_DEV_NAME_LEN];
100 struct t3cdev *t3cdev_p;
101 struct rdma_info rnic_info;
102 struct adap_ports port_info;
103 struct cxio_hal_resource *rscp;
104 struct cxio_hal_ctrl_qp ctrl_qp;
105 void *ulp;
106 unsigned long qpshift;
107 u32 qpnr;
108 u32 qpmask;
109 struct cxio_ucontext uctx;
110 struct gen_pool *pbl_pool;
111 struct gen_pool *rqt_pool;
112 struct list_head entry;
113 struct ch_embedded_info fw_info;
114 u32 flags;
115 #define CXIO_ERROR_FATAL 1
116 };
117
118 static inline int cxio_fatal_error(struct cxio_rdev *rdev_p)
119 {
120 return rdev_p->flags & CXIO_ERROR_FATAL;
121 }
122
123 static inline int cxio_num_stags(struct cxio_rdev *rdev_p)
124 {
125 return min((int)T3_MAX_NUM_STAG, (int)((rdev_p->rnic_info.tpt_top - rdev_p->rnic_info.tpt_base) >> 5));
126 }
127
128 typedef void (*cxio_hal_ev_callback_func_t) (struct cxio_rdev * rdev_p,
129 struct sk_buff * skb);
130
131 #define RSPQ_CQID(rsp) (be32_to_cpu(rsp->cq_ptrid) & 0xffff)
132 #define RSPQ_CQPTR(rsp) ((be32_to_cpu(rsp->cq_ptrid) >> 16) & 0xffff)
133 #define RSPQ_GENBIT(rsp) ((be32_to_cpu(rsp->flags) >> 16) & 1)
134 #define RSPQ_OVERFLOW(rsp) ((be32_to_cpu(rsp->flags) >> 17) & 1)
135 #define RSPQ_AN(rsp) ((be32_to_cpu(rsp->flags) >> 18) & 1)
136 #define RSPQ_SE(rsp) ((be32_to_cpu(rsp->flags) >> 19) & 1)
137 #define RSPQ_NOTIFY(rsp) ((be32_to_cpu(rsp->flags) >> 20) & 1)
138 #define RSPQ_CQBRANCH(rsp) ((be32_to_cpu(rsp->flags) >> 21) & 1)
139 #define RSPQ_CREDIT_THRESH(rsp) ((be32_to_cpu(rsp->flags) >> 22) & 1)
140
141 struct respQ_msg_t {
142 __be32 flags; /* flit 0 */
143 __be32 cq_ptrid;
144 __be64 rsvd; /* flit 1 */
145 struct t3_cqe cqe; /* flits 2-3 */
146 };
147
148 enum t3_cq_opcode {
149 CQ_ARM_AN = 0x2,
150 CQ_ARM_SE = 0x6,
151 CQ_FORCE_AN = 0x3,
152 CQ_CREDIT_UPDATE = 0x7
153 };
154
155 int cxio_rdev_open(struct cxio_rdev *rdev);
156 void cxio_rdev_close(struct cxio_rdev *rdev);
157 int cxio_hal_cq_op(struct cxio_rdev *rdev, struct t3_cq *cq,
158 enum t3_cq_opcode op, u32 credit);
159 int cxio_create_cq(struct cxio_rdev *rdev, struct t3_cq *cq);
160 int cxio_destroy_cq(struct cxio_rdev *rdev, struct t3_cq *cq);
161 int cxio_resize_cq(struct cxio_rdev *rdev, struct t3_cq *cq);
162 void cxio_release_ucontext(struct cxio_rdev *rdev, struct cxio_ucontext *uctx);
163 void cxio_init_ucontext(struct cxio_rdev *rdev, struct cxio_ucontext *uctx);
164 int cxio_create_qp(struct cxio_rdev *rdev, u32 kernel_domain, struct t3_wq *wq,
165 struct cxio_ucontext *uctx);
166 int cxio_destroy_qp(struct cxio_rdev *rdev, struct t3_wq *wq,
167 struct cxio_ucontext *uctx);
168 int cxio_peek_cq(struct t3_wq *wr, struct t3_cq *cq, int opcode);
169 int cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl,
170 u32 pbl_addr, u32 pbl_size);
171 int cxio_register_phys_mem(struct cxio_rdev *rdev, u32 * stag, u32 pdid,
172 enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
173 u8 page_size, u32 pbl_size, u32 pbl_addr);
174 int cxio_reregister_phys_mem(struct cxio_rdev *rdev, u32 * stag, u32 pdid,
175 enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
176 u8 page_size, u32 pbl_size, u32 pbl_addr);
177 int cxio_dereg_mem(struct cxio_rdev *rdev, u32 stag, u32 pbl_size,
178 u32 pbl_addr);
179 int cxio_allocate_window(struct cxio_rdev *rdev, u32 * stag, u32 pdid);
180 int cxio_allocate_stag(struct cxio_rdev *rdev, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr);
181 int cxio_deallocate_window(struct cxio_rdev *rdev, u32 stag);
182 int cxio_rdma_init(struct cxio_rdev *rdev, struct t3_rdma_init_attr *attr);
183 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb);
184 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb);
185 u32 cxio_hal_get_pdid(struct cxio_hal_resource *rscp);
186 void cxio_hal_put_pdid(struct cxio_hal_resource *rscp, u32 pdid);
187 int __init cxio_hal_init(void);
188 void __exit cxio_hal_exit(void);
189 int cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count);
190 int cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count);
191 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count);
192 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count);
193 void cxio_flush_hw_cq(struct t3_cq *cq);
194 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
195 u8 *cqe_flushed, u64 *cookie, u32 *credit);
196 int iwch_cxgb3_ofld_send(struct t3cdev *tdev, struct sk_buff *skb);
197
198 #define MOD "iw_cxgb3: "
199 #define PDBG(fmt, args...) pr_debug(MOD fmt, ## args)
200
201 #ifdef DEBUG
202 void cxio_dump_tpt(struct cxio_rdev *rev, u32 stag);
203 void cxio_dump_pbl(struct cxio_rdev *rev, u32 pbl_addr, uint len, u8 shift);
204 void cxio_dump_wqe(union t3_wr *wqe);
205 void cxio_dump_wce(struct t3_cqe *wce);
206 void cxio_dump_rqt(struct cxio_rdev *rdev, u32 hwtid, int nents);
207 void cxio_dump_tcb(struct cxio_rdev *rdev, u32 hwtid);
208 #endif
209
210 #endif
211
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