1 /*
2 * linux/drivers/ide/ide-pmac.c
3 *
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
6 * for doing DMA.
7 *
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
25 #include <linux/config.h>
26 #include <linux/types.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/init.h>
30 #include <linux/delay.h>
31 #include <linux/ide.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <linux/pci.h>
35 #include <linux/adb.h>
36 #include <linux/pmu.h>
37 #include <linux/scatterlist.h>
38
39 #include <asm/prom.h>
40 #include <asm/io.h>
41 #include <asm/dbdma.h>
42 #include <asm/ide.h>
43 #include <asm/pci-bridge.h>
44 #include <asm/machdep.h>
45 #include <asm/pmac_feature.h>
46 #include <asm/sections.h>
47 #include <asm/irq.h>
48
49 #ifndef CONFIG_PPC64
50 #include <asm/mediabay.h>
51 #endif
52
53 #include "ide-timing.h"
54
55 #undef IDE_PMAC_DEBUG
56
57 #define DMA_WAIT_TIMEOUT 50
58
59 typedef struct pmac_ide_hwif {
60 unsigned long regbase;
61 int irq;
62 int kind;
63 int aapl_bus_id;
64 unsigned cable_80 : 1;
65 unsigned mediabay : 1;
66 unsigned broken_dma : 1;
67 unsigned broken_dma_warn : 1;
68 struct device_node* node;
69 struct macio_dev *mdev;
70 u32 timings[4];
71 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
72 /* Those fields are duplicating what is in hwif. We currently
73 * can't use the hwif ones because of some assumptions that are
74 * beeing done by the generic code about the kind of dma controller
75 * and format of the dma table. This will have to be fixed though.
76 */
77 volatile struct dbdma_regs __iomem * dma_regs;
78 struct dbdma_cmd* dma_table_cpu;
79 #endif
80
81 } pmac_ide_hwif_t;
82
83 static pmac_ide_hwif_t pmac_ide[MAX_HWIFS] __pmacdata;
84 static int pmac_ide_count;
85
86 enum {
87 controller_ohare, /* OHare based */
88 controller_heathrow, /* Heathrow/Paddington */
89 controller_kl_ata3, /* KeyLargo ATA-3 */
90 controller_kl_ata4, /* KeyLargo ATA-4 */
91 controller_un_ata6, /* UniNorth2 ATA-6 */
92 controller_k2_ata6 /* K2 ATA-6 */
93 };
94
95 static const char* model_name[] = {
96 "OHare ATA", /* OHare based */
97 "Heathrow ATA", /* Heathrow/Paddington */
98 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
99 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
100 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
101 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
102 };
103
104 /*
105 * Extra registers, both 32-bit little-endian
106 */
107 #define IDE_TIMING_CONFIG 0x200
108 #define IDE_INTERRUPT 0x300
109
110 /* Kauai (U2) ATA has different register setup */
111 #define IDE_KAUAI_PIO_CONFIG 0x200
112 #define IDE_KAUAI_ULTRA_CONFIG 0x210
113 #define IDE_KAUAI_POLL_CONFIG 0x220
114
115 /*
116 * Timing configuration register definitions
117 */
118
119 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
120 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
121 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
122 #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
123 #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
124
125 /* 100Mhz cell, found in Uninorth 2. I don't have much infos about
126 * this one yet, it appears as a pci device (106b/0033) on uninorth
127 * internal PCI bus and it's clock is controlled like gem or fw. It
128 * appears to be an evolution of keylargo ATA4 with a timing register
129 * extended to 2 32bits registers and a similar DBDMA channel. Other
130 * registers seem to exist but I can't tell much about them.
131 *
132 * So far, I'm using pre-calculated tables for this extracted from
133 * the values used by the MacOS X driver.
134 *
135 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
136 * register controls the UDMA timings. At least, it seems bit 0
137 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
138 * cycle time in units of 10ns. Bits 8..15 are used by I don't
139 * know their meaning yet
140 */
141 #define TR_100_PIOREG_PIO_MASK 0xff000fff
142 #define TR_100_PIOREG_MDMA_MASK 0x00fff000
143 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
144 #define TR_100_UDMAREG_UDMA_EN 0x00000001
145
146
147 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
148 * 40 connector cable and to 4 on 80 connector one.
149 * Clock unit is 15ns (66Mhz)
150 *
151 * 3 Values can be programmed:
152 * - Write data setup, which appears to match the cycle time. They
153 * also call it DIOW setup.
154 * - Ready to pause time (from spec)
155 * - Address setup. That one is weird. I don't see where exactly
156 * it fits in UDMA cycles, I got it's name from an obscure piece
157 * of commented out code in Darwin. They leave it to 0, we do as
158 * well, despite a comment that would lead to think it has a
159 * min value of 45ns.
160 * Apple also add 60ns to the write data setup (or cycle time ?) on
161 * reads.
162 */
163 #define TR_66_UDMA_MASK 0xfff00000
164 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
165 #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
166 #define TR_66_UDMA_ADDRSETUP_SHIFT 29
167 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
168 #define TR_66_UDMA_RDY2PAUS_SHIFT 25
169 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
170 #define TR_66_UDMA_WRDATASETUP_SHIFT 21
171 #define TR_66_MDMA_MASK 0x000ffc00
172 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
173 #define TR_66_MDMA_RECOVERY_SHIFT 15
174 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
175 #define TR_66_MDMA_ACCESS_SHIFT 10
176 #define TR_66_PIO_MASK 0x000003ff
177 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
178 #define TR_66_PIO_RECOVERY_SHIFT 5
179 #define TR_66_PIO_ACCESS_MASK 0x0000001f
180 #define TR_66_PIO_ACCESS_SHIFT 0
181
182 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
183 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
184 *
185 * The access time and recovery time can be programmed. Some older
186 * Darwin code base limit OHare to 150ns cycle time. I decided to do
187 * the same here fore safety against broken old hardware ;)
188 * The HalfTick bit, when set, adds half a clock (15ns) to the access
189 * time and removes one from recovery. It's not supported on KeyLargo
190 * implementation afaik. The E bit appears to be set for PIO mode 0 and
191 * is used to reach long timings used in this mode.
192 */
193 #define TR_33_MDMA_MASK 0x003ff800
194 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
195 #define TR_33_MDMA_RECOVERY_SHIFT 16
196 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
197 #define TR_33_MDMA_ACCESS_SHIFT 11
198 #define TR_33_MDMA_HALFTICK 0x00200000
199 #define TR_33_PIO_MASK 0x000007ff
200 #define TR_33_PIO_E 0x00000400
201 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
202 #define TR_33_PIO_RECOVERY_SHIFT 5
203 #define TR_33_PIO_ACCESS_MASK 0x0000001f
204 #define TR_33_PIO_ACCESS_SHIFT 0
205
206 /*
207 * Interrupt register definitions
208 */
209 #define IDE_INTR_DMA 0x80000000
210 #define IDE_INTR_DEVICE 0x40000000
211
212 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
213
214 /* Rounded Multiword DMA timings
215 *
216 * I gave up finding a generic formula for all controller
217 * types and instead, built tables based on timing values
218 * used by Apple in Darwin's implementation.
219 */
220 struct mdma_timings_t {
221 int accessTime;
222 int recoveryTime;
223 int cycleTime;
224 };
225
226 struct mdma_timings_t mdma_timings_33[] __pmacdata =
227 {
228 { 240, 240, 480 },
229 { 180, 180, 360 },
230 { 135, 135, 270 },
231 { 120, 120, 240 },
232 { 105, 105, 210 },
233 { 90, 90, 180 },
234 { 75, 75, 150 },
235 { 75, 45, 120 },
236 { 0, 0, 0 }
237 };
238
239 struct mdma_timings_t mdma_timings_33k[] __pmacdata =
240 {
241 { 240, 240, 480 },
242 { 180, 180, 360 },
243 { 150, 150, 300 },
244 { 120, 120, 240 },
245 { 90, 120, 210 },
246 { 90, 90, 180 },
247 { 90, 60, 150 },
248 { 90, 30, 120 },
249 { 0, 0, 0 }
250 };
251
252 struct mdma_timings_t mdma_timings_66[] __pmacdata =
253 {
254 { 240, 240, 480 },
255 { 180, 180, 360 },
256 { 135, 135, 270 },
257 { 120, 120, 240 },
258 { 105, 105, 210 },
259 { 90, 90, 180 },
260 { 90, 75, 165 },
261 { 75, 45, 120 },
262 { 0, 0, 0 }
263 };
264
265 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
266 struct {
267 int addrSetup; /* ??? */
268 int rdy2pause;
269 int wrDataSetup;
270 } kl66_udma_timings[] __pmacdata =
271 {
272 { 0, 180, 120 }, /* Mode 0 */
273 { 0, 150, 90 }, /* 1 */
274 { 0, 120, 60 }, /* 2 */
275 { 0, 90, 45 }, /* 3 */
276 { 0, 90, 30 } /* 4 */
277 };
278
279 /* UniNorth 2 ATA/100 timings */
280 struct kauai_timing {
281 int cycle_time;
282 u32 timing_reg;
283 };
284
285 static struct kauai_timing kauai_pio_timings[] __pmacdata =
286 {
287 { 930 , 0x08000fff },
288 { 600 , 0x08000a92 },
289 { 383 , 0x0800060f },
290 { 360 , 0x08000492 },
291 { 330 , 0x0800048f },
292 { 300 , 0x080003cf },
293 { 270 , 0x080003cc },
294 { 240 , 0x0800038b },
295 { 239 , 0x0800030c },
296 { 180 , 0x05000249 },
297 { 120 , 0x04000148 }
298 };
299
300 static struct kauai_timing kauai_mdma_timings[] __pmacdata =
301 {
302 { 1260 , 0x00fff000 },
303 { 480 , 0x00618000 },
304 { 360 , 0x00492000 },
305 { 270 , 0x0038e000 },
306 { 240 , 0x0030c000 },
307 { 210 , 0x002cb000 },
308 { 180 , 0x00249000 },
309 { 150 , 0x00209000 },
310 { 120 , 0x00148000 },
311 { 0 , 0 },
312 };
313
314 static struct kauai_timing kauai_udma_timings[] __pmacdata =
315 {
316 { 120 , 0x000070c0 },
317 { 90 , 0x00005d80 },
318 { 60 , 0x00004a60 },
319 { 45 , 0x00003a50 },
320 { 30 , 0x00002a30 },
321 { 20 , 0x00002921 },
322 { 0 , 0 },
323 };
324
325 static inline u32
326 kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
327 {
328 int i;
329
330 for (i=0; table[i].cycle_time; i++)
331 if (cycle_time > table[i+1].cycle_time)
332 return table[i].timing_reg;
333 return 0;
334 }
335
336 /* allow up to 256 DBDMA commands per xfer */
337 #define MAX_DCMDS 256
338
339 /*
340 * Wait 1s for disk to answer on IDE bus after a hard reset
341 * of the device (via GPIO/FCR).
342 *
343 * Some devices seem to "pollute" the bus even after dropping
344 * the BSY bit (typically some combo drives slave on the UDMA
345 * bus) after a hard reset. Since we hard reset all drives on
346 * KeyLargo ATA66, we have to keep that delay around. I may end
347 * up not hard resetting anymore on these and keep the delay only
348 * for older interfaces instead (we have to reset when coming
349 * from MacOS...) --BenH.
350 */
351 #define IDE_WAKEUP_DELAY (1*HZ)
352
353 static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
354 static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
355 static int pmac_ide_tune_chipset(ide_drive_t *drive, u8 speed);
356 static void pmac_ide_tuneproc(ide_drive_t *drive, u8 pio);
357 static void pmac_ide_selectproc(ide_drive_t *drive);
358 static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
359
360 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
361
362 /*
363 * Below is the code for blinking the laptop LED along with hard
364 * disk activity.
365 */
366
367 #ifdef CONFIG_BLK_DEV_IDE_PMAC_BLINK
368
369 /* Set to 50ms minimum led-on time (also used to limit frequency
370 * of requests sent to the PMU
371 */
372 #define PMU_HD_BLINK_TIME (HZ/50)
373
374 static struct adb_request pmu_blink_on, pmu_blink_off;
375 static spinlock_t pmu_blink_lock;
376 static unsigned long pmu_blink_stoptime;
377 static int pmu_blink_ledstate;
378 static struct timer_list pmu_blink_timer;
379 static int pmu_ide_blink_enabled;
380
381
382 static void
383 pmu_hd_blink_timeout(unsigned long data)
384 {
385 unsigned long flags;
386
387 spin_lock_irqsave(&pmu_blink_lock, flags);
388
389 /* We may have been triggered again in a racy way, check
390 * that we really want to switch it off
391 */
392 if (time_after(pmu_blink_stoptime, jiffies))
393 goto done;
394
395 /* Previous req. not complete, try 100ms more */
396 if (pmu_blink_off.complete == 0)
397 mod_timer(&pmu_blink_timer, jiffies + PMU_HD_BLINK_TIME);
398 else if (pmu_blink_ledstate) {
399 pmu_request(&pmu_blink_off, NULL, 4, 0xee, 4, 0, 0);
400 pmu_blink_ledstate = 0;
401 }
402 done:
403 spin_unlock_irqrestore(&pmu_blink_lock, flags);
404 }
405
406 static void
407 pmu_hd_kick_blink(void *data, int rw)
408 {
409 unsigned long flags;
410
411 pmu_blink_stoptime = jiffies + PMU_HD_BLINK_TIME;
412 wmb();
413 mod_timer(&pmu_blink_timer, pmu_blink_stoptime);
414 /* Fast path when LED is already ON */
415 if (pmu_blink_ledstate == 1)
416 return;
417 spin_lock_irqsave(&pmu_blink_lock, flags);
418 if (pmu_blink_on.complete && !pmu_blink_ledstate) {
419 pmu_request(&pmu_blink_on, NULL, 4, 0xee, 4, 0, 1);
420 pmu_blink_ledstate = 1;
421 }
422 spin_unlock_irqrestore(&pmu_blink_lock, flags);
423 }
424
425 static int
426 pmu_hd_blink_init(void)
427 {
428 struct device_node *dt;
429 const char *model;
430
431 /* Currently, I only enable this feature on KeyLargo based laptops,
432 * older laptops may support it (at least heathrow/paddington) but
433 * I don't feel like loading those venerable old machines with so
434 * much additional interrupt & PMU activity...
435 */
436 if (pmu_get_model() != PMU_KEYLARGO_BASED)
437 return 0;
438
439 dt = find_devices("device-tree");
440 if (dt == NULL)
441 return 0;
442 model = (const char *)get_property(dt, "model", NULL);
443 if (model == NULL)
444 return 0;
445 if (strncmp(model, "PowerBook", strlen("PowerBook")) != 0 &&
446 strncmp(model, "iBook", strlen("iBook")) != 0)
447 return 0;
448
449 pmu_blink_on.complete = 1;
450 pmu_blink_off.complete = 1;
451 spin_lock_init(&pmu_blink_lock);
452 init_timer(&pmu_blink_timer);
453 pmu_blink_timer.function = pmu_hd_blink_timeout;
454
455 return 1;
456 }
457
458 #endif /* CONFIG_BLK_DEV_IDE_PMAC_BLINK */
459
460 /*
461 * N.B. this can't be an initfunc, because the media-bay task can
462 * call ide_[un]register at any time.
463 */
464 void __pmac
465 pmac_ide_init_hwif_ports(hw_regs_t *hw,
466 unsigned long data_port, unsigned long ctrl_port,
467 int *irq)
468 {
469 int i, ix;
470
471 if (data_port == 0)
472 return;
473
474 for (ix = 0; ix < MAX_HWIFS; ++ix)
475 if (data_port == pmac_ide[ix].regbase)
476 break;
477
478 if (ix >= MAX_HWIFS) {
479 /* Probably a PCI interface... */
480 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
481 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
482 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
483 return;
484 }
485
486 for (i = 0; i < 8; ++i)
487 hw->io_ports[i] = data_port + i * 0x10;
488 hw->io_ports[8] = data_port + 0x160;
489
490 if (irq != NULL)
491 *irq = pmac_ide[ix].irq;
492 }
493
494 #define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
495
496 /*
497 * Apply the timings of the proper unit (master/slave) to the shared
498 * timing register when selecting that unit. This version is for
499 * ASICs with a single timing register
500 */
501 static void __pmac
502 pmac_ide_selectproc(ide_drive_t *drive)
503 {
504 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
505
506 if (pmif == NULL)
507 return;
508
509 if (drive->select.b.unit & 0x01)
510 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
511 else
512 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
513 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
514 }
515
516 /*
517 * Apply the timings of the proper unit (master/slave) to the shared
518 * timing register when selecting that unit. This version is for
519 * ASICs with a dual timing register (Kauai)
520 */
521 static void __pmac
522 pmac_ide_kauai_selectproc(ide_drive_t *drive)
523 {
524 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
525
526 if (pmif == NULL)
527 return;
528
529 if (drive->select.b.unit & 0x01) {
530 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
531 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
532 } else {
533 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
534 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
535 }
536 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
537 }
538
539 /*
540 * Force an update of controller timing values for a given drive
541 */
542 static void __pmac
543 pmac_ide_do_update_timings(ide_drive_t *drive)
544 {
545 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
546
547 if (pmif == NULL)
548 return;
549
550 if (pmif->kind == controller_un_ata6 || pmif->kind == controller_k2_ata6)
551 pmac_ide_kauai_selectproc(drive);
552 else
553 pmac_ide_selectproc(drive);
554 }
555
556 static void
557 pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
558 {
559 u32 tmp;
560
561 writeb(value, (void __iomem *) port);
562 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
563 }
564
565 /*
566 * Send the SET_FEATURE IDE command to the drive and update drive->id with
567 * the new state. We currently don't use the generic routine as it used to
568 * cause various trouble, especially with older mediabays.
569 * This code is sometimes triggering a spurrious interrupt though, I need
570 * to sort that out sooner or later and see if I can finally get the
571 * common version to work properly in all cases
572 */
573 static int __pmac
574 pmac_ide_do_setfeature(ide_drive_t *drive, u8 command)
575 {
576 ide_hwif_t *hwif = HWIF(drive);
577 int result = 1;
578
579 disable_irq_nosync(hwif->irq);
580 udelay(1);
581 SELECT_DRIVE(drive);
582 SELECT_MASK(drive, 0);
583 udelay(1);
584 /* Get rid of pending error state */
585 (void) hwif->INB(IDE_STATUS_REG);
586 /* Timeout bumped for some powerbooks */
587 if (wait_for_ready(drive, 2000)) {
588 /* Timeout bumped for some powerbooks */
589 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
590 "before SET_FEATURE!\n", drive->name);
591 goto out;
592 }
593 udelay(10);
594 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
595 hwif->OUTB(command, IDE_NSECTOR_REG);
596 hwif->OUTB(SETFEATURES_XFER, IDE_FEATURE_REG);
597 hwif->OUTBSYNC(drive, WIN_SETFEATURES, IDE_COMMAND_REG);
598 udelay(1);
599 /* Timeout bumped for some powerbooks */
600 result = wait_for_ready(drive, 2000);
601 hwif->OUTB(drive->ctl, IDE_CONTROL_REG);
602 if (result)
603 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
604 "after SET_FEATURE !\n", drive->name);
605 out:
606 SELECT_MASK(drive, 0);
607 if (result == 0) {
608 drive->id->dma_ultra &= ~0xFF00;
609 drive->id->dma_mword &= ~0x0F00;
610 drive->id->dma_1word &= ~0x0F00;
611 switch(command) {
612 case XFER_UDMA_7:
613 drive->id->dma_ultra |= 0x8080; break;
614 case XFER_UDMA_6:
615 drive->id->dma_ultra |= 0x4040; break;
616 case XFER_UDMA_5:
617 drive->id->dma_ultra |= 0x2020; break;
618 case XFER_UDMA_4:
619 drive->id->dma_ultra |= 0x1010; break;
620 case XFER_UDMA_3:
621 drive->id->dma_ultra |= 0x0808; break;
622 case XFER_UDMA_2:
623 drive->id->dma_ultra |= 0x0404; break;
624 case XFER_UDMA_1:
625 drive->id->dma_ultra |= 0x0202; break;
626 case XFER_UDMA_0:
627 drive->id->dma_ultra |= 0x0101; break;
628 case XFER_MW_DMA_2:
629 drive->id->dma_mword |= 0x0404; break;
630 case XFER_MW_DMA_1:
631 drive->id->dma_mword |= 0x0202; break;
632 case XFER_MW_DMA_0:
633 drive->id->dma_mword |= 0x0101; break;
634 case XFER_SW_DMA_2:
635 drive->id->dma_1word |= 0x0404; break;
636 case XFER_SW_DMA_1:
637 drive->id->dma_1word |= 0x0202; break;
638 case XFER_SW_DMA_0:
639 drive->id->dma_1word |= 0x0101; break;
640 default: break;
641 }
642 }
643 enable_irq(hwif->irq);
644 return result;
645 }
646
647 /*
648 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
649 */
650 static void __pmac
651 pmac_ide_tuneproc(ide_drive_t *drive, u8 pio)
652 {
653 ide_pio_data_t d;
654 u32 *timings;
655 unsigned accessTicks, recTicks;
656 unsigned accessTime, recTime;
657 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
658
659 if (pmif == NULL)
660 return;
661
662 /* which drive is it ? */
663 timings = &pmif->timings[drive->select.b.unit & 0x01];
664
665 pio = ide_get_best_pio_mode(drive, pio, 4, &d);
666
667 switch (pmif->kind) {
668 case controller_un_ata6:
669 case controller_k2_ata6: {
670 /* 100Mhz cell */
671 u32 tr = kauai_lookup_timing(kauai_pio_timings, d.cycle_time);
672 if (tr == 0)
673 return;
674 *timings = ((*timings) & ~TR_100_PIOREG_PIO_MASK) | tr;
675 break;
676 }
677 case controller_kl_ata4:
678 /* 66Mhz cell */
679 recTime = d.cycle_time - ide_pio_timings[pio].active_time
680 - ide_pio_timings[pio].setup_time;
681 recTime = max(recTime, 150U);
682 accessTime = ide_pio_timings[pio].active_time;
683 accessTime = max(accessTime, 150U);
684 accessTicks = SYSCLK_TICKS_66(accessTime);
685 accessTicks = min(accessTicks, 0x1fU);
686 recTicks = SYSCLK_TICKS_66(recTime);
687 recTicks = min(recTicks, 0x1fU);
688 *timings = ((*timings) & ~TR_66_PIO_MASK) |
689 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
690 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
691 break;
692 default: {
693 /* 33Mhz cell */
694 int ebit = 0;
695 recTime = d.cycle_time - ide_pio_timings[pio].active_time
696 - ide_pio_timings[pio].setup_time;
697 recTime = max(recTime, 150U);
698 accessTime = ide_pio_timings[pio].active_time;
699 accessTime = max(accessTime, 150U);
700 accessTicks = SYSCLK_TICKS(accessTime);
701 accessTicks = min(accessTicks, 0x1fU);
702 accessTicks = max(accessTicks, 4U);
703 recTicks = SYSCLK_TICKS(recTime);
704 recTicks = min(recTicks, 0x1fU);
705 recTicks = max(recTicks, 5U) - 4;
706 if (recTicks > 9) {
707 recTicks--; /* guess, but it's only for PIO0, so... */
708 ebit = 1;
709 }
710 *timings = ((*timings) & ~TR_33_PIO_MASK) |
711 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
712 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
713 if (ebit)
714 *timings |= TR_33_PIO_E;
715 break;
716 }
717 }
718
719 #ifdef IDE_PMAC_DEBUG
720 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
721 drive->name, pio, *timings);
722 #endif
723
724 if (drive->select.all == HWIF(drive)->INB(IDE_SELECT_REG))
725 pmac_ide_do_update_timings(drive);
726 }
727
728 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
729
730 /*
731 * Calculate KeyLargo ATA/66 UDMA timings
732 */
733 static int __pmac
734 set_timings_udma_ata4(u32 *timings, u8 speed)
735 {
736 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
737
738 if (speed > XFER_UDMA_4)
739 return 1;
740
741 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
742 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
743 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
744
745 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
746 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
747 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
748 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
749 TR_66_UDMA_EN;
750 #ifdef IDE_PMAC_DEBUG
751 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
752 speed & 0xf, *timings);
753 #endif
754
755 return 0;
756 }
757
758 /*
759 * Calculate Kauai ATA/100 UDMA timings
760 */
761 static int __pmac
762 set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
763 {
764 struct ide_timing *t = ide_timing_find_mode(speed);
765 u32 tr;
766
767 if (speed > XFER_UDMA_5 || t == NULL)
768 return 1;
769 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
770 if (tr == 0)
771 return 1;
772 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
773 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
774
775 return 0;
776 }
777
778 /*
779 * Calculate MDMA timings for all cells
780 */
781 static int __pmac
782 set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
783 u8 speed, int drive_cycle_time)
784 {
785 int cycleTime, accessTime = 0, recTime = 0;
786 unsigned accessTicks, recTicks;
787 struct mdma_timings_t* tm = NULL;
788 int i;
789
790 /* Get default cycle time for mode */
791 switch(speed & 0xf) {
792 case 0: cycleTime = 480; break;
793 case 1: cycleTime = 150; break;
794 case 2: cycleTime = 120; break;
795 default:
796 return 1;
797 }
798 /* Adjust for drive */
799 if (drive_cycle_time && drive_cycle_time > cycleTime)
800 cycleTime = drive_cycle_time;
801 /* OHare limits according to some old Apple sources */
802 if ((intf_type == controller_ohare) && (cycleTime < 150))
803 cycleTime = 150;
804 /* Get the proper timing array for this controller */
805 switch(intf_type) {
806 case controller_un_ata6:
807 case controller_k2_ata6:
808 break;
809 case controller_kl_ata4:
810 tm = mdma_timings_66;
811 break;
812 case controller_kl_ata3:
813 tm = mdma_timings_33k;
814 break;
815 default:
816 tm = mdma_timings_33;
817 break;
818 }
819 if (tm != NULL) {
820 /* Lookup matching access & recovery times */
821 i = -1;
822 for (;;) {
823 if (tm[i+1].cycleTime < cycleTime)
824 break;
825 i++;
826 }
827 if (i < 0)
828 return 1;
829 cycleTime = tm[i].cycleTime;
830 accessTime = tm[i].accessTime;
831 recTime = tm[i].recoveryTime;
832
833 #ifdef IDE_PMAC_DEBUG
834 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
835 drive->name, cycleTime, accessTime, recTime);
836 #endif
837 }
838 switch(intf_type) {
839 case controller_un_ata6:
840 case controller_k2_ata6: {
841 /* 100Mhz cell */
842 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
843 if (tr == 0)
844 return 1;
845 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
846 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
847 }
848 break;
849 case controller_kl_ata4:
850 /* 66Mhz cell */
851 accessTicks = SYSCLK_TICKS_66(accessTime);
852 accessTicks = min(accessTicks, 0x1fU);
853 accessTicks = max(accessTicks, 0x1U);
854 recTicks = SYSCLK_TICKS_66(recTime);
855 recTicks = min(recTicks, 0x1fU);
856 recTicks = max(recTicks, 0x3U);
857 /* Clear out mdma bits and disable udma */
858 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
859 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
860 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
861 break;
862 case controller_kl_ata3:
863 /* 33Mhz cell on KeyLargo */
864 accessTicks = SYSCLK_TICKS(accessTime);
865 accessTicks = max(accessTicks, 1U);
866 accessTicks = min(accessTicks, 0x1fU);
867 accessTime = accessTicks * IDE_SYSCLK_NS;
868 recTicks = SYSCLK_TICKS(recTime);
869 recTicks = max(recTicks, 1U);
870 recTicks = min(recTicks, 0x1fU);
871 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
872 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
873 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
874 break;
875 default: {
876 /* 33Mhz cell on others */
877 int halfTick = 0;
878 int origAccessTime = accessTime;
879 int origRecTime = recTime;
880
881 accessTicks = SYSCLK_TICKS(accessTime);
882 accessTicks = max(accessTicks, 1U);
883 accessTicks = min(accessTicks, 0x1fU);
884 accessTime = accessTicks * IDE_SYSCLK_NS;
885 recTicks = SYSCLK_TICKS(recTime);
886 recTicks = max(recTicks, 2U) - 1;
887 recTicks = min(recTicks, 0x1fU);
888 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
889 if ((accessTicks > 1) &&
890 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
891 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
892 halfTick = 1;
893 accessTicks--;
894 }
895 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
896 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
897 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
898 if (halfTick)
899 *timings |= TR_33_MDMA_HALFTICK;
900 }
901 }
902 #ifdef IDE_PMAC_DEBUG
903 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
904 drive->name, speed & 0xf, *timings);
905 #endif
906 return 0;
907 }
908 #endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
909
910 /*
911 * Speedproc. This function is called by the core to set any of the standard
912 * timing (PIO, MDMA or UDMA) to both the drive and the controller.
913 * You may notice we don't use this function on normal "dma check" operation,
914 * our dedicated function is more precise as it uses the drive provided
915 * cycle time value. We should probably fix this one to deal with that too...
916 */
917 static int __pmac
918 pmac_ide_tune_chipset (ide_drive_t *drive, byte speed)
919 {
920 int unit = (drive->select.b.unit & 0x01);
921 int ret = 0;
922 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
923 u32 *timings, *timings2;
924
925 if (pmif == NULL)
926 return 1;
927
928 timings = &pmif->timings[unit];
929 timings2 = &pmif->timings[unit+2];
930
931 switch(speed) {
932 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
933 case XFER_UDMA_5:
934 if (pmif->kind != controller_un_ata6 &&
935 pmif->kind != controller_k2_ata6)
936 return 1;
937 case XFER_UDMA_4:
938 case XFER_UDMA_3:
939 if (HWIF(drive)->udma_four == 0)
940 return 1;
941 case XFER_UDMA_2:
942 case XFER_UDMA_1:
943 case XFER_UDMA_0:
944 if (pmif->kind == controller_kl_ata4)
945 ret = set_timings_udma_ata4(timings, speed);
946 else if (pmif->kind == controller_un_ata6
947 || pmif->kind == controller_k2_ata6)
948 ret = set_timings_udma_ata6(timings, timings2, speed);
949 else
950 ret = 1;
951 break;
952 case XFER_MW_DMA_2:
953 case XFER_MW_DMA_1:
954 case XFER_MW_DMA_0:
955 ret = set_timings_mdma(drive, pmif->kind, timings, timings2, speed, 0);
956 break;
957 case XFER_SW_DMA_2:
958 case XFER_SW_DMA_1:
959 case XFER_SW_DMA_0:
960 return 1;
961 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
962 case XFER_PIO_4:
963 case XFER_PIO_3:
964 case XFER_PIO_2:
965 case XFER_PIO_1:
966 case XFER_PIO_0:
967 pmac_ide_tuneproc(drive, speed & 0x07);
968 break;
969 default:
970 ret = 1;
971 }
972 if (ret)
973 return ret;
974
975 ret = pmac_ide_do_setfeature(drive, speed);
976 if (ret)
977 return ret;
978
979 pmac_ide_do_update_timings(drive);
980 drive->current_speed = speed;
981
982 return 0;
983 }
984
985 /*
986 * Blast some well known "safe" values to the timing registers at init or
987 * wakeup from sleep time, before we do real calculation
988 */
989 static void __pmac
990 sanitize_timings(pmac_ide_hwif_t *pmif)
991 {
992 unsigned int value, value2 = 0;
993
994 switch(pmif->kind) {
995 case controller_un_ata6:
996 case controller_k2_ata6:
997 value = 0x08618a92;
998 value2 = 0x00002921;
999 break;
1000 case controller_kl_ata4:
1001 value = 0x0008438c;
1002 break;
1003 case controller_kl_ata3:
1004 value = 0x00084526;
1005 break;
1006 case controller_heathrow:
1007 case controller_ohare:
1008 default:
1009 value = 0x00074526;
1010 break;
1011 }
1012 pmif->timings[0] = pmif->timings[1] = value;
1013 pmif->timings[2] = pmif->timings[3] = value2;
1014 }
1015
1016 unsigned long __pmac
1017 pmac_ide_get_base(int index)
1018 {
1019 return pmac_ide[index].regbase;
1020 }
1021
1022 int __pmac
1023 pmac_ide_check_base(unsigned long base)
1024 {
1025 int ix;
1026
1027 for (ix = 0; ix < MAX_HWIFS; ++ix)
1028 if (base == pmac_ide[ix].regbase)
1029 return ix;
1030 return -1;
1031 }
1032
1033 int __pmac
1034 pmac_ide_get_irq(unsigned long base)
1035 {
1036 int ix;
1037
1038 for (ix = 0; ix < MAX_HWIFS; ++ix)
1039 if (base == pmac_ide[ix].regbase)
1040 return pmac_ide[ix].irq;
1041 return 0;
1042 }
1043
1044 static int ide_majors[] __pmacdata = { 3, 22, 33, 34, 56, 57 };
1045
1046 dev_t __init
1047 pmac_find_ide_boot(char *bootdevice, int n)
1048 {
1049 int i;
1050
1051 /*
1052 * Look through the list of IDE interfaces for this one.
1053 */
1054 for (i = 0; i < pmac_ide_count; ++i) {
1055 char *name;
1056 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
1057 continue;
1058 name = pmac_ide[i].node->full_name;
1059 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
1060 /* XXX should cope with the 2nd drive as well... */
1061 return MKDEV(ide_majors[i], 0);
1062 }
1063 }
1064
1065 return 0;
1066 }
1067
1068 /* Suspend call back, should be called after the child devices
1069 * have actually been suspended
1070 */
1071 static int
1072 pmac_ide_do_suspend(ide_hwif_t *hwif)
1073 {
1074 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1075
1076 /* We clear the timings */
1077 pmif->timings[0] = 0;
1078 pmif->timings[1] = 0;
1079
1080 #ifdef CONFIG_BLK_DEV_IDE_PMAC_BLINK
1081 /* Note: This code will be called for every hwif, thus we'll
1082 * try several time to stop the LED blinker timer, but that
1083 * should be harmless
1084 */
1085 if (pmu_ide_blink_enabled) {
1086 unsigned long flags;
1087
1088 /* Make sure we don't hit the PMU blink */
1089 spin_lock_irqsave(&pmu_blink_lock, flags);
1090 if (pmu_blink_ledstate)
1091 del_timer(&pmu_blink_timer);
1092 pmu_blink_ledstate = 0;
1093 spin_unlock_irqrestore(&pmu_blink_lock, flags);
1094 }
1095 #endif /* CONFIG_BLK_DEV_IDE_PMAC_BLINK */
1096
1097 /* The media bay will handle itself just fine */
1098 if (pmif->mediabay)
1099 return 0;
1100
1101 /* Disable the bus */
1102 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 0);
1103
1104 return 0;
1105 }
1106
1107 /* Resume call back, should be called before the child devices
1108 * are resumed
1109 */
1110 static int
1111 pmac_ide_do_resume(ide_hwif_t *hwif)
1112 {
1113 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1114
1115 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1116 if (!pmif->mediabay) {
1117 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
1118 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
1119 msleep(10);
1120 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
1121 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1122 }
1123
1124 /* Sanitize drive timings */
1125 sanitize_timings(pmif);
1126
1127 return 0;
1128 }
1129
1130 /*
1131 * Setup, register & probe an IDE channel driven by this driver, this is
1132 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1133 * that ends up beeing free of any device is not kept around by this driver
1134 * (it is kept in 2.4). This introduce an interface numbering change on some
1135 * rare machines unfortunately, but it's better this way.
1136 */
1137 static int
1138 pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1139 {
1140 struct device_node *np = pmif->node;
1141 int *bidp, i;
1142
1143 pmif->cable_80 = 0;
1144 pmif->broken_dma = pmif->broken_dma_warn = 0;
1145 if (device_is_compatible(np, "kauai-ata"))
1146 pmif->kind = controller_un_ata6;
1147 else if (device_is_compatible(np, "K2-UATA"))
1148 pmif->kind = controller_k2_ata6;
1149 else if (device_is_compatible(np, "keylargo-ata")) {
1150 if (strcmp(np->name, "ata-4") == 0)
1151 pmif->kind = controller_kl_ata4;
1152 else
1153 pmif->kind = controller_kl_ata3;
1154 } else if (device_is_compatible(np, "heathrow-ata"))
1155 pmif->kind = controller_heathrow;
1156 else {
1157 pmif->kind = controller_ohare;
1158 pmif->broken_dma = 1;
1159 }
1160
1161 bidp = (int *)get_property(np, "AAPL,bus-id", NULL);
1162 pmif->aapl_bus_id = bidp ? *bidp : 0;
1163
1164 /* Get cable type from device-tree */
1165 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1166 || pmif->kind == controller_k2_ata6) {
1167 char* cable = get_property(np, "cable-type", NULL);
1168 if (cable && !strncmp(cable, "80-", 3))
1169 pmif->cable_80 = 1;
1170 }
1171
1172 pmif->mediabay = 0;
1173
1174 /* Make sure we have sane timings */
1175 sanitize_timings(pmif);
1176
1177 #ifndef CONFIG_PPC64
1178 /* XXX FIXME: Media bay stuff need re-organizing */
1179 if (np->parent && np->parent->name
1180 && strcasecmp(np->parent->name, "media-bay") == 0) {
1181 #ifdef CONFIG_PMAC_PBOOK
1182 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index);
1183 #endif /* CONFIG_PMAC_PBOOK */
1184 pmif->mediabay = 1;
1185 if (!bidp)
1186 pmif->aapl_bus_id = 1;
1187 } else if (pmif->kind == controller_ohare) {
1188 /* The code below is having trouble on some ohare machines
1189 * (timing related ?). Until I can put my hand on one of these
1190 * units, I keep the old way
1191 */
1192 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1193 } else
1194 #endif
1195 {
1196 /* This is necessary to enable IDE when net-booting */
1197 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1198 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1199 msleep(10);
1200 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1201 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1202 }
1203
1204 /* Setup MMIO ops */
1205 default_hwif_mmiops(hwif);
1206 hwif->OUTBSYNC = pmac_outbsync;
1207
1208 /* Tell common code _not_ to mess with resources */
1209 hwif->mmio = 2;
1210 hwif->hwif_data = pmif;
1211 pmac_ide_init_hwif_ports(&hwif->hw, pmif->regbase, 0, &hwif->irq);
1212 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
1213 hwif->chipset = ide_pmac;
1214 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || pmif->mediabay;
1215 hwif->hold = pmif->mediabay;
1216 hwif->udma_four = pmif->cable_80;
1217 hwif->drives[0].unmask = 1;
1218 hwif->drives[1].unmask = 1;
1219 hwif->tuneproc = pmac_ide_tuneproc;
1220 if (pmif->kind == controller_un_ata6 || pmif->kind == controller_k2_ata6)
1221 hwif->selectproc = pmac_ide_kauai_selectproc;
1222 else
1223 hwif->selectproc = pmac_ide_selectproc;
1224 hwif->speedproc = pmac_ide_tune_chipset;
1225
1226 #ifdef CONFIG_BLK_DEV_IDE_PMAC_BLINK
1227 pmu_ide_blink_enabled = pmu_hd_blink_init();
1228
1229 if (pmu_ide_blink_enabled)
1230 hwif->led_act = pmu_hd_kick_blink;
1231 #endif
1232
1233 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1234 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1235 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1236
1237 #ifdef CONFIG_PMAC_PBOOK
1238 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1239 hwif->noprobe = 0;
1240 #endif /* CONFIG_PMAC_PBOOK */
1241
1242 hwif->sg_max_nents = MAX_DCMDS;
1243
1244 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1245 /* has a DBDMA controller channel */
1246 if (pmif->dma_regs)
1247 pmac_ide_setup_dma(pmif, hwif);
1248 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1249
1250 /* We probe the hwif now */
1251 probe_hwif_init(hwif);
1252
1253 /* The code IDE code will have set hwif->present if we have devices attached,
1254 * if we don't, the discard the interface except if we are on a media bay slot
1255 */
1256 if (!hwif->present && !pmif->mediabay) {
1257 printk(KERN_INFO "ide%d: Bus empty, interface released.\n",
1258 hwif->index);
1259 default_hwif_iops(hwif);
1260 for (i = IDE_DATA_OFFSET; i <= IDE_CONTROL_OFFSET; ++i)
1261 hwif->io_ports[i] = 0;
1262 hwif->chipset = ide_unknown;
1263 hwif->noprobe = 1;
1264 return -ENODEV;
1265 }
1266
1267 return 0;
1268 }
1269
1270 /*
1271 * Attach to a macio probed interface
1272 */
1273 static int __devinit
1274 pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_match *match)
1275 {
1276 void __iomem *base;
1277 unsigned long regbase;
1278 int irq;
1279 ide_hwif_t *hwif;
1280 pmac_ide_hwif_t *pmif;
1281 int i, rc;
1282
1283 i = 0;
1284 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1285 || pmac_ide[i].node != NULL))
1286 ++i;
1287 if (i >= MAX_HWIFS) {
1288 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1289 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1290 return -ENODEV;
1291 }
1292
1293 pmif = &pmac_ide[i];
1294 hwif = &ide_hwifs[i];
1295
1296 if (mdev->ofdev.node->n_addrs == 0) {
1297 printk(KERN_WARNING "ide%d: no address for %s\n",
1298 i, mdev->ofdev.node->full_name);
1299 return -ENXIO;
1300 }
1301
1302 /* Request memory resource for IO ports */
1303 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1304 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1305 return -EBUSY;
1306 }
1307
1308 /* XXX This is bogus. Should be fixed in the registry by checking
1309 * the kind of host interrupt controller, a bit like gatwick
1310 * fixes in irq.c. That works well enough for the single case
1311 * where that happens though...
1312 */
1313 if (macio_irq_count(mdev) == 0) {
1314 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1315 i, mdev->ofdev.node->full_name);
1316 irq = 13;
1317 } else
1318 irq = macio_irq(mdev, 0);
1319
1320 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1321 regbase = (unsigned long) base;
1322
1323 hwif->pci_dev = mdev->bus->pdev;
1324 hwif->gendev.parent = &mdev->ofdev.dev;
1325
1326 pmif->mdev = mdev;
1327 pmif->node = mdev->ofdev.node;
1328 pmif->regbase = regbase;
1329 pmif->irq = irq;
1330 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1331 if (macio_resource_count(mdev) >= 2) {
1332 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1333 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1334 else
1335 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1336 } else
1337 pmif->dma_regs = NULL;
1338 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1339 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1340
1341 rc = pmac_ide_setup_device(pmif, hwif);
1342 if (rc != 0) {
1343 /* The inteface is released to the common IDE layer */
1344 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1345 iounmap(base);
1346 if (pmif->dma_regs)
1347 iounmap(pmif->dma_regs);
1348 memset(pmif, 0, sizeof(*pmif));
1349 macio_release_resource(mdev, 0);
1350 if (pmif->dma_regs)
1351 macio_release_resource(mdev, 1);
1352 }
1353
1354 return rc;
1355 }
1356
1357 static int
1358 pmac_ide_macio_suspend(struct macio_dev *mdev, u32 state)
1359 {
1360 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1361 int rc = 0;
1362
1363 if (state != mdev->ofdev.dev.power.power_state && state >= 2) {
1364 rc = pmac_ide_do_suspend(hwif);
1365 if (rc == 0)
1366 mdev->ofdev.dev.power.power_state = state;
1367 }
1368
1369 return rc;
1370 }
1371
1372 static int
1373 pmac_ide_macio_resume(struct macio_dev *mdev)
1374 {
1375 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1376 int rc = 0;
1377
1378 if (mdev->ofdev.dev.power.power_state != 0) {
1379 rc = pmac_ide_do_resume(hwif);
1380 if (rc == 0)
1381 mdev->ofdev.dev.power.power_state = 0;
1382 }
1383
1384 return rc;
1385 }
1386
1387 /*
1388 * Attach to a PCI probed interface
1389 */
1390 static int __devinit
1391 pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1392 {
1393 ide_hwif_t *hwif;
1394 struct device_node *np;
1395 pmac_ide_hwif_t *pmif;
1396 void __iomem *base;
1397 unsigned long rbase, rlen;
1398 int i, rc;
1399
1400 np = pci_device_to_OF_node(pdev);
1401 if (np == NULL) {
1402 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1403 return -ENODEV;
1404 }
1405 i = 0;
1406 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1407 || pmac_ide[i].node != NULL))
1408 ++i;
1409 if (i >= MAX_HWIFS) {
1410 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1411 printk(KERN_ERR " %s\n", np->full_name);
1412 return -ENODEV;
1413 }
1414
1415 pmif = &pmac_ide[i];
1416 hwif = &ide_hwifs[i];
1417
1418 if (pci_enable_device(pdev)) {
1419 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1420 i, np->full_name);
1421 return -ENXIO;
1422 }
1423 pci_set_master(pdev);
1424
1425 if (pci_request_regions(pdev, "Kauai ATA")) {
1426 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1427 i, np->full_name);
1428 return -ENXIO;
1429 }
1430
1431 hwif->pci_dev = pdev;
1432 hwif->gendev.parent = &pdev->dev;
1433 pmif->mdev = NULL;
1434 pmif->node = np;
1435
1436 rbase = pci_resource_start(pdev, 0);
1437 rlen = pci_resource_len(pdev, 0);
1438
1439 base = ioremap(rbase, rlen);
1440 pmif->regbase = (unsigned long) base + 0x2000;
1441 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1442 pmif->dma_regs = base + 0x1000;
1443 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1444
1445 /* We use the OF node irq mapping */
1446 if (np->n_intrs == 0)
1447 pmif->irq = pdev->irq;
1448 else
1449 pmif->irq = np->intrs[0].line;
1450
1451 pci_set_drvdata(pdev, hwif);
1452
1453 rc = pmac_ide_setup_device(pmif, hwif);
1454 if (rc != 0) {
1455 /* The inteface is released to the common IDE layer */
1456 pci_set_drvdata(pdev, NULL);
1457 iounmap(base);
1458 memset(pmif, 0, sizeof(*pmif));
1459 pci_release_regions(pdev);
1460 }
1461
1462 return rc;
1463 }
1464
1465 static int
1466 pmac_ide_pci_suspend(struct pci_dev *pdev, u32 state)
1467 {
1468 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1469 int rc = 0;
1470
1471 if (state != pdev->dev.power.power_state && state >= 2) {
1472 rc = pmac_ide_do_suspend(hwif);
1473 if (rc == 0)
1474 pdev->dev.power.power_state = state;
1475 }
1476
1477 return rc;
1478 }
1479
1480 static int
1481 pmac_ide_pci_resume(struct pci_dev *pdev)
1482 {
1483 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1484 int rc = 0;
1485
1486 if (pdev->dev.power.power_state != 0) {
1487 rc = pmac_ide_do_resume(hwif);
1488 if (rc == 0)
1489 pdev->dev.power.power_state = 0;
1490 }
1491
1492 return rc;
1493 }
1494
1495 static struct of_match pmac_ide_macio_match[] =
1496 {
1497 {
1498 .name = "IDE",
1499 .type = OF_ANY_MATCH,
1500 .compatible = OF_ANY_MATCH
1501 },
1502 {
1503 .name = "ATA",
1504 .type = OF_ANY_MATCH,
1505 .compatible = OF_ANY_MATCH
1506 },
1507 {
1508 .name = OF_ANY_MATCH,
1509 .type = "ide",
1510 .compatible = OF_ANY_MATCH
1511 },
1512 {
1513 .name = OF_ANY_MATCH,
1514 .type = "ata",
1515 .compatible = OF_ANY_MATCH
1516 },
1517 {},
1518 };
1519
1520 static struct macio_driver pmac_ide_macio_driver =
1521 {
1522 .name = "ide-pmac",
1523 .match_table = pmac_ide_macio_match,
1524 .probe = pmac_ide_macio_attach,
1525 .suspend = pmac_ide_macio_suspend,
1526 .resume = pmac_ide_macio_resume,
1527 };
1528
1529 static struct pci_device_id pmac_ide_pci_match[] = {
1530 { PCI_VENDOR_ID_APPLE, PCI_DEVIEC_ID_APPLE_UNI_N_ATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1531 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1532 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1533 };
1534
1535 static struct pci_driver pmac_ide_pci_driver = {
1536 .name = "ide-pmac",
1537 .id_table = pmac_ide_pci_match,
1538 .probe = pmac_ide_pci_attach,
1539 .suspend = pmac_ide_pci_suspend,
1540 .resume = pmac_ide_pci_resume,
1541 };
1542
1543 void __init
1544 pmac_ide_probe(void)
1545 {
1546 if (_machine != _MACH_Pmac)
1547 return;
1548
1549 #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1550 pci_register_driver(&pmac_ide_pci_driver);
1551 macio_register_driver(&pmac_ide_macio_driver);
1552 #else
1553 macio_register_driver(&pmac_ide_macio_driver);
1554 pci_register_driver(&pmac_ide_pci_driver);
1555 #endif
1556 }
1557
1558 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1559
1560 /*
1561 * pmac_ide_build_dmatable builds the DBDMA command list
1562 * for a transfer and sets the DBDMA channel to point to it.
1563 */
1564 static int __pmac
1565 pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1566 {
1567 struct dbdma_cmd *table;
1568 int i, count = 0;
1569 ide_hwif_t *hwif = HWIF(drive);
1570 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1571 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1572 struct scatterlist *sg;
1573 int wr = (rq_data_dir(rq) == WRITE);
1574
1575 /* DMA table is already aligned */
1576 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1577
1578 /* Make sure DMA controller is stopped (necessary ?) */
1579 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1580 while (readl(&dma->status) & RUN)
1581 udelay(1);
1582
1583 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1584
1585 if (!i)
1586 return 0;
1587
1588 /* Build DBDMA commands list */
1589 sg = hwif->sg_table;
1590 while (i && sg_dma_len(sg)) {
1591 u32 cur_addr;
1592 u32 cur_len;
1593
1594 cur_addr = sg_dma_address(sg);
1595 cur_len = sg_dma_len(sg);
1596
1597 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1598 if (pmif->broken_dma_warn == 0) {
1599 printk(KERN_WARNING "%s: DMA on non aligned address,"
1600 "switching to PIO on Ohare chipset\n", drive->name);
1601 pmif->broken_dma_warn = 1;
1602 }
1603 goto use_pio_instead;
1604 }
1605 while (cur_len) {
1606 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1607
1608 if (count++ >= MAX_DCMDS) {
1609 printk(KERN_WARNING "%s: DMA table too small\n",
1610 drive->name);
1611 goto use_pio_instead;
1612 }
1613 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1614 st_le16(&table->req_count, tc);
1615 st_le32(&table->phy_addr, cur_addr);
1616 table->cmd_dep = 0;
1617 table->xfer_status = 0;
1618 table->res_count = 0;
1619 cur_addr += tc;
1620 cur_len -= tc;
1621 ++table;
1622 }
1623 sg++;
1624 i--;
1625 }
1626
1627 /* convert the last command to an input/output last command */
1628 if (count) {
1629 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1630 /* add the stop command to the end of the list */
1631 memset(table, 0, sizeof(struct dbdma_cmd));
1632 st_le16(&table->command, DBDMA_STOP);
1633 mb();
1634 writel(hwif->dmatable_dma, &dma->cmdptr);
1635 return 1;
1636 }
1637
1638 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1639 use_pio_instead:
1640 pci_unmap_sg(hwif->pci_dev,
1641 hwif->sg_table,
1642 hwif->sg_nents,
1643 hwif->sg_dma_direction);
1644 return 0; /* revert to PIO for this request */
1645 }
1646
1647 /* Teardown mappings after DMA has completed. */
1648 static void __pmac
1649 pmac_ide_destroy_dmatable (ide_drive_t *drive)
1650 {
1651 ide_hwif_t *hwif = drive->hwif;
1652 struct pci_dev *dev = HWIF(drive)->pci_dev;
1653 struct scatterlist *sg = hwif->sg_table;
1654 int nents = hwif->sg_nents;
1655
1656 if (nents) {
1657 pci_unmap_sg(dev, sg, nents, hwif->sg_dma_direction);
1658 hwif->sg_nents = 0;
1659 }
1660 }
1661
1662 /*
1663 * Pick up best MDMA timing for the drive and apply it
1664 */
1665 static int __pmac
1666 pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode)
1667 {
1668 ide_hwif_t *hwif = HWIF(drive);
1669 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1670 int drive_cycle_time;
1671 struct hd_driveid *id = drive->id;
1672 u32 *timings, *timings2;
1673 u32 timing_local[2];
1674 int ret;
1675
1676 /* which drive is it ? */
1677 timings = &pmif->timings[drive->select.b.unit & 0x01];
1678 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1679
1680 /* Check if drive provide explicit cycle time */
1681 if ((id->field_valid & 2) && (id->eide_dma_time))
1682 drive_cycle_time = id->eide_dma_time;
1683 else
1684 drive_cycle_time = 0;
1685
1686 /* Copy timings to local image */
1687 timing_local[0] = *timings;
1688 timing_local[1] = *timings2;
1689
1690 /* Calculate controller timings */
1691 ret = set_timings_mdma( drive, pmif->kind,
1692 &timing_local[0],
1693 &timing_local[1],
1694 mode,
1695 drive_cycle_time);
1696 if (ret)
1697 return 0;
1698
1699 /* Set feature on drive */
1700 printk(KERN_INFO "%s: Enabling MultiWord DMA %d\n", drive->name, mode & 0xf);
1701 ret = pmac_ide_do_setfeature(drive, mode);
1702 if (ret) {
1703 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1704 return 0;
1705 }
1706
1707 /* Apply timings to controller */
1708 *timings = timing_local[0];
1709 *timings2 = timing_local[1];
1710
1711 /* Set speed info in drive */
1712 drive->current_speed = mode;
1713 if (!drive->init_speed)
1714 drive->init_speed = mode;
1715
1716 return 1;
1717 }
1718
1719 /*
1720 * Pick up best UDMA timing for the drive and apply it
1721 */
1722 static int __pmac
1723 pmac_ide_udma_enable(ide_drive_t *drive, u16 mode)
1724 {
1725 ide_hwif_t *hwif = HWIF(drive);
1726 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1727 u32 *timings, *timings2;
1728 u32 timing_local[2];
1729 int ret;
1730
1731 /* which drive is it ? */
1732 timings = &pmif->timings[drive->select.b.unit & 0x01];
1733 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1734
1735 /* Copy timings to local image */
1736 timing_local[0] = *timings;
1737 timing_local[1] = *timings2;
1738
1739 /* Calculate timings for interface */
1740 if (pmif->kind == controller_un_ata6 || pmif->kind == controller_k2_ata6)
1741 ret = set_timings_udma_ata6( &timing_local[0],
1742 &timing_local[1],
1743 mode);
1744 else
1745 ret = set_timings_udma_ata4(&timing_local[0], mode);
1746 if (ret)
1747 return 0;
1748
1749 /* Set feature on drive */
1750 printk(KERN_INFO "%s: Enabling Ultra DMA %d\n", drive->name, mode & 0x0f);
1751 ret = pmac_ide_do_setfeature(drive, mode);
1752 if (ret) {
1753 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1754 return 0;
1755 }
1756
1757 /* Apply timings to controller */
1758 *timings = timing_local[0];
1759 *timings2 = timing_local[1];
1760
1761 /* Set speed info in drive */
1762 drive->current_speed = mode;
1763 if (!drive->init_speed)
1764 drive->init_speed = mode;
1765
1766 return 1;
1767 }
1768
1769 /*
1770 * Check what is the best DMA timing setting for the drive and
1771 * call appropriate functions to apply it.
1772 */
1773 static int __pmac
1774 pmac_ide_dma_check(ide_drive_t *drive)
1775 {
1776 struct hd_driveid *id = drive->id;
1777 ide_hwif_t *hwif = HWIF(drive);
1778 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1779 int enable = 1;
1780 int map;
1781 drive->using_dma = 0;
1782
1783 if (drive->media == ide_floppy)
1784 enable = 0;
1785 if (((id->capability & 1) == 0) && !__ide_dma_good_drive(drive))
1786 enable = 0;
1787 if (__ide_dma_bad_drive(drive))
1788 enable = 0;
1789
1790 if (enable) {
1791 short mode;
1792
1793 map = XFER_MWDMA;
1794 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1795 || pmif->kind == controller_k2_ata6) {
1796 map |= XFER_UDMA;
1797 if (pmif->cable_80) {
1798 map |= XFER_UDMA_66;
1799 if (pmif->kind == controller_un_ata6 ||
1800 pmif->kind == controller_k2_ata6)
1801 map |= XFER_UDMA_100;
1802 }
1803 }
1804 mode = ide_find_best_mode(drive, map);
1805 if (mode & XFER_UDMA)
1806 drive->using_dma = pmac_ide_udma_enable(drive, mode);
1807 else if (mode & XFER_MWDMA)
1808 drive->using_dma = pmac_ide_mdma_enable(drive, mode);
1809 hwif->OUTB(0, IDE_CONTROL_REG);
1810 /* Apply settings to controller */
1811 pmac_ide_do_update_timings(drive);
1812 }
1813 return 0;
1814 }
1815
1816 /*
1817 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1818 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1819 */
1820 static int __pmac
1821 pmac_ide_dma_setup(ide_drive_t *drive)
1822 {
1823 ide_hwif_t *hwif = HWIF(drive);
1824 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1825 struct request *rq = HWGROUP(drive)->rq;
1826 u8 unit = (drive->select.b.unit & 0x01);
1827 u8 ata4;
1828
1829 if (pmif == NULL)
1830 return 1;
1831 ata4 = (pmif->kind == controller_kl_ata4);
1832
1833 if (!pmac_ide_build_dmatable(drive, rq)) {
1834 ide_map_sg(drive, rq);
1835 return 1;
1836 }
1837
1838 /* Apple adds 60ns to wrDataSetup on reads */
1839 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1840 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1841 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1842 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1843 }
1844
1845 drive->waiting_for_dma = 1;
1846
1847 return 0;
1848 }
1849
1850 static void __pmac
1851 pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1852 {
1853 /* issue cmd to drive */
1854 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1855 }
1856
1857 /*
1858 * Kick the DMA controller into life after the DMA command has been issued
1859 * to the drive.
1860 */
1861 static void __pmac
1862 pmac_ide_dma_start(ide_drive_t *drive)
1863 {
1864 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1865 volatile struct dbdma_regs __iomem *dma;
1866
1867 dma = pmif->dma_regs;
1868
1869 writel((RUN << 16) | RUN, &dma->control);
1870 /* Make sure it gets to the controller right now */
1871 (void)readl(&dma->control);
1872 }
1873
1874 /*
1875 * After a DMA transfer, make sure the controller is stopped
1876 */
1877 static int __pmac
1878 pmac_ide_dma_end (ide_drive_t *drive)
1879 {
1880 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1881 volatile struct dbdma_regs __iomem *dma;
1882 u32 dstat;
1883
1884 if (pmif == NULL)
1885 return 0;
1886 dma = pmif->dma_regs;
1887
1888 drive->waiting_for_dma = 0;
1889 dstat = readl(&dma->status);
1890 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1891 pmac_ide_destroy_dmatable(drive);
1892 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1893 * in theory, but with ATAPI decices doing buffer underruns, that would
1894 * cause us to disable DMA, which isn't what we want
1895 */
1896 return (dstat & (RUN|DEAD)) != RUN;
1897 }
1898
1899 /*
1900 * Check out that the interrupt we got was for us. We can't always know this
1901 * for sure with those Apple interfaces (well, we could on the recent ones but
1902 * that's not implemented yet), on the other hand, we don't have shared interrupts
1903 * so it's not really a problem
1904 */
1905 static int __pmac
1906 pmac_ide_dma_test_irq (ide_drive_t *drive)
1907 {
1908 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1909 volatile struct dbdma_regs __iomem *dma;
1910 unsigned long status, timeout;
1911
1912 if (pmif == NULL)
1913 return 0;
1914 dma = pmif->dma_regs;
1915
1916 /* We have to things to deal with here:
1917 *
1918 * - The dbdma won't stop if the command was started
1919 * but completed with an error without transferring all
1920 * datas. This happens when bad blocks are met during
1921 * a multi-block transfer.
1922 *
1923 * - The dbdma fifo hasn't yet finished flushing to
1924 * to system memory when the disk interrupt occurs.
1925 *
1926 */
1927
1928 /* If ACTIVE is cleared, the STOP command have passed and
1929 * transfer is complete.
1930 */
1931 status = readl(&dma->status);
1932 if (!(status & ACTIVE))
1933 return 1;
1934 if (!drive->waiting_for_dma)
1935 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1936 called while not waiting\n", HWIF(drive)->index);
1937
1938 /* If dbdma didn't execute the STOP command yet, the
1939 * active bit is still set. We consider that we aren't
1940 * sharing interrupts (which is hopefully the case with
1941 * those controllers) and so we just try to flush the
1942 * channel for pending data in the fifo
1943 */
1944 udelay(1);
1945 writel((FLUSH << 16) | FLUSH, &dma->control);
1946 timeout = 0;
1947 for (;;) {
1948 udelay(1);
1949 status = readl(&dma->status);
1950 if ((status & FLUSH) == 0)
1951 break;
1952 if (++timeout > 100) {
1953 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1954 timeout flushing channel\n", HWIF(drive)->index);
1955 break;
1956 }
1957 }
1958 return 1;
1959 }
1960
1961 static int __pmac
1962 pmac_ide_dma_host_off (ide_drive_t *drive)
1963 {
1964 return 0;
1965 }
1966
1967 static int __pmac
1968 pmac_ide_dma_host_on (ide_drive_t *drive)
1969 {
1970 return 0;
1971 }
1972
1973 static int __pmac
1974 pmac_ide_dma_lostirq (ide_drive_t *drive)
1975 {
1976 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1977 volatile struct dbdma_regs __iomem *dma;
1978 unsigned long status;
1979
1980 if (pmif == NULL)
1981 return 0;
1982 dma = pmif->dma_regs;
1983
1984 status = readl(&dma->status);
1985 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
1986 return 0;
1987 }
1988
1989 /*
1990 * Allocate the data structures needed for using DMA with an interface
1991 * and fill the proper list of functions pointers
1992 */
1993 static void __init
1994 pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1995 {
1996 /* We won't need pci_dev if we switch to generic consistent
1997 * DMA routines ...
1998 */
1999 if (hwif->pci_dev == NULL)
2000 return;
2001 /*
2002 * Allocate space for the DBDMA commands.
2003 * The +2 is +1 for the stop command and +1 to allow for
2004 * aligning the start address to a multiple of 16 bytes.
2005 */
2006 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
2007 hwif->pci_dev,
2008 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
2009 &hwif->dmatable_dma);
2010 if (pmif->dma_table_cpu == NULL) {
2011 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
2012 hwif->name);
2013 return;
2014 }
2015
2016 hwif->ide_dma_off_quietly = &__ide_dma_off_quietly;
2017 hwif->ide_dma_on = &__ide_dma_on;
2018 hwif->ide_dma_check = &pmac_ide_dma_check;
2019 hwif->dma_setup = &pmac_ide_dma_setup;
2020 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
2021 hwif->dma_start = &pmac_ide_dma_start;
2022 hwif->ide_dma_end = &pmac_ide_dma_end;
2023 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
2024 hwif->ide_dma_host_off = &pmac_ide_dma_host_off;
2025 hwif->ide_dma_host_on = &pmac_ide_dma_host_on;
2026 hwif->ide_dma_timeout = &__ide_dma_timeout;
2027 hwif->ide_dma_lostirq = &pmac_ide_dma_lostirq;
2028
2029 hwif->atapi_dma = 1;
2030 switch(pmif->kind) {
2031 case controller_un_ata6:
2032 case controller_k2_ata6:
2033 hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07;
2034 hwif->mwdma_mask = 0x07;
2035 hwif->swdma_mask = 0x00;
2036 break;
2037 case controller_kl_ata4:
2038 hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07;
2039 hwif->mwdma_mask = 0x07;
2040 hwif->swdma_mask = 0x00;
2041 break;
2042 default:
2043 hwif->ultra_mask = 0x00;
2044 hwif->mwdma_mask = 0x07;
2045 hwif->swdma_mask = 0x00;
2046 break;
2047 }
2048 }
2049
2050 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
2051
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