1 /*
2 * Copyright (c) 2003 Silicon Graphics, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it would be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
11 *
12 * You should have received a copy of the GNU General Public
13 * License along with this program; if not, write the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
15 *
16 * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy,
17 * Mountain View, CA 94043, or:
18 *
19 * http://www.sgi.com
20 *
21 * For further information regarding this notice, see:
22 *
23 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
24 */
25
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/hdreg.h>
31 #include <linux/init.h>
32 #include <linux/kernel.h>
33 #include <linux/timer.h>
34 #include <linux/mm.h>
35 #include <linux/ioport.h>
36 #include <linux/blkdev.h>
37 #include <asm/io.h>
38
39 #include <linux/ide.h>
40
41 /* IOC4 Specific Definitions */
42 #define IOC4_CMD_OFFSET 0x100
43 #define IOC4_CTRL_OFFSET 0x120
44 #define IOC4_DMA_OFFSET 0x140
45 #define IOC4_INTR_OFFSET 0x0
46
47 #define IOC4_TIMING 0x00
48 #define IOC4_DMA_PTR_L 0x01
49 #define IOC4_DMA_PTR_H 0x02
50 #define IOC4_DMA_ADDR_L 0x03
51 #define IOC4_DMA_ADDR_H 0x04
52 #define IOC4_BC_DEV 0x05
53 #define IOC4_BC_MEM 0x06
54 #define IOC4_DMA_CTRL 0x07
55 #define IOC4_DMA_END_ADDR 0x08
56
57 /* Bits in the IOC4 Control/Status Register */
58 #define IOC4_S_DMA_START 0x01
59 #define IOC4_S_DMA_STOP 0x02
60 #define IOC4_S_DMA_DIR 0x04
61 #define IOC4_S_DMA_ACTIVE 0x08
62 #define IOC4_S_DMA_ERROR 0x10
63 #define IOC4_ATA_MEMERR 0x02
64
65 /* Read/Write Directions */
66 #define IOC4_DMA_WRITE 0x04
67 #define IOC4_DMA_READ 0x00
68
69 /* Interrupt Register Offsets */
70 #define IOC4_INTR_REG 0x03
71 #define IOC4_INTR_SET 0x05
72 #define IOC4_INTR_CLEAR 0x07
73
74 #define IOC4_IDE_CACHELINE_SIZE 128
75 #define IOC4_CMD_CTL_BLK_SIZE 0x20
76 #define IOC4_SUPPORTED_FIRMWARE_REV 46
77
78 typedef struct {
79 u32 timing_reg0;
80 u32 timing_reg1;
81 u32 low_mem_ptr;
82 u32 high_mem_ptr;
83 u32 low_mem_addr;
84 u32 high_mem_addr;
85 u32 dev_byte_count;
86 u32 mem_byte_count;
87 u32 status;
88 } ioc4_dma_regs_t;
89
90 /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
91 /* IOC4 has only 1 IDE channel */
92 #define IOC4_PRD_BYTES 16
93 #define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES))
94
95
96 static void
97 sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
98 unsigned long ctrl_port, unsigned long irq_port)
99 {
100 unsigned long reg = data_port;
101 int i;
102
103 /* Registers are word (32 bit) aligned */
104 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
105 hw->io_ports[i] = reg + i * 4;
106
107 if (ctrl_port)
108 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
109
110 if (irq_port)
111 hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
112 }
113
114 static void
115 sgiioc4_maskproc(ide_drive_t * drive, int mask)
116 {
117 ide_hwif_t *hwif = HWIF(drive);
118 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
119 IDE_CONTROL_REG);
120 }
121
122
123 static int
124 sgiioc4_checkirq(ide_hwif_t * hwif)
125 {
126 u8 intr_reg =
127 hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4);
128
129 if (intr_reg & 0x03)
130 return 1;
131
132 return 0;
133 }
134
135
136 static int
137 sgiioc4_clearirq(ide_drive_t * drive)
138 {
139 u32 intr_reg;
140 ide_hwif_t *hwif = HWIF(drive);
141 unsigned long other_ir =
142 hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2);
143
144 /* Code to check for PCI error conditions */
145 intr_reg = hwif->INL(other_ir);
146 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
147 /*
148 * Using hwif->INB to read the IDE_STATUS_REG has a side effect
149 * of clearing the interrupt. The first read should clear it
150 * if it is set. The second read should return a "clear" status
151 * if it got cleared. If not, then spin for a bit trying to
152 * clear it.
153 */
154 u8 stat = hwif->INB(IDE_STATUS_REG);
155 int count = 0;
156 stat = hwif->INB(IDE_STATUS_REG);
157 while ((stat & 0x80) && (count++ < 100)) {
158 udelay(1);
159 stat = hwif->INB(IDE_STATUS_REG);
160 }
161
162 if (intr_reg & 0x02) {
163 /* Error when transferring DMA data on PCI bus */
164 u32 pci_err_addr_low, pci_err_addr_high,
165 pci_stat_cmd_reg;
166
167 pci_err_addr_low =
168 hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET]);
169 pci_err_addr_high =
170 hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET] + 4);
171 pci_read_config_dword(hwif->pci_dev, PCI_COMMAND,
172 &pci_stat_cmd_reg);
173 printk(KERN_ERR
174 "%s(%s) : PCI Bus Error when doing DMA:"
175 " status-cmd reg is 0x%x\n",
176 __FUNCTION__, drive->name, pci_stat_cmd_reg);
177 printk(KERN_ERR
178 "%s(%s) : PCI Error Address is 0x%x%x\n",
179 __FUNCTION__, drive->name,
180 pci_err_addr_high, pci_err_addr_low);
181 /* Clear the PCI Error indicator */
182 pci_write_config_dword(hwif->pci_dev, PCI_COMMAND,
183 0x00000146);
184 }
185
186 /* Clear the Interrupt, Error bits on the IOC4 */
187 hwif->OUTL(0x03, other_ir);
188
189 intr_reg = hwif->INL(other_ir);
190 }
191
192 return intr_reg & 3;
193 }
194
195 static void sgiioc4_ide_dma_start(ide_drive_t * drive)
196 {
197 ide_hwif_t *hwif = HWIF(drive);
198 unsigned int reg = hwif->INL(hwif->dma_base + IOC4_DMA_CTRL * 4);
199 unsigned int temp_reg = reg | IOC4_S_DMA_START;
200
201 hwif->OUTL(temp_reg, hwif->dma_base + IOC4_DMA_CTRL * 4);
202 }
203
204 static u32
205 sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
206 {
207 u32 ioc4_dma;
208 int count;
209
210 count = 0;
211 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
212 while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
213 udelay(1);
214 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
215 }
216 return ioc4_dma;
217 }
218
219 /* Stops the IOC4 DMA Engine */
220 static int
221 sgiioc4_ide_dma_end(ide_drive_t * drive)
222 {
223 u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
224 ide_hwif_t *hwif = HWIF(drive);
225 u64 dma_base = hwif->dma_base;
226 int dma_stat = 0;
227 unsigned long *ending_dma = (unsigned long *) hwif->dma_base2;
228
229 hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4);
230
231 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
232
233 if (ioc4_dma & IOC4_S_DMA_STOP) {
234 printk(KERN_ERR
235 "%s(%s): IOC4 DMA STOP bit is still 1 :"
236 "ioc4_dma_reg 0x%x\n",
237 __FUNCTION__, drive->name, ioc4_dma);
238 dma_stat = 1;
239 }
240
241 /*
242 * The IOC4 will DMA 1's to the ending dma area to indicate that
243 * previous data DMA is complete. This is necessary because of relaxed
244 * ordering between register reads and DMA writes on the Altix.
245 */
246 while ((cnt++ < 200) && (!valid)) {
247 for (num = 0; num < 16; num++) {
248 if (ending_dma[num]) {
249 valid = 1;
250 break;
251 }
252 }
253 udelay(1);
254 }
255 if (!valid) {
256 printk(KERN_ERR "%s(%s) : DMA incomplete\n", __FUNCTION__,
257 drive->name);
258 dma_stat = 1;
259 }
260
261 bc_dev = hwif->INL(dma_base + IOC4_BC_DEV * 4);
262 bc_mem = hwif->INL(dma_base + IOC4_BC_MEM * 4);
263
264 if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
265 if (bc_dev > bc_mem + 8) {
266 printk(KERN_ERR
267 "%s(%s): WARNING!! byte_count_dev %d "
268 "!= byte_count_mem %d\n",
269 __FUNCTION__, drive->name, bc_dev, bc_mem);
270 }
271 }
272
273 drive->waiting_for_dma = 0;
274 ide_destroy_dmatable(drive);
275
276 return dma_stat;
277 }
278
279 static int
280 sgiioc4_ide_dma_check(ide_drive_t * drive)
281 {
282 if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0) {
283 printk(KERN_INFO
284 "Couldnot set %s in Multimode-2 DMA mode | "
285 "Drive %s using PIO instead\n",
286 drive->name, drive->name);
287 drive->using_dma = 0;
288 } else
289 drive->using_dma = 1;
290
291 return 0;
292 }
293
294 static int
295 sgiioc4_ide_dma_on(ide_drive_t * drive)
296 {
297 drive->using_dma = 1;
298
299 return HWIF(drive)->ide_dma_host_on(drive);
300 }
301
302 static int
303 sgiioc4_ide_dma_off_quietly(ide_drive_t * drive)
304 {
305 drive->using_dma = 0;
306
307 return HWIF(drive)->ide_dma_host_off(drive);
308 }
309
310 /* returns 1 if dma irq issued, 0 otherwise */
311 static int
312 sgiioc4_ide_dma_test_irq(ide_drive_t * drive)
313 {
314 return sgiioc4_checkirq(HWIF(drive));
315 }
316
317 static int
318 sgiioc4_ide_dma_host_on(ide_drive_t * drive)
319 {
320 if (drive->using_dma)
321 return 0;
322
323 return 1;
324 }
325
326 static int
327 sgiioc4_ide_dma_host_off(ide_drive_t * drive)
328 {
329 sgiioc4_clearirq(drive);
330
331 return 0;
332 }
333
334 static int
335 sgiioc4_ide_dma_lostirq(ide_drive_t * drive)
336 {
337 HWIF(drive)->resetproc(drive);
338
339 return __ide_dma_lostirq(drive);
340 }
341
342 static void
343 sgiioc4_resetproc(ide_drive_t * drive)
344 {
345 sgiioc4_ide_dma_end(drive);
346 sgiioc4_clearirq(drive);
347 }
348
349 static u8
350 sgiioc4_INB(unsigned long port)
351 {
352 u8 reg = (u8) inb(port);
353
354 if ((port & 0xFFF) == 0x11C) { /* Status register of IOC4 */
355 if (reg & 0x51) { /* Not busy...check for interrupt */
356 unsigned long other_ir = port - 0x110;
357 unsigned int intr_reg = (u32) inl(other_ir);
358
359 /* Clear the Interrupt, Error bits on the IOC4 */
360 if (intr_reg & 0x03) {
361 outl(0x03, other_ir);
362 intr_reg = (u32) inl(other_ir);
363 }
364 }
365 }
366
367 return reg;
368 }
369
370 /* Creates a dma map for the scatter-gather list entries */
371 static void __devinit
372 ide_dma_sgiioc4(ide_hwif_t * hwif, unsigned long dma_base)
373 {
374 int num_ports = sizeof (ioc4_dma_regs_t);
375
376 printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name,
377 dma_base, dma_base + num_ports - 1);
378
379 if (!request_region(dma_base, num_ports, hwif->name)) {
380 printk(KERN_ERR
381 "%s(%s) -- ERROR, Addresses 0x%p to 0x%p "
382 "ALREADY in use\n",
383 __FUNCTION__, hwif->name, (void *) dma_base,
384 (void *) dma_base + num_ports - 1);
385 goto dma_alloc_failure;
386 }
387
388 hwif->dma_base = dma_base;
389 hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev,
390 IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
391 &hwif->dmatable_dma);
392
393 if (!hwif->dmatable_cpu)
394 goto dma_alloc_failure;
395
396 hwif->sg_max_nents = IOC4_PRD_ENTRIES;
397
398 hwif->dma_base2 = (unsigned long)
399 pci_alloc_consistent(hwif->pci_dev,
400 IOC4_IDE_CACHELINE_SIZE,
401 (dma_addr_t *) &(hwif->dma_status));
402
403 if (!hwif->dma_base2)
404 goto dma_base2alloc_failure;
405
406 return;
407
408 dma_base2alloc_failure:
409 pci_free_consistent(hwif->pci_dev,
410 IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
411 hwif->dmatable_cpu, hwif->dmatable_dma);
412 printk(KERN_INFO
413 "%s() -- Error! Unable to allocate DMA Maps for drive %s\n",
414 __FUNCTION__, hwif->name);
415 printk(KERN_INFO
416 "Changing from DMA to PIO mode for Drive %s\n", hwif->name);
417
418 dma_alloc_failure:
419 /* Disable DMA because we couldnot allocate any DMA maps */
420 hwif->autodma = 0;
421 hwif->atapi_dma = 0;
422 }
423
424 /* Initializes the IOC4 DMA Engine */
425 static void
426 sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
427 {
428 u32 ioc4_dma;
429 ide_hwif_t *hwif = HWIF(drive);
430 u64 dma_base = hwif->dma_base;
431 u32 dma_addr, ending_dma_addr;
432
433 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
434
435 if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
436 printk(KERN_WARNING
437 "%s(%s):Warning!! DMA from previous transfer was still active\n",
438 __FUNCTION__, drive->name);
439 hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4);
440 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
441
442 if (ioc4_dma & IOC4_S_DMA_STOP)
443 printk(KERN_ERR
444 "%s(%s) : IOC4 Dma STOP bit is still 1\n",
445 __FUNCTION__, drive->name);
446 }
447
448 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
449 if (ioc4_dma & IOC4_S_DMA_ERROR) {
450 printk(KERN_WARNING
451 "%s(%s) : Warning!! - DMA Error during Previous"
452 " transfer | status 0x%x\n",
453 __FUNCTION__, drive->name, ioc4_dma);
454 hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4);
455 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
456
457 if (ioc4_dma & IOC4_S_DMA_STOP)
458 printk(KERN_ERR
459 "%s(%s) : IOC4 DMA STOP bit is still 1\n",
460 __FUNCTION__, drive->name);
461 }
462
463 /* Address of the Scatter Gather List */
464 dma_addr = cpu_to_le32(hwif->dmatable_dma);
465 hwif->OUTL(dma_addr, dma_base + IOC4_DMA_PTR_L * 4);
466
467 /* Address of the Ending DMA */
468 memset((unsigned int *) hwif->dma_base2, 0, IOC4_IDE_CACHELINE_SIZE);
469 ending_dma_addr = cpu_to_le32(hwif->dma_status);
470 hwif->OUTL(ending_dma_addr, dma_base + IOC4_DMA_END_ADDR * 4);
471
472 hwif->OUTL(dma_direction, dma_base + IOC4_DMA_CTRL * 4);
473 drive->waiting_for_dma = 1;
474 }
475
476 /* IOC4 Scatter Gather list Format */
477 /* 128 Bit entries to support 64 bit addresses in the future */
478 /* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */
479 /* --------------------------------------------------------------------- */
480 /* | Upper 32 bits - Zero | Lower 32 bits- address | */
481 /* --------------------------------------------------------------------- */
482 /* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */
483 /* --------------------------------------------------------------------- */
484 /* Creates the scatter gather list, DMA Table */
485 static unsigned int
486 sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
487 {
488 ide_hwif_t *hwif = HWIF(drive);
489 unsigned int *table = hwif->dmatable_cpu;
490 unsigned int count = 0, i = 1;
491 struct scatterlist *sg;
492
493 hwif->sg_nents = i = ide_build_sglist(drive, rq);
494
495 if (!i)
496 return 0; /* sglist of length Zero */
497
498 sg = hwif->sg_table;
499 while (i && sg_dma_len(sg)) {
500 dma_addr_t cur_addr;
501 int cur_len;
502 cur_addr = sg_dma_address(sg);
503 cur_len = sg_dma_len(sg);
504
505 while (cur_len) {
506 if (count++ >= IOC4_PRD_ENTRIES) {
507 printk(KERN_WARNING
508 "%s: DMA table too small\n",
509 drive->name);
510 goto use_pio_instead;
511 } else {
512 u32 xcount, bcount =
513 0x10000 - (cur_addr & 0xffff);
514
515 if (bcount > cur_len)
516 bcount = cur_len;
517
518 /* put the addr, length in
519 * the IOC4 dma-table format */
520 *table = 0x0;
521 table++;
522 *table = cpu_to_be32(cur_addr);
523 table++;
524 *table = 0x0;
525 table++;
526
527 xcount = bcount & 0xffff;
528 *table = cpu_to_be32(xcount);
529 table++;
530
531 cur_addr += bcount;
532 cur_len -= bcount;
533 }
534 }
535
536 sg++;
537 i--;
538 }
539
540 if (count) {
541 table--;
542 *table |= cpu_to_be32(0x80000000);
543 return count;
544 }
545
546 use_pio_instead:
547 pci_unmap_sg(hwif->pci_dev, hwif->sg_table, hwif->sg_nents,
548 hwif->sg_dma_direction);
549
550 return 0; /* revert to PIO for this request */
551 }
552
553 static int sgiioc4_ide_dma_setup(ide_drive_t *drive)
554 {
555 struct request *rq = HWGROUP(drive)->rq;
556 unsigned int count = 0;
557 int ddir;
558
559 if (rq_data_dir(rq))
560 ddir = PCI_DMA_TODEVICE;
561 else
562 ddir = PCI_DMA_FROMDEVICE;
563
564 if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) {
565 /* try PIO instead of DMA */
566 ide_map_sg(drive, rq);
567 return 1;
568 }
569
570 if (rq_data_dir(rq))
571 /* Writes TO the IOC4 FROM Main Memory */
572 ddir = IOC4_DMA_READ;
573 else
574 /* Writes FROM the IOC4 TO Main Memory */
575 ddir = IOC4_DMA_WRITE;
576
577 sgiioc4_configure_for_dma(ddir, drive);
578
579 return 0;
580 }
581
582 static void __devinit
583 ide_init_sgiioc4(ide_hwif_t * hwif)
584 {
585 hwif->mmio = 2;
586 hwif->autodma = 1;
587 hwif->atapi_dma = 1;
588 hwif->ultra_mask = 0x0; /* Disable Ultra DMA */
589 hwif->mwdma_mask = 0x2; /* Multimode-2 DMA */
590 hwif->swdma_mask = 0x2;
591 hwif->tuneproc = NULL; /* Sets timing for PIO mode */
592 hwif->speedproc = NULL; /* Sets timing for DMA &/or PIO modes */
593 hwif->selectproc = NULL;/* Use the default routine to select drive */
594 hwif->reset_poll = NULL;/* No HBA specific reset_poll needed */
595 hwif->pre_reset = NULL; /* No HBA specific pre_set needed */
596 hwif->resetproc = &sgiioc4_resetproc;/* Reset DMA engine,
597 clear interrupts */
598 hwif->intrproc = NULL; /* Enable or Disable interrupt from drive */
599 hwif->maskproc = &sgiioc4_maskproc; /* Mask on/off NIEN register */
600 hwif->quirkproc = NULL;
601 hwif->busproc = NULL;
602
603 hwif->dma_setup = &sgiioc4_ide_dma_setup;
604 hwif->dma_start = &sgiioc4_ide_dma_start;
605 hwif->ide_dma_end = &sgiioc4_ide_dma_end;
606 hwif->ide_dma_check = &sgiioc4_ide_dma_check;
607 hwif->ide_dma_on = &sgiioc4_ide_dma_on;
608 hwif->ide_dma_off_quietly = &sgiioc4_ide_dma_off_quietly;
609 hwif->ide_dma_test_irq = &sgiioc4_ide_dma_test_irq;
610 hwif->ide_dma_host_on = &sgiioc4_ide_dma_host_on;
611 hwif->ide_dma_host_off = &sgiioc4_ide_dma_host_off;
612 hwif->ide_dma_lostirq = &sgiioc4_ide_dma_lostirq;
613 hwif->ide_dma_timeout = &__ide_dma_timeout;
614 hwif->INB = &sgiioc4_INB;
615 }
616
617 static int __devinit
618 sgiioc4_ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t * d)
619 {
620 unsigned long base, ctl, dma_base, irqport;
621 ide_hwif_t *hwif;
622 int h;
623
624 for (h = 0; h < MAX_HWIFS; ++h) {
625 hwif = &ide_hwifs[h];
626 /* Find an empty HWIF */
627 if (hwif->chipset == ide_unknown)
628 break;
629 }
630
631 /* Get the CmdBlk and CtrlBlk Base Registers */
632 base = pci_resource_start(dev, 0) + IOC4_CMD_OFFSET;
633 ctl = pci_resource_start(dev, 0) + IOC4_CTRL_OFFSET;
634 irqport = pci_resource_start(dev, 0) + IOC4_INTR_OFFSET;
635 dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
636
637 if (!request_region(base, IOC4_CMD_CTL_BLK_SIZE, hwif->name)) {
638 printk(KERN_ERR
639 "%s : %s -- ERROR, Port Addresses "
640 "0x%p to 0x%p ALREADY in use\n",
641 __FUNCTION__, hwif->name, (void *) base,
642 (void *) base + IOC4_CMD_CTL_BLK_SIZE);
643 return -ENOMEM;
644 }
645
646 if (hwif->io_ports[IDE_DATA_OFFSET] != base) {
647 /* Initialize the IO registers */
648 sgiioc4_init_hwif_ports(&hwif->hw, base, ctl, irqport);
649 memcpy(hwif->io_ports, hwif->hw.io_ports,
650 sizeof (hwif->io_ports));
651 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
652 }
653
654 hwif->irq = dev->irq;
655 hwif->chipset = ide_pci;
656 hwif->pci_dev = dev;
657 hwif->channel = 0; /* Single Channel chip */
658 hwif->cds = (struct ide_pci_device_s *) d;
659 hwif->gendev.parent = &dev->dev;/* setup proper ancestral information */
660
661 /* Initializing chipset IRQ Registers */
662 hwif->OUTL(0x03, irqport + IOC4_INTR_SET * 4);
663
664 ide_init_sgiioc4(hwif);
665
666 if (dma_base)
667 ide_dma_sgiioc4(hwif, dma_base);
668 else
669 printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n",
670 hwif->name, d->name);
671
672 if (probe_hwif_init(hwif))
673 return -EIO;
674
675 /* Create /proc/ide entries */
676 create_proc_ide_interfaces();
677
678 return 0;
679 }
680
681 static unsigned int __devinit
682 pci_init_sgiioc4(struct pci_dev *dev, ide_pci_device_t * d)
683 {
684 unsigned int class_rev;
685 int ret;
686
687 ret = pci_enable_device(dev);
688 if (ret < 0) {
689 printk(KERN_ERR
690 "Failed to enable device %s at slot %s\n",
691 d->name, dev->slot_name);
692 goto out;
693 }
694 pci_set_master(dev);
695
696 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
697 class_rev &= 0xff;
698 printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
699 d->name, dev->slot_name, class_rev);
700 if (class_rev < IOC4_SUPPORTED_FIRMWARE_REV) {
701 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
702 "firmware is obsolete - please upgrade to revision"
703 "46 or higher\n", d->name, dev->slot_name);
704 ret = -EAGAIN;
705 goto out;
706 }
707 ret = sgiioc4_ide_setup_pci_device(dev, d);
708 out:
709 return ret;
710 }
711
712 static ide_pci_device_t sgiioc4_chipsets[] __devinitdata = {
713 {
714 /* Channel 0 */
715 .name = "SGIIOC4",
716 .init_hwif = ide_init_sgiioc4,
717 .init_dma = ide_dma_sgiioc4,
718 .channels = 1,
719 .autodma = AUTODMA,
720 /* SGI IOC4 doesn't have enablebits. */
721 .bootable = ON_BOARD,
722 }
723 };
724
725 static int __devinit
726 sgiioc4_init_one(struct pci_dev *dev, const struct pci_device_id *id)
727 {
728 pci_init_sgiioc4(dev, &sgiioc4_chipsets[id->driver_data]);
729 return 0;
730 }
731
732 static struct pci_device_id sgiioc4_pci_tbl[] = {
733 {PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC4, PCI_ANY_ID,
734 PCI_ANY_ID, 0x0b4000, 0xFFFFFF, 0},
735 {0}
736 };
737 MODULE_DEVICE_TABLE(pci, sgiioc4_pci_tbl);
738
739 static struct pci_driver __devinitdata driver = {
740 .name = "SGI-IOC4_IDE",
741 .id_table = sgiioc4_pci_tbl,
742 .probe = sgiioc4_init_one,
743 };
744
745 static int __devinit
746 sgiioc4_ide_init(void)
747 {
748 return ide_pci_register_driver(&driver);
749 }
750
751 module_init(sgiioc4_ide_init);
752
753 MODULE_AUTHOR("Aniket Malatpure - Silicon Graphics Inc. (SGI)");
754 MODULE_DESCRIPTION("PCI driver module for SGI IOC4 Base-IO Card");
755 MODULE_LICENSE("GPL");
756
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