1 /*
2 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
3 * Due to massive hardware bugs, UltraDMA is only supported
4 * on the 646U2 and not on the 646U.
5 *
6 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
8 *
9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
10 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
11 */
12
13 #include <linux/module.h>
14 #include <linux/types.h>
15 #include <linux/pci.h>
16 #include <linux/hdreg.h>
17 #include <linux/ide.h>
18 #include <linux/init.h>
19
20 #include <asm/io.h>
21
22 #define CMD_DEBUG 0
23
24 #if CMD_DEBUG
25 #define cmdprintk(x...) printk(x)
26 #else
27 #define cmdprintk(x...)
28 #endif
29
30 /*
31 * CMD64x specific registers definition.
32 */
33 #define CFR 0x50
34 #define CFR_INTR_CH0 0x04
35
36 #define CMDTIM 0x52
37 #define ARTTIM0 0x53
38 #define DRWTIM0 0x54
39 #define ARTTIM1 0x55
40 #define DRWTIM1 0x56
41 #define ARTTIM23 0x57
42 #define ARTTIM23_DIS_RA2 0x04
43 #define ARTTIM23_DIS_RA3 0x08
44 #define ARTTIM23_INTR_CH1 0x10
45 #define DRWTIM2 0x58
46 #define BRST 0x59
47 #define DRWTIM3 0x5b
48
49 #define BMIDECR0 0x70
50 #define MRDMODE 0x71
51 #define MRDMODE_INTR_CH0 0x04
52 #define MRDMODE_INTR_CH1 0x08
53 #define UDIDETCR0 0x73
54 #define DTPR0 0x74
55 #define BMIDECR1 0x78
56 #define BMIDECSR 0x79
57 #define UDIDETCR1 0x7B
58 #define DTPR1 0x7C
59
60 static u8 quantize_timing(int timing, int quant)
61 {
62 return (timing + quant - 1) / quant;
63 }
64
65 /*
66 * This routine calculates active/recovery counts and then writes them into
67 * the chipset registers.
68 */
69 static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
70 {
71 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
72 int clock_time = 1000 / system_bus_clock();
73 u8 cycle_count, active_count, recovery_count, drwtim;
74 static const u8 recovery_values[] =
75 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
76 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
77
78 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
79 cycle_time, active_time);
80
81 cycle_count = quantize_timing( cycle_time, clock_time);
82 active_count = quantize_timing(active_time, clock_time);
83 recovery_count = cycle_count - active_count;
84
85 /*
86 * In case we've got too long recovery phase, try to lengthen
87 * the active phase
88 */
89 if (recovery_count > 16) {
90 active_count += recovery_count - 16;
91 recovery_count = 16;
92 }
93 if (active_count > 16) /* shouldn't actually happen... */
94 active_count = 16;
95
96 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
97 cycle_count, active_count, recovery_count);
98
99 /*
100 * Convert values to internal chipset representation
101 */
102 recovery_count = recovery_values[recovery_count];
103 active_count &= 0x0f;
104
105 /* Program the active/recovery counts into the DRWTIM register */
106 drwtim = (active_count << 4) | recovery_count;
107 (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
108 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
109 }
110
111 /*
112 * This routine writes into the chipset registers
113 * PIO setup/active/recovery timings.
114 */
115 static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
116 {
117 ide_hwif_t *hwif = HWIF(drive);
118 struct pci_dev *dev = to_pci_dev(hwif->dev);
119 unsigned int cycle_time;
120 u8 setup_count, arttim = 0;
121
122 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
123 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
124
125 cycle_time = ide_pio_cycle_time(drive, pio);
126
127 program_cycle_times(drive, cycle_time,
128 ide_pio_timings[pio].active_time);
129
130 setup_count = quantize_timing(ide_pio_timings[pio].setup_time,
131 1000 / system_bus_clock());
132
133 /*
134 * The primary channel has individual address setup timing registers
135 * for each drive and the hardware selects the slowest timing itself.
136 * The secondary channel has one common register and we have to select
137 * the slowest address setup timing ourselves.
138 */
139 if (hwif->channel) {
140 ide_drive_t *drives = hwif->drives;
141
142 drive->drive_data = setup_count;
143 setup_count = max(drives[0].drive_data, drives[1].drive_data);
144 }
145
146 if (setup_count > 5) /* shouldn't actually happen... */
147 setup_count = 5;
148 cmdprintk("Final address setup count: %d\n", setup_count);
149
150 /*
151 * Program the address setup clocks into the ARTTIM registers.
152 * Avoid clearing the secondary channel's interrupt bit.
153 */
154 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
155 if (hwif->channel)
156 arttim &= ~ARTTIM23_INTR_CH1;
157 arttim &= ~0xc0;
158 arttim |= setup_values[setup_count];
159 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
160 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
161 }
162
163 /*
164 * Attempts to set drive's PIO mode.
165 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
166 */
167
168 static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
169 {
170 /*
171 * Filter out the prefetch control values
172 * to prevent PIO5 from being programmed
173 */
174 if (pio == 8 || pio == 9)
175 return;
176
177 cmd64x_tune_pio(drive, pio);
178 }
179
180 static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
181 {
182 ide_hwif_t *hwif = HWIF(drive);
183 struct pci_dev *dev = to_pci_dev(hwif->dev);
184 u8 unit = drive->dn & 0x01;
185 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
186
187 if (speed >= XFER_SW_DMA_0) {
188 (void) pci_read_config_byte(dev, pciU, ®U);
189 regU &= ~(unit ? 0xCA : 0x35);
190 }
191
192 switch(speed) {
193 case XFER_UDMA_5:
194 regU |= unit ? 0x0A : 0x05;
195 break;
196 case XFER_UDMA_4:
197 regU |= unit ? 0x4A : 0x15;
198 break;
199 case XFER_UDMA_3:
200 regU |= unit ? 0x8A : 0x25;
201 break;
202 case XFER_UDMA_2:
203 regU |= unit ? 0x42 : 0x11;
204 break;
205 case XFER_UDMA_1:
206 regU |= unit ? 0x82 : 0x21;
207 break;
208 case XFER_UDMA_0:
209 regU |= unit ? 0xC2 : 0x31;
210 break;
211 case XFER_MW_DMA_2:
212 program_cycle_times(drive, 120, 70);
213 break;
214 case XFER_MW_DMA_1:
215 program_cycle_times(drive, 150, 80);
216 break;
217 case XFER_MW_DMA_0:
218 program_cycle_times(drive, 480, 215);
219 break;
220 }
221
222 if (speed >= XFER_SW_DMA_0)
223 (void) pci_write_config_byte(dev, pciU, regU);
224 }
225
226 static int cmd648_ide_dma_end (ide_drive_t *drive)
227 {
228 ide_hwif_t *hwif = HWIF(drive);
229 unsigned long base = hwif->dma_base - (hwif->channel * 8);
230 int err = __ide_dma_end(drive);
231 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
232 MRDMODE_INTR_CH0;
233 u8 mrdmode = inb(base + 1);
234
235 /* clear the interrupt bit */
236 outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
237 base + 1);
238
239 return err;
240 }
241
242 static int cmd64x_ide_dma_end (ide_drive_t *drive)
243 {
244 ide_hwif_t *hwif = HWIF(drive);
245 struct pci_dev *dev = to_pci_dev(hwif->dev);
246 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
247 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
248 CFR_INTR_CH0;
249 u8 irq_stat = 0;
250 int err = __ide_dma_end(drive);
251
252 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
253 /* clear the interrupt bit */
254 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
255
256 return err;
257 }
258
259 static int cmd648_ide_dma_test_irq (ide_drive_t *drive)
260 {
261 ide_hwif_t *hwif = HWIF(drive);
262 unsigned long base = hwif->dma_base - (hwif->channel * 8);
263 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
264 MRDMODE_INTR_CH0;
265 u8 dma_stat = inb(hwif->dma_status);
266 u8 mrdmode = inb(base + 1);
267
268 #ifdef DEBUG
269 printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
270 drive->name, dma_stat, mrdmode, irq_mask);
271 #endif
272 if (!(mrdmode & irq_mask))
273 return 0;
274
275 /* return 1 if INTR asserted */
276 if (dma_stat & 4)
277 return 1;
278
279 return 0;
280 }
281
282 static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
283 {
284 ide_hwif_t *hwif = HWIF(drive);
285 struct pci_dev *dev = to_pci_dev(hwif->dev);
286 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
287 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
288 CFR_INTR_CH0;
289 u8 dma_stat = inb(hwif->dma_status);
290 u8 irq_stat = 0;
291
292 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
293
294 #ifdef DEBUG
295 printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
296 drive->name, dma_stat, irq_stat, irq_mask);
297 #endif
298 if (!(irq_stat & irq_mask))
299 return 0;
300
301 /* return 1 if INTR asserted */
302 if (dma_stat & 4)
303 return 1;
304
305 return 0;
306 }
307
308 /*
309 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
310 * event order for DMA transfers.
311 */
312
313 static int cmd646_1_ide_dma_end (ide_drive_t *drive)
314 {
315 ide_hwif_t *hwif = HWIF(drive);
316 u8 dma_stat = 0, dma_cmd = 0;
317
318 drive->waiting_for_dma = 0;
319 /* get DMA status */
320 dma_stat = inb(hwif->dma_status);
321 /* read DMA command state */
322 dma_cmd = inb(hwif->dma_command);
323 /* stop DMA */
324 outb(dma_cmd & ~1, hwif->dma_command);
325 /* clear the INTR & ERROR bits */
326 outb(dma_stat | 6, hwif->dma_status);
327 /* and free any DMA resources */
328 ide_destroy_dmatable(drive);
329 /* verify good DMA status */
330 return (dma_stat & 7) != 4;
331 }
332
333 static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name)
334 {
335 u8 mrdmode = 0;
336
337 if (dev->device == PCI_DEVICE_ID_CMD_646) {
338
339 switch (dev->revision) {
340 case 0x07:
341 case 0x05:
342 printk("%s: UltraDMA capable\n", name);
343 break;
344 case 0x03:
345 default:
346 printk("%s: MultiWord DMA force limited\n", name);
347 break;
348 case 0x01:
349 printk("%s: MultiWord DMA limited, "
350 "IRQ workaround enabled\n", name);
351 break;
352 }
353 }
354
355 /* Set a good latency timer and cache line size value. */
356 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
357 /* FIXME: pci_set_master() to ensure a good latency timer value */
358
359 /*
360 * Enable interrupts, select MEMORY READ LINE for reads.
361 *
362 * NOTE: although not mentioned in the PCI0646U specs,
363 * bits 0-1 are write only and won't be read back as
364 * set or not -- PCI0646U2 specs clarify this point.
365 */
366 (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
367 mrdmode &= ~0x30;
368 (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
369
370 return 0;
371 }
372
373 static u8 __devinit ata66_cmd64x(ide_hwif_t *hwif)
374 {
375 struct pci_dev *dev = to_pci_dev(hwif->dev);
376 u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
377
378 switch (dev->device) {
379 case PCI_DEVICE_ID_CMD_648:
380 case PCI_DEVICE_ID_CMD_649:
381 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
382 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
383 default:
384 return ATA_CBL_PATA40;
385 }
386 }
387
388 static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
389 {
390 struct pci_dev *dev = to_pci_dev(hwif->dev);
391
392 hwif->set_pio_mode = &cmd64x_set_pio_mode;
393 hwif->set_dma_mode = &cmd64x_set_dma_mode;
394
395 hwif->cable_detect = ata66_cmd64x;
396
397 if (!hwif->dma_base)
398 return;
399
400 /*
401 * UltraDMA only supported on PCI646U and PCI646U2, which
402 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
403 * Actually, although the CMD tech support people won't
404 * tell me the details, the 0x03 revision cannot support
405 * UDMA correctly without hardware modifications, and even
406 * then it only works with Quantum disks due to some
407 * hold time assumptions in the 646U part which are fixed
408 * in the 646U2.
409 *
410 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
411 */
412 if (dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 5)
413 hwif->ultra_mask = 0x00;
414
415 switch (dev->device) {
416 case PCI_DEVICE_ID_CMD_648:
417 case PCI_DEVICE_ID_CMD_649:
418 alt_irq_bits:
419 hwif->ide_dma_end = &cmd648_ide_dma_end;
420 hwif->ide_dma_test_irq = &cmd648_ide_dma_test_irq;
421 break;
422 case PCI_DEVICE_ID_CMD_646:
423 if (dev->revision == 0x01) {
424 hwif->ide_dma_end = &cmd646_1_ide_dma_end;
425 break;
426 } else if (dev->revision >= 0x03)
427 goto alt_irq_bits;
428 /* fall thru */
429 default:
430 hwif->ide_dma_end = &cmd64x_ide_dma_end;
431 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
432 break;
433 }
434 }
435
436 static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
437 { /* 0 */
438 .name = "CMD643",
439 .init_chipset = init_chipset_cmd64x,
440 .init_hwif = init_hwif_cmd64x,
441 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
442 .host_flags = IDE_HFLAG_CLEAR_SIMPLEX |
443 IDE_HFLAG_ABUSE_PREFETCH |
444 IDE_HFLAG_BOOTABLE,
445 .pio_mask = ATA_PIO5,
446 .mwdma_mask = ATA_MWDMA2,
447 .udma_mask = 0x00, /* no udma */
448 },{ /* 1 */
449 .name = "CMD646",
450 .init_chipset = init_chipset_cmd64x,
451 .init_hwif = init_hwif_cmd64x,
452 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
453 .chipset = ide_cmd646,
454 .host_flags = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
455 .pio_mask = ATA_PIO5,
456 .mwdma_mask = ATA_MWDMA2,
457 .udma_mask = ATA_UDMA2,
458 },{ /* 2 */
459 .name = "CMD648",
460 .init_chipset = init_chipset_cmd64x,
461 .init_hwif = init_hwif_cmd64x,
462 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
463 .host_flags = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
464 .pio_mask = ATA_PIO5,
465 .mwdma_mask = ATA_MWDMA2,
466 .udma_mask = ATA_UDMA4,
467 },{ /* 3 */
468 .name = "CMD649",
469 .init_chipset = init_chipset_cmd64x,
470 .init_hwif = init_hwif_cmd64x,
471 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
472 .host_flags = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
473 .pio_mask = ATA_PIO5,
474 .mwdma_mask = ATA_MWDMA2,
475 .udma_mask = ATA_UDMA5,
476 }
477 };
478
479 static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
480 {
481 struct ide_port_info d;
482 u8 idx = id->driver_data;
483
484 d = cmd64x_chipsets[idx];
485
486 /*
487 * The original PCI0646 didn't have the primary channel enable bit,
488 * it appeared starting with PCI0646U (i.e. revision ID 3).
489 */
490 if (idx == 1 && dev->revision < 3)
491 d.enablebits[0].reg = 0;
492
493 return ide_setup_pci_device(dev, &d);
494 }
495
496 static const struct pci_device_id cmd64x_pci_tbl[] = {
497 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
498 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
499 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
500 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
501 { 0, },
502 };
503 MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
504
505 static struct pci_driver driver = {
506 .name = "CMD64x_IDE",
507 .id_table = cmd64x_pci_tbl,
508 .probe = cmd64x_init_one,
509 };
510
511 static int __init cmd64x_ide_init(void)
512 {
513 return ide_pci_register_driver(&driver);
514 }
515
516 module_init(cmd64x_ide_init);
517
518 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
519 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
520 MODULE_LICENSE("GPL");
521
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