1 /*
2 piix4.c - Part of lm_sensors, Linux kernel modules for hardware
3 monitoring
4 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
5 Philip Edelbrock <phil@netroedge.com>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 /*
23 Supports:
24 Intel PIIX4, 440MX
25 Serverworks OSB4, CSB5, CSB6, HT-1000
26 ATI IXP200, IXP300, IXP400, SB600, SB700, SB800
27 SMSC Victory66
28
29 Note: we assume there can only be one device, with one SMBus interface.
30 */
31
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/pci.h>
35 #include <linux/kernel.h>
36 #include <linux/delay.h>
37 #include <linux/stddef.h>
38 #include <linux/ioport.h>
39 #include <linux/i2c.h>
40 #include <linux/init.h>
41 #include <linux/apm_bios.h>
42 #include <linux/dmi.h>
43 #include <asm/io.h>
44
45
46 struct sd {
47 const unsigned short mfr;
48 const unsigned short dev;
49 const unsigned char fn;
50 const char *name;
51 };
52
53 /* PIIX4 SMBus address offsets */
54 #define SMBHSTSTS (0 + piix4_smba)
55 #define SMBHSLVSTS (1 + piix4_smba)
56 #define SMBHSTCNT (2 + piix4_smba)
57 #define SMBHSTCMD (3 + piix4_smba)
58 #define SMBHSTADD (4 + piix4_smba)
59 #define SMBHSTDAT0 (5 + piix4_smba)
60 #define SMBHSTDAT1 (6 + piix4_smba)
61 #define SMBBLKDAT (7 + piix4_smba)
62 #define SMBSLVCNT (8 + piix4_smba)
63 #define SMBSHDWCMD (9 + piix4_smba)
64 #define SMBSLVEVT (0xA + piix4_smba)
65 #define SMBSLVDAT (0xC + piix4_smba)
66
67 /* count for request_region */
68 #define SMBIOSIZE 8
69
70 /* PCI Address Constants */
71 #define SMBBA 0x090
72 #define SMBHSTCFG 0x0D2
73 #define SMBSLVC 0x0D3
74 #define SMBSHDW1 0x0D4
75 #define SMBSHDW2 0x0D5
76 #define SMBREV 0x0D6
77
78 /* Other settings */
79 #define MAX_TIMEOUT 500
80 #define ENABLE_INT9 0
81
82 /* PIIX4 constants */
83 #define PIIX4_QUICK 0x00
84 #define PIIX4_BYTE 0x04
85 #define PIIX4_BYTE_DATA 0x08
86 #define PIIX4_WORD_DATA 0x0C
87 #define PIIX4_BLOCK_DATA 0x14
88
89 /* insmod parameters */
90
91 /* If force is set to anything different from 0, we forcibly enable the
92 PIIX4. DANGEROUS! */
93 static int force;
94 module_param (force, int, 0);
95 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
96
97 /* If force_addr is set to anything different from 0, we forcibly enable
98 the PIIX4 at the given address. VERY DANGEROUS! */
99 static int force_addr;
100 module_param (force_addr, int, 0);
101 MODULE_PARM_DESC(force_addr,
102 "Forcibly enable the PIIX4 at the given address. "
103 "EXTREMELY DANGEROUS!");
104
105 static int piix4_transaction(void);
106
107 static unsigned short piix4_smba;
108 static struct pci_driver piix4_driver;
109 static struct i2c_adapter piix4_adapter;
110
111 static struct dmi_system_id __devinitdata piix4_dmi_blacklist[] = {
112 {
113 .ident = "Sapphire AM2RD790",
114 .matches = {
115 DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
116 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
117 },
118 },
119 {
120 .ident = "DFI Lanparty UT 790FX",
121 .matches = {
122 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
123 DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
124 },
125 },
126 { }
127 };
128
129 /* The IBM entry is in a separate table because we only check it
130 on Intel-based systems */
131 static struct dmi_system_id __devinitdata piix4_dmi_ibm[] = {
132 {
133 .ident = "IBM",
134 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
135 },
136 { },
137 };
138
139 static int __devinit piix4_setup(struct pci_dev *PIIX4_dev,
140 const struct pci_device_id *id)
141 {
142 unsigned char temp;
143
144 dev_info(&PIIX4_dev->dev, "Found %s device\n", pci_name(PIIX4_dev));
145
146 /* On some motherboards, it was reported that accessing the SMBus
147 caused severe hardware problems */
148 if (dmi_check_system(piix4_dmi_blacklist)) {
149 dev_err(&PIIX4_dev->dev,
150 "Accessing the SMBus on this system is unsafe!\n");
151 return -EPERM;
152 }
153
154 /* Don't access SMBus on IBM systems which get corrupted eeproms */
155 if (dmi_check_system(piix4_dmi_ibm) &&
156 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
157 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
158 "may corrupt your serial eeprom! Refusing to load "
159 "module!\n");
160 return -EPERM;
161 }
162
163 /* Determine the address of the SMBus areas */
164 if (force_addr) {
165 piix4_smba = force_addr & 0xfff0;
166 force = 0;
167 } else {
168 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
169 piix4_smba &= 0xfff0;
170 if(piix4_smba == 0) {
171 dev_err(&PIIX4_dev->dev, "SMB base address "
172 "uninitialized - upgrade BIOS or use "
173 "force_addr=0xaddr\n");
174 return -ENODEV;
175 }
176 }
177
178 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
179 dev_err(&PIIX4_dev->dev, "SMB region 0x%x already in use!\n",
180 piix4_smba);
181 return -ENODEV;
182 }
183
184 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
185
186 /* If force_addr is set, we program the new address here. Just to make
187 sure, we disable the PIIX4 first. */
188 if (force_addr) {
189 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
190 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
191 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
192 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
193 "new address %04x!\n", piix4_smba);
194 } else if ((temp & 1) == 0) {
195 if (force) {
196 /* This should never need to be done, but has been
197 * noted that many Dell machines have the SMBus
198 * interface on the PIIX4 disabled!? NOTE: This assumes
199 * I/O space and other allocations WERE done by the
200 * Bios! Don't complain if your hardware does weird
201 * things after enabling this. :') Check for Bios
202 * updates before resorting to this.
203 */
204 pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
205 temp | 1);
206 dev_printk(KERN_NOTICE, &PIIX4_dev->dev,
207 "WARNING: SMBus interface has been "
208 "FORCEFULLY ENABLED!\n");
209 } else {
210 dev_err(&PIIX4_dev->dev,
211 "Host SMBus controller not enabled!\n");
212 release_region(piix4_smba, SMBIOSIZE);
213 piix4_smba = 0;
214 return -ENODEV;
215 }
216 }
217
218 if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
219 dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n");
220 else if ((temp & 0x0E) == 0)
221 dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n");
222 else
223 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
224 "(or code out of date)!\n");
225
226 pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
227 dev_dbg(&PIIX4_dev->dev, "SMBREV = 0x%X\n", temp);
228 dev_dbg(&PIIX4_dev->dev, "SMBA = 0x%X\n", piix4_smba);
229
230 return 0;
231 }
232
233 /* Another internally used function */
234 static int piix4_transaction(void)
235 {
236 int temp;
237 int result = 0;
238 int timeout = 0;
239
240 dev_dbg(&piix4_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
241 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
242 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
243 inb_p(SMBHSTDAT1));
244
245 /* Make sure the SMBus host is ready to start transmitting */
246 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
247 dev_dbg(&piix4_adapter.dev, "SMBus busy (%02x). "
248 "Resetting...\n", temp);
249 outb_p(temp, SMBHSTSTS);
250 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
251 dev_err(&piix4_adapter.dev, "Failed! (%02x)\n", temp);
252 return -1;
253 } else {
254 dev_dbg(&piix4_adapter.dev, "Successfull!\n");
255 }
256 }
257
258 /* start the transaction by setting bit 6 */
259 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
260
261 /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
262 do {
263 msleep(1);
264 temp = inb_p(SMBHSTSTS);
265 } while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
266
267 /* If the SMBus is still busy, we give up */
268 if (timeout >= MAX_TIMEOUT) {
269 dev_err(&piix4_adapter.dev, "SMBus Timeout!\n");
270 result = -1;
271 }
272
273 if (temp & 0x10) {
274 result = -1;
275 dev_err(&piix4_adapter.dev, "Error: Failed bus transaction\n");
276 }
277
278 if (temp & 0x08) {
279 result = -1;
280 dev_dbg(&piix4_adapter.dev, "Bus collision! SMBus may be "
281 "locked until next hard reset. (sorry!)\n");
282 /* Clock stops and slave is stuck in mid-transmission */
283 }
284
285 if (temp & 0x04) {
286 result = -1;
287 dev_dbg(&piix4_adapter.dev, "Error: no response!\n");
288 }
289
290 if (inb_p(SMBHSTSTS) != 0x00)
291 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
292
293 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
294 dev_err(&piix4_adapter.dev, "Failed reset at end of "
295 "transaction (%02x)\n", temp);
296 }
297 dev_dbg(&piix4_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
298 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
299 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
300 inb_p(SMBHSTDAT1));
301 return result;
302 }
303
304 /* Return -1 on error. */
305 static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
306 unsigned short flags, char read_write,
307 u8 command, int size, union i2c_smbus_data * data)
308 {
309 int i, len;
310
311 switch (size) {
312 case I2C_SMBUS_PROC_CALL:
313 dev_err(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n");
314 return -1;
315 case I2C_SMBUS_QUICK:
316 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
317 SMBHSTADD);
318 size = PIIX4_QUICK;
319 break;
320 case I2C_SMBUS_BYTE:
321 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
322 SMBHSTADD);
323 if (read_write == I2C_SMBUS_WRITE)
324 outb_p(command, SMBHSTCMD);
325 size = PIIX4_BYTE;
326 break;
327 case I2C_SMBUS_BYTE_DATA:
328 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
329 SMBHSTADD);
330 outb_p(command, SMBHSTCMD);
331 if (read_write == I2C_SMBUS_WRITE)
332 outb_p(data->byte, SMBHSTDAT0);
333 size = PIIX4_BYTE_DATA;
334 break;
335 case I2C_SMBUS_WORD_DATA:
336 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
337 SMBHSTADD);
338 outb_p(command, SMBHSTCMD);
339 if (read_write == I2C_SMBUS_WRITE) {
340 outb_p(data->word & 0xff, SMBHSTDAT0);
341 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
342 }
343 size = PIIX4_WORD_DATA;
344 break;
345 case I2C_SMBUS_BLOCK_DATA:
346 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
347 SMBHSTADD);
348 outb_p(command, SMBHSTCMD);
349 if (read_write == I2C_SMBUS_WRITE) {
350 len = data->block[0];
351 if (len < 0)
352 len = 0;
353 if (len > 32)
354 len = 32;
355 outb_p(len, SMBHSTDAT0);
356 i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
357 for (i = 1; i <= len; i++)
358 outb_p(data->block[i], SMBBLKDAT);
359 }
360 size = PIIX4_BLOCK_DATA;
361 break;
362 }
363
364 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
365
366 if (piix4_transaction()) /* Error in transaction */
367 return -1;
368
369 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
370 return 0;
371
372
373 switch (size) {
374 case PIIX4_BYTE: /* Where is the result put? I assume here it is in
375 SMBHSTDAT0 but it might just as well be in the
376 SMBHSTCMD. No clue in the docs */
377
378 data->byte = inb_p(SMBHSTDAT0);
379 break;
380 case PIIX4_BYTE_DATA:
381 data->byte = inb_p(SMBHSTDAT0);
382 break;
383 case PIIX4_WORD_DATA:
384 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
385 break;
386 case PIIX4_BLOCK_DATA:
387 data->block[0] = inb_p(SMBHSTDAT0);
388 i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
389 for (i = 1; i <= data->block[0]; i++)
390 data->block[i] = inb_p(SMBBLKDAT);
391 break;
392 }
393 return 0;
394 }
395
396 static u32 piix4_func(struct i2c_adapter *adapter)
397 {
398 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
399 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
400 I2C_FUNC_SMBUS_BLOCK_DATA;
401 }
402
403 static const struct i2c_algorithm smbus_algorithm = {
404 .smbus_xfer = piix4_access,
405 .functionality = piix4_func,
406 };
407
408 static struct i2c_adapter piix4_adapter = {
409 .owner = THIS_MODULE,
410 .id = I2C_HW_SMBUS_PIIX4,
411 .class = I2C_CLASS_HWMON,
412 .algo = &smbus_algorithm,
413 };
414
415 static struct pci_device_id piix4_ids[] = {
416 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
417 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
418 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
419 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
420 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
421 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
422 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
423 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
424 PCI_DEVICE_ID_SERVERWORKS_OSB4) },
425 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
426 PCI_DEVICE_ID_SERVERWORKS_CSB5) },
427 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
428 PCI_DEVICE_ID_SERVERWORKS_CSB6) },
429 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
430 PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
431 { 0, }
432 };
433
434 MODULE_DEVICE_TABLE (pci, piix4_ids);
435
436 static int __devinit piix4_probe(struct pci_dev *dev,
437 const struct pci_device_id *id)
438 {
439 int retval;
440
441 retval = piix4_setup(dev, id);
442 if (retval)
443 return retval;
444
445 /* set up the sysfs linkage to our parent device */
446 piix4_adapter.dev.parent = &dev->dev;
447
448 snprintf(piix4_adapter.name, sizeof(piix4_adapter.name),
449 "SMBus PIIX4 adapter at %04x", piix4_smba);
450
451 if ((retval = i2c_add_adapter(&piix4_adapter))) {
452 dev_err(&dev->dev, "Couldn't register adapter!\n");
453 release_region(piix4_smba, SMBIOSIZE);
454 piix4_smba = 0;
455 }
456
457 return retval;
458 }
459
460 static void __devexit piix4_remove(struct pci_dev *dev)
461 {
462 if (piix4_smba) {
463 i2c_del_adapter(&piix4_adapter);
464 release_region(piix4_smba, SMBIOSIZE);
465 piix4_smba = 0;
466 }
467 }
468
469 static struct pci_driver piix4_driver = {
470 .name = "piix4_smbus",
471 .id_table = piix4_ids,
472 .probe = piix4_probe,
473 .remove = __devexit_p(piix4_remove),
474 };
475
476 static int __init i2c_piix4_init(void)
477 {
478 return pci_register_driver(&piix4_driver);
479 }
480
481 static void __exit i2c_piix4_exit(void)
482 {
483 pci_unregister_driver(&piix4_driver);
484 }
485
486 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
487 "Philip Edelbrock <phil@netroedge.com>");
488 MODULE_DESCRIPTION("PIIX4 SMBus driver");
489 MODULE_LICENSE("GPL");
490
491 module_init(i2c_piix4_init);
492 module_exit(i2c_piix4_exit);
493
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