1 /*
2 * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface
3 * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
4 *
5 * 2.6 port by Matt Porter <mporter@kernel.crashing.org>
6 *
7 * The documentation describes this as an SMBus controller, but it doesn't
8 * understand any of the SMBus protocol in hardware. It's really an I2C
9 * controller that could emulate most of the SMBus in software.
10 *
11 * This is just a skeleton adapter to use with the Au1550 PSC
12 * algorithm. It was developed for the Pb1550, but will work with
13 * any Au1550 board that has a similar PSC configuration.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 */
29
30 #include <linux/delay.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/platform_device.h>
34 #include <linux/init.h>
35 #include <linux/errno.h>
36 #include <linux/i2c.h>
37 #include <linux/slab.h>
38
39 #include <asm/mach-au1x00/au1xxx.h>
40 #include <asm/mach-au1x00/au1xxx_psc.h>
41
42 struct i2c_au1550_data {
43 u32 psc_base;
44 int xfer_timeout;
45 int ack_timeout;
46 struct i2c_adapter adap;
47 struct resource *ioarea;
48 };
49
50 static int
51 wait_xfer_done(struct i2c_au1550_data *adap)
52 {
53 u32 stat;
54 int i;
55 volatile psc_smb_t *sp;
56
57 sp = (volatile psc_smb_t *)(adap->psc_base);
58
59 /* Wait for Tx Buffer Empty
60 */
61 for (i = 0; i < adap->xfer_timeout; i++) {
62 stat = sp->psc_smbstat;
63 au_sync();
64 if ((stat & PSC_SMBSTAT_TE) != 0)
65 return 0;
66
67 udelay(1);
68 }
69
70 return -ETIMEDOUT;
71 }
72
73 static int
74 wait_ack(struct i2c_au1550_data *adap)
75 {
76 u32 stat;
77 volatile psc_smb_t *sp;
78
79 if (wait_xfer_done(adap))
80 return -ETIMEDOUT;
81
82 sp = (volatile psc_smb_t *)(adap->psc_base);
83
84 stat = sp->psc_smbevnt;
85 au_sync();
86
87 if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0)
88 return -ETIMEDOUT;
89
90 return 0;
91 }
92
93 static int
94 wait_master_done(struct i2c_au1550_data *adap)
95 {
96 u32 stat;
97 int i;
98 volatile psc_smb_t *sp;
99
100 sp = (volatile psc_smb_t *)(adap->psc_base);
101
102 /* Wait for Master Done.
103 */
104 for (i = 0; i < adap->xfer_timeout; i++) {
105 stat = sp->psc_smbevnt;
106 au_sync();
107 if ((stat & PSC_SMBEVNT_MD) != 0)
108 return 0;
109 udelay(1);
110 }
111
112 return -ETIMEDOUT;
113 }
114
115 static int
116 do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q)
117 {
118 volatile psc_smb_t *sp;
119 u32 stat;
120
121 sp = (volatile psc_smb_t *)(adap->psc_base);
122
123 /* Reset the FIFOs, clear events.
124 */
125 stat = sp->psc_smbstat;
126 sp->psc_smbevnt = PSC_SMBEVNT_ALLCLR;
127 au_sync();
128
129 if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) {
130 sp->psc_smbpcr = PSC_SMBPCR_DC;
131 au_sync();
132 do {
133 stat = sp->psc_smbpcr;
134 au_sync();
135 } while ((stat & PSC_SMBPCR_DC) != 0);
136 udelay(50);
137 }
138
139 /* Write out the i2c chip address and specify operation
140 */
141 addr <<= 1;
142 if (rd)
143 addr |= 1;
144
145 /* zero-byte xfers stop immediately */
146 if (q)
147 addr |= PSC_SMBTXRX_STP;
148
149 /* Put byte into fifo, start up master.
150 */
151 sp->psc_smbtxrx = addr;
152 au_sync();
153 sp->psc_smbpcr = PSC_SMBPCR_MS;
154 au_sync();
155 if (wait_ack(adap))
156 return -EIO;
157 return (q) ? wait_master_done(adap) : 0;
158 }
159
160 static u32
161 wait_for_rx_byte(struct i2c_au1550_data *adap, u32 *ret_data)
162 {
163 int j;
164 u32 data, stat;
165 volatile psc_smb_t *sp;
166
167 if (wait_xfer_done(adap))
168 return -EIO;
169
170 sp = (volatile psc_smb_t *)(adap->psc_base);
171
172 j = adap->xfer_timeout * 100;
173 do {
174 j--;
175 if (j <= 0)
176 return -EIO;
177
178 stat = sp->psc_smbstat;
179 au_sync();
180 if ((stat & PSC_SMBSTAT_RE) == 0)
181 j = 0;
182 else
183 udelay(1);
184 } while (j > 0);
185 data = sp->psc_smbtxrx;
186 au_sync();
187 *ret_data = data;
188
189 return 0;
190 }
191
192 static int
193 i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
194 unsigned int len)
195 {
196 int i;
197 u32 data;
198 volatile psc_smb_t *sp;
199
200 if (len == 0)
201 return 0;
202
203 /* A read is performed by stuffing the transmit fifo with
204 * zero bytes for timing, waiting for bytes to appear in the
205 * receive fifo, then reading the bytes.
206 */
207
208 sp = (volatile psc_smb_t *)(adap->psc_base);
209
210 i = 0;
211 while (i < (len-1)) {
212 sp->psc_smbtxrx = 0;
213 au_sync();
214 if (wait_for_rx_byte(adap, &data))
215 return -EIO;
216
217 buf[i] = data;
218 i++;
219 }
220
221 /* The last byte has to indicate transfer done.
222 */
223 sp->psc_smbtxrx = PSC_SMBTXRX_STP;
224 au_sync();
225 if (wait_master_done(adap))
226 return -EIO;
227
228 data = sp->psc_smbtxrx;
229 au_sync();
230 buf[i] = data;
231 return 0;
232 }
233
234 static int
235 i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
236 unsigned int len)
237 {
238 int i;
239 u32 data;
240 volatile psc_smb_t *sp;
241
242 if (len == 0)
243 return 0;
244
245 sp = (volatile psc_smb_t *)(adap->psc_base);
246
247 i = 0;
248 while (i < (len-1)) {
249 data = buf[i];
250 sp->psc_smbtxrx = data;
251 au_sync();
252 if (wait_ack(adap))
253 return -EIO;
254 i++;
255 }
256
257 /* The last byte has to indicate transfer done.
258 */
259 data = buf[i];
260 data |= PSC_SMBTXRX_STP;
261 sp->psc_smbtxrx = data;
262 au_sync();
263 if (wait_master_done(adap))
264 return -EIO;
265 return 0;
266 }
267
268 static int
269 au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
270 {
271 struct i2c_au1550_data *adap = i2c_adap->algo_data;
272 struct i2c_msg *p;
273 int i, err = 0;
274
275 for (i = 0; !err && i < num; i++) {
276 p = &msgs[i];
277 err = do_address(adap, p->addr, p->flags & I2C_M_RD,
278 (p->len == 0));
279 if (err || !p->len)
280 continue;
281 if (p->flags & I2C_M_RD)
282 err = i2c_read(adap, p->buf, p->len);
283 else
284 err = i2c_write(adap, p->buf, p->len);
285 }
286
287 /* Return the number of messages processed, or the error code.
288 */
289 if (err == 0)
290 err = num;
291 return err;
292 }
293
294 static u32
295 au1550_func(struct i2c_adapter *adap)
296 {
297 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
298 }
299
300 static const struct i2c_algorithm au1550_algo = {
301 .master_xfer = au1550_xfer,
302 .functionality = au1550_func,
303 };
304
305 /*
306 * registering functions to load algorithms at runtime
307 * Prior to calling us, the 50MHz clock frequency and routing
308 * must have been set up for the PSC indicated by the adapter.
309 */
310 static int __devinit
311 i2c_au1550_probe(struct platform_device *pdev)
312 {
313 struct i2c_au1550_data *priv;
314 volatile psc_smb_t *sp;
315 struct resource *r;
316 u32 stat;
317 int ret;
318
319 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
320 if (!r) {
321 ret = -ENODEV;
322 goto out;
323 }
324
325 priv = kzalloc(sizeof(struct i2c_au1550_data), GFP_KERNEL);
326 if (!priv) {
327 ret = -ENOMEM;
328 goto out;
329 }
330
331 priv->ioarea = request_mem_region(r->start, r->end - r->start + 1,
332 pdev->name);
333 if (!priv->ioarea) {
334 ret = -EBUSY;
335 goto out_mem;
336 }
337
338 priv->psc_base = r->start;
339 priv->xfer_timeout = 200;
340 priv->ack_timeout = 200;
341
342 priv->adap.id = I2C_HW_AU1550_PSC;
343 priv->adap.nr = pdev->id;
344 priv->adap.algo = &au1550_algo;
345 priv->adap.algo_data = priv;
346 priv->adap.dev.parent = &pdev->dev;
347 strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
348
349 /* Now, set up the PSC for SMBus PIO mode.
350 */
351 sp = (volatile psc_smb_t *)priv->psc_base;
352 sp->psc_ctrl = PSC_CTRL_DISABLE;
353 au_sync();
354 sp->psc_sel = PSC_SEL_PS_SMBUSMODE;
355 sp->psc_smbcfg = 0;
356 au_sync();
357 sp->psc_ctrl = PSC_CTRL_ENABLE;
358 au_sync();
359 do {
360 stat = sp->psc_smbstat;
361 au_sync();
362 } while ((stat & PSC_SMBSTAT_SR) == 0);
363
364 sp->psc_smbcfg = (PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 |
365 PSC_SMBCFG_DD_DISABLE);
366
367 /* Divide by 8 to get a 6.25 MHz clock. The later protocol
368 * timings are based on this clock.
369 */
370 sp->psc_smbcfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
371 sp->psc_smbmsk = PSC_SMBMSK_ALLMASK;
372 au_sync();
373
374 /* Set the protocol timer values. See Table 71 in the
375 * Au1550 Data Book for standard timing values.
376 */
377 sp->psc_smbtmr = PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \
378 PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \
379 PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \
380 PSC_SMBTMR_SET_CH(15);
381 au_sync();
382
383 sp->psc_smbcfg |= PSC_SMBCFG_DE_ENABLE;
384 do {
385 stat = sp->psc_smbstat;
386 au_sync();
387 } while ((stat & PSC_SMBSTAT_DR) == 0);
388
389 ret = i2c_add_numbered_adapter(&priv->adap);
390 if (ret == 0) {
391 platform_set_drvdata(pdev, priv);
392 return 0;
393 }
394
395 /* disable the PSC */
396 sp->psc_smbcfg = 0;
397 sp->psc_ctrl = PSC_CTRL_DISABLE;
398 au_sync();
399
400 release_resource(priv->ioarea);
401 kfree(priv->ioarea);
402 out_mem:
403 kfree(priv);
404 out:
405 return ret;
406 }
407
408 static int __devexit
409 i2c_au1550_remove(struct platform_device *pdev)
410 {
411 struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
412 volatile psc_smb_t *sp = (volatile psc_smb_t *)priv->psc_base;
413
414 platform_set_drvdata(pdev, NULL);
415 i2c_del_adapter(&priv->adap);
416 sp->psc_smbcfg = 0;
417 sp->psc_ctrl = PSC_CTRL_DISABLE;
418 au_sync();
419 release_resource(priv->ioarea);
420 kfree(priv->ioarea);
421 kfree(priv);
422 return 0;
423 }
424
425 static int
426 i2c_au1550_suspend(struct platform_device *pdev, pm_message_t state)
427 {
428 struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
429 volatile psc_smb_t *sp = (volatile psc_smb_t *)priv->psc_base;
430
431 sp->psc_ctrl = PSC_CTRL_SUSPEND;
432 au_sync();
433 return 0;
434 }
435
436 static int
437 i2c_au1550_resume(struct platform_device *pdev)
438 {
439 struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
440 volatile psc_smb_t *sp = (volatile psc_smb_t *)priv->psc_base;
441
442 sp->psc_ctrl = PSC_CTRL_ENABLE;
443 au_sync();
444 while (!(sp->psc_smbstat & PSC_SMBSTAT_SR))
445 au_sync();
446 return 0;
447 }
448
449 static struct platform_driver au1xpsc_smbus_driver = {
450 .driver = {
451 .name = "au1xpsc_smbus",
452 .owner = THIS_MODULE,
453 },
454 .probe = i2c_au1550_probe,
455 .remove = __devexit_p(i2c_au1550_remove),
456 .suspend = i2c_au1550_suspend,
457 .resume = i2c_au1550_resume,
458 };
459
460 static int __init
461 i2c_au1550_init(void)
462 {
463 return platform_driver_register(&au1xpsc_smbus_driver);
464 }
465
466 static void __exit
467 i2c_au1550_exit(void)
468 {
469 platform_driver_unregister(&au1xpsc_smbus_driver);
470 }
471
472 MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
473 MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
474 MODULE_LICENSE("GPL");
475
476 module_init (i2c_au1550_init);
477 module_exit (i2c_au1550_exit);
478
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