1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef RS690R_H
29 #define RS690R_H
30
31 /* RS690/RS740 registers */
32 #define MC_INDEX 0x0078
33 # define MC_INDEX_MASK 0x1FF
34 # define MC_INDEX_WR_EN (1 << 9)
35 # define MC_INDEX_WR_ACK 0x7F
36 #define MC_DATA 0x007C
37 #define HDP_FB_LOCATION 0x0134
38 #define DC_LB_MEMORY_SPLIT 0x6520
39 #define DC_LB_MEMORY_SPLIT_MASK 0x00000003
40 #define DC_LB_MEMORY_SPLIT_SHIFT 0
41 #define DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0
42 #define DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1
43 #define DC_LB_MEMORY_SPLIT_D1_ONLY 2
44 #define DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3
45 #define DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2)
46 #define DC_LB_DISP1_END_ADR_SHIFT 4
47 #define DC_LB_DISP1_END_ADR_MASK 0x00007FF0
48 #define D1MODE_PRIORITY_A_CNT 0x6548
49 #define MODE_PRIORITY_MARK_MASK 0x00007FFF
50 #define MODE_PRIORITY_OFF (1 << 16)
51 #define MODE_PRIORITY_ALWAYS_ON (1 << 20)
52 #define MODE_PRIORITY_FORCE_MASK (1 << 24)
53 #define D1MODE_PRIORITY_B_CNT 0x654C
54 #define LB_MAX_REQ_OUTSTANDING 0x6D58
55 #define LB_D1_MAX_REQ_OUTSTANDING_MASK 0x0000000F
56 #define LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0
57 #define LB_D2_MAX_REQ_OUTSTANDING_MASK 0x000F0000
58 #define LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16
59 #define DCP_CONTROL 0x6C9C
60 #define D2MODE_PRIORITY_A_CNT 0x6D48
61 #define D2MODE_PRIORITY_B_CNT 0x6D4C
62
63 /* MC indirect registers */
64 #define MC_STATUS_IDLE (1 << 0)
65 #define MC_MISC_CNTL 0x18
66 #define DISABLE_GTW (1 << 1)
67 #define GART_INDEX_REG_EN (1 << 12)
68 #define BLOCK_GFX_D3_EN (1 << 14)
69 #define GART_FEATURE_ID 0x2B
70 #define HANG_EN (1 << 11)
71 #define TLB_ENABLE (1 << 18)
72 #define P2P_ENABLE (1 << 19)
73 #define GTW_LAC_EN (1 << 25)
74 #define LEVEL2_GART (0 << 30)
75 #define LEVEL1_GART (1 << 30)
76 #define PDC_EN (1 << 31)
77 #define GART_BASE 0x2C
78 #define GART_CACHE_CNTRL 0x2E
79 # define GART_CACHE_INVALIDATE (1 << 0)
80 #define MC_STATUS 0x90
81 #define MCCFG_FB_LOCATION 0x100
82 #define MC_FB_START_MASK 0x0000FFFF
83 #define MC_FB_START_SHIFT 0
84 #define MC_FB_TOP_MASK 0xFFFF0000
85 #define MC_FB_TOP_SHIFT 16
86 #define MCCFG_AGP_LOCATION 0x101
87 #define MC_AGP_START_MASK 0x0000FFFF
88 #define MC_AGP_START_SHIFT 0
89 #define MC_AGP_TOP_MASK 0xFFFF0000
90 #define MC_AGP_TOP_SHIFT 16
91 #define MCCFG_AGP_BASE 0x102
92 #define MCCFG_AGP_BASE_2 0x103
93 #define MC_INIT_MISC_LAT_TIMER 0x104
94 #define MC_DISP0R_INIT_LAT_SHIFT 8
95 #define MC_DISP0R_INIT_LAT_MASK 0x00000F00
96 #define MC_DISP1R_INIT_LAT_SHIFT 12
97 #define MC_DISP1R_INIT_LAT_MASK 0x0000F000
98
99 #endif
100
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