1 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
3 */
4 /*
5 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
7 * All Rights Reserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "r128_drm.h"
35 #include "r128_drv.h"
36
37 #define R128_FIFO_DEBUG 0
38
39 /* CCE microcode (from ATI) */
40 static u32 r128_cce_microcode[] = {
41 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
42 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
43 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
44 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
45 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
46 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
47 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
48 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
49 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
50 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
51 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
52 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
53 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
54 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
55 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
56 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
57 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
58 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
59 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
60 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
61 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
62 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
63 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
64 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
65 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
66 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
67 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
68 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
69 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
70 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
71 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
72 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
73 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
74 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
75 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
76 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
77 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
78 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
81 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
82 };
83
84 static int R128_READ_PLL(struct drm_device * dev, int addr)
85 {
86 drm_r128_private_t *dev_priv = dev->dev_private;
87
88 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
89 return R128_READ(R128_CLOCK_CNTL_DATA);
90 }
91
92 #if R128_FIFO_DEBUG
93 static void r128_status(drm_r128_private_t * dev_priv)
94 {
95 printk("GUI_STAT = 0x%08x\n",
96 (unsigned int)R128_READ(R128_GUI_STAT));
97 printk("PM4_STAT = 0x%08x\n",
98 (unsigned int)R128_READ(R128_PM4_STAT));
99 printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
100 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
101 printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
102 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
103 printk("PM4_MICRO_CNTL = 0x%08x\n",
104 (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
105 printk("PM4_BUFFER_CNTL = 0x%08x\n",
106 (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
107 }
108 #endif
109
110 /* ================================================================
111 * Engine, FIFO control
112 */
113
114 static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv)
115 {
116 u32 tmp;
117 int i;
118
119 tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
120 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
121
122 for (i = 0; i < dev_priv->usec_timeout; i++) {
123 if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) {
124 return 0;
125 }
126 DRM_UDELAY(1);
127 }
128
129 #if R128_FIFO_DEBUG
130 DRM_ERROR("failed!\n");
131 #endif
132 return -EBUSY;
133 }
134
135 static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries)
136 {
137 int i;
138
139 for (i = 0; i < dev_priv->usec_timeout; i++) {
140 int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
141 if (slots >= entries)
142 return 0;
143 DRM_UDELAY(1);
144 }
145
146 #if R128_FIFO_DEBUG
147 DRM_ERROR("failed!\n");
148 #endif
149 return -EBUSY;
150 }
151
152 static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)
153 {
154 int i, ret;
155
156 ret = r128_do_wait_for_fifo(dev_priv, 64);
157 if (ret)
158 return ret;
159
160 for (i = 0; i < dev_priv->usec_timeout; i++) {
161 if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
162 r128_do_pixcache_flush(dev_priv);
163 return 0;
164 }
165 DRM_UDELAY(1);
166 }
167
168 #if R128_FIFO_DEBUG
169 DRM_ERROR("failed!\n");
170 #endif
171 return -EBUSY;
172 }
173
174 /* ================================================================
175 * CCE control, initialization
176 */
177
178 /* Load the microcode for the CCE */
179 static void r128_cce_load_microcode(drm_r128_private_t * dev_priv)
180 {
181 int i;
182
183 DRM_DEBUG("\n");
184
185 r128_do_wait_for_idle(dev_priv);
186
187 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
188 for (i = 0; i < 256; i++) {
189 R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]);
190 R128_WRITE(R128_PM4_MICROCODE_DATAL,
191 r128_cce_microcode[i * 2 + 1]);
192 }
193 }
194
195 /* Flush any pending commands to the CCE. This should only be used just
196 * prior to a wait for idle, as it informs the engine that the command
197 * stream is ending.
198 */
199 static void r128_do_cce_flush(drm_r128_private_t * dev_priv)
200 {
201 u32 tmp;
202
203 tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
204 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
205 }
206
207 /* Wait for the CCE to go idle.
208 */
209 int r128_do_cce_idle(drm_r128_private_t * dev_priv)
210 {
211 int i;
212
213 for (i = 0; i < dev_priv->usec_timeout; i++) {
214 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
215 int pm4stat = R128_READ(R128_PM4_STAT);
216 if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
217 dev_priv->cce_fifo_size) &&
218 !(pm4stat & (R128_PM4_BUSY |
219 R128_PM4_GUI_ACTIVE))) {
220 return r128_do_pixcache_flush(dev_priv);
221 }
222 }
223 DRM_UDELAY(1);
224 }
225
226 #if R128_FIFO_DEBUG
227 DRM_ERROR("failed!\n");
228 r128_status(dev_priv);
229 #endif
230 return -EBUSY;
231 }
232
233 /* Start the Concurrent Command Engine.
234 */
235 static void r128_do_cce_start(drm_r128_private_t * dev_priv)
236 {
237 r128_do_wait_for_idle(dev_priv);
238
239 R128_WRITE(R128_PM4_BUFFER_CNTL,
240 dev_priv->cce_mode | dev_priv->ring.size_l2qw
241 | R128_PM4_BUFFER_CNTL_NOUPDATE);
242 R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */
243 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
244
245 dev_priv->cce_running = 1;
246 }
247
248 /* Reset the Concurrent Command Engine. This will not flush any pending
249 * commands, so you must wait for the CCE command stream to complete
250 * before calling this routine.
251 */
252 static void r128_do_cce_reset(drm_r128_private_t * dev_priv)
253 {
254 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
255 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
256 dev_priv->ring.tail = 0;
257 }
258
259 /* Stop the Concurrent Command Engine. This will not flush any pending
260 * commands, so you must flush the command stream and wait for the CCE
261 * to go idle before calling this routine.
262 */
263 static void r128_do_cce_stop(drm_r128_private_t * dev_priv)
264 {
265 R128_WRITE(R128_PM4_MICRO_CNTL, 0);
266 R128_WRITE(R128_PM4_BUFFER_CNTL,
267 R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
268
269 dev_priv->cce_running = 0;
270 }
271
272 /* Reset the engine. This will stop the CCE if it is running.
273 */
274 static int r128_do_engine_reset(struct drm_device * dev)
275 {
276 drm_r128_private_t *dev_priv = dev->dev_private;
277 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
278
279 r128_do_pixcache_flush(dev_priv);
280
281 clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
282 mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
283
284 R128_WRITE_PLL(R128_MCLK_CNTL,
285 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
286
287 gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
288
289 /* Taken from the sample code - do not change */
290 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
291 R128_READ(R128_GEN_RESET_CNTL);
292 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
293 R128_READ(R128_GEN_RESET_CNTL);
294
295 R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
296 R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
297 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
298
299 /* Reset the CCE ring */
300 r128_do_cce_reset(dev_priv);
301
302 /* The CCE is no longer running after an engine reset */
303 dev_priv->cce_running = 0;
304
305 /* Reset any pending vertex, indirect buffers */
306 r128_freelist_reset(dev);
307
308 return 0;
309 }
310
311 static void r128_cce_init_ring_buffer(struct drm_device * dev,
312 drm_r128_private_t * dev_priv)
313 {
314 u32 ring_start;
315 u32 tmp;
316
317 DRM_DEBUG("\n");
318
319 /* The manual (p. 2) says this address is in "VM space". This
320 * means it's an offset from the start of AGP space.
321 */
322 #if __OS_HAS_AGP
323 if (!dev_priv->is_pci)
324 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
325 else
326 #endif
327 ring_start = dev_priv->cce_ring->offset -
328 (unsigned long)dev->sg->virtual;
329
330 R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
331
332 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
333 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
334
335 /* Set watermark control */
336 R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
337 ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
338 | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
339 | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
340 | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
341
342 /* Force read. Why? Because it's in the examples... */
343 R128_READ(R128_PM4_BUFFER_ADDR);
344
345 /* Turn on bus mastering */
346 tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
347 R128_WRITE(R128_BUS_CNTL, tmp);
348 }
349
350 static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init)
351 {
352 drm_r128_private_t *dev_priv;
353
354 DRM_DEBUG("\n");
355
356 if (dev->dev_private) {
357 DRM_DEBUG("called when already initialized\n");
358 return -EINVAL;
359 }
360
361 dev_priv = kzalloc(sizeof(drm_r128_private_t), GFP_KERNEL);
362 if (dev_priv == NULL)
363 return -ENOMEM;
364
365 dev_priv->is_pci = init->is_pci;
366
367 if (dev_priv->is_pci && !dev->sg) {
368 DRM_ERROR("PCI GART memory not allocated!\n");
369 dev->dev_private = (void *)dev_priv;
370 r128_do_cleanup_cce(dev);
371 return -EINVAL;
372 }
373
374 dev_priv->usec_timeout = init->usec_timeout;
375 if (dev_priv->usec_timeout < 1 ||
376 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
377 DRM_DEBUG("TIMEOUT problem!\n");
378 dev->dev_private = (void *)dev_priv;
379 r128_do_cleanup_cce(dev);
380 return -EINVAL;
381 }
382
383 dev_priv->cce_mode = init->cce_mode;
384
385 /* GH: Simple idle check.
386 */
387 atomic_set(&dev_priv->idle_count, 0);
388
389 /* We don't support anything other than bus-mastering ring mode,
390 * but the ring can be in either AGP or PCI space for the ring
391 * read pointer.
392 */
393 if ((init->cce_mode != R128_PM4_192BM) &&
394 (init->cce_mode != R128_PM4_128BM_64INDBM) &&
395 (init->cce_mode != R128_PM4_64BM_128INDBM) &&
396 (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
397 DRM_DEBUG("Bad cce_mode!\n");
398 dev->dev_private = (void *)dev_priv;
399 r128_do_cleanup_cce(dev);
400 return -EINVAL;
401 }
402
403 switch (init->cce_mode) {
404 case R128_PM4_NONPM4:
405 dev_priv->cce_fifo_size = 0;
406 break;
407 case R128_PM4_192PIO:
408 case R128_PM4_192BM:
409 dev_priv->cce_fifo_size = 192;
410 break;
411 case R128_PM4_128PIO_64INDBM:
412 case R128_PM4_128BM_64INDBM:
413 dev_priv->cce_fifo_size = 128;
414 break;
415 case R128_PM4_64PIO_128INDBM:
416 case R128_PM4_64BM_128INDBM:
417 case R128_PM4_64PIO_64VCBM_64INDBM:
418 case R128_PM4_64BM_64VCBM_64INDBM:
419 case R128_PM4_64PIO_64VCPIO_64INDPIO:
420 dev_priv->cce_fifo_size = 64;
421 break;
422 }
423
424 switch (init->fb_bpp) {
425 case 16:
426 dev_priv->color_fmt = R128_DATATYPE_RGB565;
427 break;
428 case 32:
429 default:
430 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
431 break;
432 }
433 dev_priv->front_offset = init->front_offset;
434 dev_priv->front_pitch = init->front_pitch;
435 dev_priv->back_offset = init->back_offset;
436 dev_priv->back_pitch = init->back_pitch;
437
438 switch (init->depth_bpp) {
439 case 16:
440 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
441 break;
442 case 24:
443 case 32:
444 default:
445 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
446 break;
447 }
448 dev_priv->depth_offset = init->depth_offset;
449 dev_priv->depth_pitch = init->depth_pitch;
450 dev_priv->span_offset = init->span_offset;
451
452 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
453 (dev_priv->front_offset >> 5));
454 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
455 (dev_priv->back_offset >> 5));
456 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
457 (dev_priv->depth_offset >> 5) |
458 R128_DST_TILE);
459 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
460 (dev_priv->span_offset >> 5));
461
462 dev_priv->sarea = drm_getsarea(dev);
463 if (!dev_priv->sarea) {
464 DRM_ERROR("could not find sarea!\n");
465 dev->dev_private = (void *)dev_priv;
466 r128_do_cleanup_cce(dev);
467 return -EINVAL;
468 }
469
470 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
471 if (!dev_priv->mmio) {
472 DRM_ERROR("could not find mmio region!\n");
473 dev->dev_private = (void *)dev_priv;
474 r128_do_cleanup_cce(dev);
475 return -EINVAL;
476 }
477 dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);
478 if (!dev_priv->cce_ring) {
479 DRM_ERROR("could not find cce ring region!\n");
480 dev->dev_private = (void *)dev_priv;
481 r128_do_cleanup_cce(dev);
482 return -EINVAL;
483 }
484 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
485 if (!dev_priv->ring_rptr) {
486 DRM_ERROR("could not find ring read pointer!\n");
487 dev->dev_private = (void *)dev_priv;
488 r128_do_cleanup_cce(dev);
489 return -EINVAL;
490 }
491 dev->agp_buffer_token = init->buffers_offset;
492 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
493 if (!dev->agp_buffer_map) {
494 DRM_ERROR("could not find dma buffer region!\n");
495 dev->dev_private = (void *)dev_priv;
496 r128_do_cleanup_cce(dev);
497 return -EINVAL;
498 }
499
500 if (!dev_priv->is_pci) {
501 dev_priv->agp_textures =
502 drm_core_findmap(dev, init->agp_textures_offset);
503 if (!dev_priv->agp_textures) {
504 DRM_ERROR("could not find agp texture region!\n");
505 dev->dev_private = (void *)dev_priv;
506 r128_do_cleanup_cce(dev);
507 return -EINVAL;
508 }
509 }
510
511 dev_priv->sarea_priv =
512 (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
513 init->sarea_priv_offset);
514
515 #if __OS_HAS_AGP
516 if (!dev_priv->is_pci) {
517 drm_core_ioremap_wc(dev_priv->cce_ring, dev);
518 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
519 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
520 if (!dev_priv->cce_ring->handle ||
521 !dev_priv->ring_rptr->handle ||
522 !dev->agp_buffer_map->handle) {
523 DRM_ERROR("Could not ioremap agp regions!\n");
524 dev->dev_private = (void *)dev_priv;
525 r128_do_cleanup_cce(dev);
526 return -ENOMEM;
527 }
528 } else
529 #endif
530 {
531 dev_priv->cce_ring->handle =
532 (void *)(unsigned long)dev_priv->cce_ring->offset;
533 dev_priv->ring_rptr->handle =
534 (void *)(unsigned long)dev_priv->ring_rptr->offset;
535 dev->agp_buffer_map->handle =
536 (void *)(unsigned long)dev->agp_buffer_map->offset;
537 }
538
539 #if __OS_HAS_AGP
540 if (!dev_priv->is_pci)
541 dev_priv->cce_buffers_offset = dev->agp->base;
542 else
543 #endif
544 dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual;
545
546 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
547 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
548 + init->ring_size / sizeof(u32));
549 dev_priv->ring.size = init->ring_size;
550 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
551
552 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
553
554 dev_priv->ring.high_mark = 128;
555
556 dev_priv->sarea_priv->last_frame = 0;
557 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
558
559 dev_priv->sarea_priv->last_dispatch = 0;
560 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
561
562 #if __OS_HAS_AGP
563 if (dev_priv->is_pci) {
564 #endif
565 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
566 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
567 dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;
568 dev_priv->gart_info.addr = NULL;
569 dev_priv->gart_info.bus_addr = 0;
570 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
571 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
572 DRM_ERROR("failed to init PCI GART!\n");
573 dev->dev_private = (void *)dev_priv;
574 r128_do_cleanup_cce(dev);
575 return -ENOMEM;
576 }
577 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);
578 #if __OS_HAS_AGP
579 }
580 #endif
581
582 r128_cce_init_ring_buffer(dev, dev_priv);
583 r128_cce_load_microcode(dev_priv);
584
585 dev->dev_private = (void *)dev_priv;
586
587 r128_do_engine_reset(dev);
588
589 return 0;
590 }
591
592 int r128_do_cleanup_cce(struct drm_device * dev)
593 {
594
595 /* Make sure interrupts are disabled here because the uninstall ioctl
596 * may not have been called from userspace and after dev_private
597 * is freed, it's too late.
598 */
599 if (dev->irq_enabled)
600 drm_irq_uninstall(dev);
601
602 if (dev->dev_private) {
603 drm_r128_private_t *dev_priv = dev->dev_private;
604
605 #if __OS_HAS_AGP
606 if (!dev_priv->is_pci) {
607 if (dev_priv->cce_ring != NULL)
608 drm_core_ioremapfree(dev_priv->cce_ring, dev);
609 if (dev_priv->ring_rptr != NULL)
610 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
611 if (dev->agp_buffer_map != NULL) {
612 drm_core_ioremapfree(dev->agp_buffer_map, dev);
613 dev->agp_buffer_map = NULL;
614 }
615 } else
616 #endif
617 {
618 if (dev_priv->gart_info.bus_addr)
619 if (!drm_ati_pcigart_cleanup(dev,
620 &dev_priv->gart_info))
621 DRM_ERROR
622 ("failed to cleanup PCI GART!\n");
623 }
624
625 kfree(dev->dev_private);
626 dev->dev_private = NULL;
627 }
628
629 return 0;
630 }
631
632 int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
633 {
634 drm_r128_init_t *init = data;
635
636 DRM_DEBUG("\n");
637
638 LOCK_TEST_WITH_RETURN(dev, file_priv);
639
640 switch (init->func) {
641 case R128_INIT_CCE:
642 return r128_do_init_cce(dev, init);
643 case R128_CLEANUP_CCE:
644 return r128_do_cleanup_cce(dev);
645 }
646
647 return -EINVAL;
648 }
649
650 int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
651 {
652 drm_r128_private_t *dev_priv = dev->dev_private;
653 DRM_DEBUG("\n");
654
655 LOCK_TEST_WITH_RETURN(dev, file_priv);
656
657 DEV_INIT_TEST_WITH_RETURN(dev_priv);
658
659 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
660 DRM_DEBUG("while CCE running\n");
661 return 0;
662 }
663
664 r128_do_cce_start(dev_priv);
665
666 return 0;
667 }
668
669 /* Stop the CCE. The engine must have been idled before calling this
670 * routine.
671 */
672 int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
673 {
674 drm_r128_private_t *dev_priv = dev->dev_private;
675 drm_r128_cce_stop_t *stop = data;
676 int ret;
677 DRM_DEBUG("\n");
678
679 LOCK_TEST_WITH_RETURN(dev, file_priv);
680
681 DEV_INIT_TEST_WITH_RETURN(dev_priv);
682
683 /* Flush any pending CCE commands. This ensures any outstanding
684 * commands are exectuted by the engine before we turn it off.
685 */
686 if (stop->flush) {
687 r128_do_cce_flush(dev_priv);
688 }
689
690 /* If we fail to make the engine go idle, we return an error
691 * code so that the DRM ioctl wrapper can try again.
692 */
693 if (stop->idle) {
694 ret = r128_do_cce_idle(dev_priv);
695 if (ret)
696 return ret;
697 }
698
699 /* Finally, we can turn off the CCE. If the engine isn't idle,
700 * we will get some dropped triangles as they won't be fully
701 * rendered before the CCE is shut down.
702 */
703 r128_do_cce_stop(dev_priv);
704
705 /* Reset the engine */
706 r128_do_engine_reset(dev);
707
708 return 0;
709 }
710
711 /* Just reset the CCE ring. Called as part of an X Server engine reset.
712 */
713 int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
714 {
715 drm_r128_private_t *dev_priv = dev->dev_private;
716 DRM_DEBUG("\n");
717
718 LOCK_TEST_WITH_RETURN(dev, file_priv);
719
720 DEV_INIT_TEST_WITH_RETURN(dev_priv);
721
722 r128_do_cce_reset(dev_priv);
723
724 /* The CCE is no longer running after an engine reset */
725 dev_priv->cce_running = 0;
726
727 return 0;
728 }
729
730 int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
731 {
732 drm_r128_private_t *dev_priv = dev->dev_private;
733 DRM_DEBUG("\n");
734
735 LOCK_TEST_WITH_RETURN(dev, file_priv);
736
737 DEV_INIT_TEST_WITH_RETURN(dev_priv);
738
739 if (dev_priv->cce_running) {
740 r128_do_cce_flush(dev_priv);
741 }
742
743 return r128_do_cce_idle(dev_priv);
744 }
745
746 int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
747 {
748 DRM_DEBUG("\n");
749
750 LOCK_TEST_WITH_RETURN(dev, file_priv);
751
752 DEV_INIT_TEST_WITH_RETURN(dev->dev_private);
753
754 return r128_do_engine_reset(dev);
755 }
756
757 int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
758 {
759 return -EINVAL;
760 }
761
762 /* ================================================================
763 * Freelist management
764 */
765 #define R128_BUFFER_USED 0xffffffff
766 #define R128_BUFFER_FREE 0
767
768 #if 0
769 static int r128_freelist_init(struct drm_device * dev)
770 {
771 struct drm_device_dma *dma = dev->dma;
772 drm_r128_private_t *dev_priv = dev->dev_private;
773 struct drm_buf *buf;
774 drm_r128_buf_priv_t *buf_priv;
775 drm_r128_freelist_t *entry;
776 int i;
777
778 dev_priv->head = kzalloc(sizeof(drm_r128_freelist_t), GFP_KERNEL);
779 if (dev_priv->head == NULL)
780 return -ENOMEM;
781
782 dev_priv->head->age = R128_BUFFER_USED;
783
784 for (i = 0; i < dma->buf_count; i++) {
785 buf = dma->buflist[i];
786 buf_priv = buf->dev_private;
787
788 entry = kmalloc(sizeof(drm_r128_freelist_t), GFP_KERNEL);
789 if (!entry)
790 return -ENOMEM;
791
792 entry->age = R128_BUFFER_FREE;
793 entry->buf = buf;
794 entry->prev = dev_priv->head;
795 entry->next = dev_priv->head->next;
796 if (!entry->next)
797 dev_priv->tail = entry;
798
799 buf_priv->discard = 0;
800 buf_priv->dispatched = 0;
801 buf_priv->list_entry = entry;
802
803 dev_priv->head->next = entry;
804
805 if (dev_priv->head->next)
806 dev_priv->head->next->prev = entry;
807 }
808
809 return 0;
810
811 }
812 #endif
813
814 static struct drm_buf *r128_freelist_get(struct drm_device * dev)
815 {
816 struct drm_device_dma *dma = dev->dma;
817 drm_r128_private_t *dev_priv = dev->dev_private;
818 drm_r128_buf_priv_t *buf_priv;
819 struct drm_buf *buf;
820 int i, t;
821
822 /* FIXME: Optimize -- use freelist code */
823
824 for (i = 0; i < dma->buf_count; i++) {
825 buf = dma->buflist[i];
826 buf_priv = buf->dev_private;
827 if (!buf->file_priv)
828 return buf;
829 }
830
831 for (t = 0; t < dev_priv->usec_timeout; t++) {
832 u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
833
834 for (i = 0; i < dma->buf_count; i++) {
835 buf = dma->buflist[i];
836 buf_priv = buf->dev_private;
837 if (buf->pending && buf_priv->age <= done_age) {
838 /* The buffer has been processed, so it
839 * can now be used.
840 */
841 buf->pending = 0;
842 return buf;
843 }
844 }
845 DRM_UDELAY(1);
846 }
847
848 DRM_DEBUG("returning NULL!\n");
849 return NULL;
850 }
851
852 void r128_freelist_reset(struct drm_device * dev)
853 {
854 struct drm_device_dma *dma = dev->dma;
855 int i;
856
857 for (i = 0; i < dma->buf_count; i++) {
858 struct drm_buf *buf = dma->buflist[i];
859 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
860 buf_priv->age = 0;
861 }
862 }
863
864 /* ================================================================
865 * CCE command submission
866 */
867
868 int r128_wait_ring(drm_r128_private_t * dev_priv, int n)
869 {
870 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
871 int i;
872
873 for (i = 0; i < dev_priv->usec_timeout; i++) {
874 r128_update_ring_snapshot(dev_priv);
875 if (ring->space >= n)
876 return 0;
877 DRM_UDELAY(1);
878 }
879
880 /* FIXME: This is being ignored... */
881 DRM_ERROR("failed!\n");
882 return -EBUSY;
883 }
884
885 static int r128_cce_get_buffers(struct drm_device * dev,
886 struct drm_file *file_priv,
887 struct drm_dma * d)
888 {
889 int i;
890 struct drm_buf *buf;
891
892 for (i = d->granted_count; i < d->request_count; i++) {
893 buf = r128_freelist_get(dev);
894 if (!buf)
895 return -EAGAIN;
896
897 buf->file_priv = file_priv;
898
899 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
900 sizeof(buf->idx)))
901 return -EFAULT;
902 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
903 sizeof(buf->total)))
904 return -EFAULT;
905
906 d->granted_count++;
907 }
908 return 0;
909 }
910
911 int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
912 {
913 struct drm_device_dma *dma = dev->dma;
914 int ret = 0;
915 struct drm_dma *d = data;
916
917 LOCK_TEST_WITH_RETURN(dev, file_priv);
918
919 /* Please don't send us buffers.
920 */
921 if (d->send_count != 0) {
922 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
923 DRM_CURRENTPID, d->send_count);
924 return -EINVAL;
925 }
926
927 /* We'll send you buffers.
928 */
929 if (d->request_count < 0 || d->request_count > dma->buf_count) {
930 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
931 DRM_CURRENTPID, d->request_count, dma->buf_count);
932 return -EINVAL;
933 }
934
935 d->granted_count = 0;
936
937 if (d->request_count) {
938 ret = r128_cce_get_buffers(dev, file_priv, d);
939 }
940
941 return ret;
942 }
943
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