1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28 #include <linux/i2c.h>
29 #include <linux/delay.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "drm_crtc.h"
33 #include "intel_drv.h"
34 #include "drm_edid.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "intel_sdvo_regs.h"
38
39 #undef SDVO_DEBUG
40 #define I915_SDVO "i915_sdvo"
41 struct intel_sdvo_priv {
42 u8 slave_addr;
43
44 /* Register for the SDVO device: SDVOB or SDVOC */
45 int output_device;
46
47 /* Active outputs controlled by this SDVO output */
48 uint16_t controlled_output;
49
50 /*
51 * Capabilities of the SDVO device returned by
52 * i830_sdvo_get_capabilities()
53 */
54 struct intel_sdvo_caps caps;
55
56 /* Pixel clock limitations reported by the SDVO device, in kHz */
57 int pixel_clock_min, pixel_clock_max;
58
59 /*
60 * For multiple function SDVO device,
61 * this is for current attached outputs.
62 */
63 uint16_t attached_output;
64
65 /**
66 * This is set if we're going to treat the device as TV-out.
67 *
68 * While we have these nice friendly flags for output types that ought
69 * to decide this for us, the S-Video output on our HDMI+S-Video card
70 * shows up as RGB1 (VGA).
71 */
72 bool is_tv;
73
74 /**
75 * This is set if we treat the device as HDMI, instead of DVI.
76 */
77 bool is_hdmi;
78
79 /**
80 * This is set if we detect output of sdvo device as LVDS.
81 */
82 bool is_lvds;
83
84 /**
85 * This is sdvo flags for input timing.
86 */
87 uint8_t sdvo_flags;
88
89 /**
90 * This is sdvo fixed pannel mode pointer
91 */
92 struct drm_display_mode *sdvo_lvds_fixed_mode;
93
94 /**
95 * Returned SDTV resolutions allowed for the current format, if the
96 * device reported it.
97 */
98 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
99
100 /**
101 * Current selected TV format.
102 *
103 * This is stored in the same structure that's passed to the device, for
104 * convenience.
105 */
106 struct intel_sdvo_tv_format tv_format;
107
108 /*
109 * supported encoding mode, used to determine whether HDMI is
110 * supported
111 */
112 struct intel_sdvo_encode encode;
113
114 /* DDC bus used by this SDVO output */
115 uint8_t ddc_bus;
116
117 /* Mac mini hack -- use the same DDC as the analog connector */
118 struct i2c_adapter *analog_ddc_bus;
119
120 int save_sdvo_mult;
121 u16 save_active_outputs;
122 struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
123 struct intel_sdvo_dtd save_output_dtd[16];
124 u32 save_SDVOX;
125 };
126
127 static bool
128 intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags);
129
130 /**
131 * Writes the SDVOB or SDVOC with the given value, but always writes both
132 * SDVOB and SDVOC to work around apparent hardware issues (according to
133 * comments in the BIOS).
134 */
135 static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
136 {
137 struct drm_device *dev = intel_output->base.dev;
138 struct drm_i915_private *dev_priv = dev->dev_private;
139 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
140 u32 bval = val, cval = val;
141 int i;
142
143 if (sdvo_priv->output_device == SDVOB) {
144 cval = I915_READ(SDVOC);
145 } else {
146 bval = I915_READ(SDVOB);
147 }
148 /*
149 * Write the registers twice for luck. Sometimes,
150 * writing them only once doesn't appear to 'stick'.
151 * The BIOS does this too. Yay, magic
152 */
153 for (i = 0; i < 2; i++)
154 {
155 I915_WRITE(SDVOB, bval);
156 I915_READ(SDVOB);
157 I915_WRITE(SDVOC, cval);
158 I915_READ(SDVOC);
159 }
160 }
161
162 static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
163 u8 *ch)
164 {
165 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
166 u8 out_buf[2];
167 u8 buf[2];
168 int ret;
169
170 struct i2c_msg msgs[] = {
171 {
172 .addr = sdvo_priv->slave_addr >> 1,
173 .flags = 0,
174 .len = 1,
175 .buf = out_buf,
176 },
177 {
178 .addr = sdvo_priv->slave_addr >> 1,
179 .flags = I2C_M_RD,
180 .len = 1,
181 .buf = buf,
182 }
183 };
184
185 out_buf[0] = addr;
186 out_buf[1] = 0;
187
188 if ((ret = i2c_transfer(intel_output->i2c_bus, msgs, 2)) == 2)
189 {
190 *ch = buf[0];
191 return true;
192 }
193
194 DRM_DEBUG("i2c transfer returned %d\n", ret);
195 return false;
196 }
197
198 static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
199 u8 ch)
200 {
201 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
202 u8 out_buf[2];
203 struct i2c_msg msgs[] = {
204 {
205 .addr = sdvo_priv->slave_addr >> 1,
206 .flags = 0,
207 .len = 2,
208 .buf = out_buf,
209 }
210 };
211
212 out_buf[0] = addr;
213 out_buf[1] = ch;
214
215 if (i2c_transfer(intel_output->i2c_bus, msgs, 1) == 1)
216 {
217 return true;
218 }
219 return false;
220 }
221
222 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
223 /** Mapping of command numbers to names, for debug output */
224 static const struct _sdvo_cmd_name {
225 u8 cmd;
226 char *name;
227 } sdvo_cmd_names[] = {
228 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
229 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
230 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
231 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
232 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
233 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
234 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
235 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
236 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
237 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
238 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
239 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
240 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
241 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
242 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
243 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
244 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
245 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
246 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
247 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
248 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
249 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
250 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
251 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
252 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
253 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
254 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
255 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
256 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
257 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
258 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
259 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
260 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
261 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
262 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
263 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
264 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
265 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
266 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
267 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
268 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
269 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
270 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
271 /* HDMI op code */
272 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
273 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
274 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
275 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
276 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
277 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
278 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
279 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
280 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
281 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
282 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
283 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
284 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
285 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
286 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
292 };
293
294 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
295 #define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
296
297 #ifdef SDVO_DEBUG
298 static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
299 void *args, int args_len)
300 {
301 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
302 int i;
303
304 DRM_DEBUG_KMS(I915_SDVO, "%s: W: %02X ",
305 SDVO_NAME(sdvo_priv), cmd);
306 for (i = 0; i < args_len; i++)
307 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
308 for (; i < 8; i++)
309 DRM_LOG_KMS(" ");
310 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
311 if (cmd == sdvo_cmd_names[i].cmd) {
312 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
313 break;
314 }
315 }
316 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
317 DRM_LOG_KMS("(%02X)", cmd);
318 DRM_LOG_KMS("\n");
319 }
320 #else
321 #define intel_sdvo_debug_write(o, c, a, l)
322 #endif
323
324 static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
325 void *args, int args_len)
326 {
327 int i;
328
329 intel_sdvo_debug_write(intel_output, cmd, args, args_len);
330
331 for (i = 0; i < args_len; i++) {
332 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
333 ((u8*)args)[i]);
334 }
335
336 intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
337 }
338
339 #ifdef SDVO_DEBUG
340 static const char *cmd_status_names[] = {
341 "Power on",
342 "Success",
343 "Not supported",
344 "Invalid arg",
345 "Pending",
346 "Target not specified",
347 "Scaling not supported"
348 };
349
350 static void intel_sdvo_debug_response(struct intel_output *intel_output,
351 void *response, int response_len,
352 u8 status)
353 {
354 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
355 int i;
356
357 DRM_DEBUG_KMS(I915_SDVO, "%s: R: ", SDVO_NAME(sdvo_priv));
358 for (i = 0; i < response_len; i++)
359 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
360 for (; i < 8; i++)
361 DRM_LOG_KMS(" ");
362 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
363 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
364 else
365 DRM_LOG_KMS("(??? %d)", status);
366 DRM_LOG_KMS("\n");
367 }
368 #else
369 #define intel_sdvo_debug_response(o, r, l, s)
370 #endif
371
372 static u8 intel_sdvo_read_response(struct intel_output *intel_output,
373 void *response, int response_len)
374 {
375 int i;
376 u8 status;
377 u8 retry = 50;
378
379 while (retry--) {
380 /* Read the command response */
381 for (i = 0; i < response_len; i++) {
382 intel_sdvo_read_byte(intel_output,
383 SDVO_I2C_RETURN_0 + i,
384 &((u8 *)response)[i]);
385 }
386
387 /* read the return status */
388 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
389 &status);
390
391 intel_sdvo_debug_response(intel_output, response, response_len,
392 status);
393 if (status != SDVO_CMD_STATUS_PENDING)
394 return status;
395
396 mdelay(50);
397 }
398
399 return status;
400 }
401
402 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
403 {
404 if (mode->clock >= 100000)
405 return 1;
406 else if (mode->clock >= 50000)
407 return 2;
408 else
409 return 4;
410 }
411
412 /**
413 * Don't check status code from this as it switches the bus back to the
414 * SDVO chips which defeats the purpose of doing a bus switch in the first
415 * place.
416 */
417 static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
418 u8 target)
419 {
420 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
421 }
422
423 static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
424 {
425 struct intel_sdvo_set_target_input_args targets = {0};
426 u8 status;
427
428 if (target_0 && target_1)
429 return SDVO_CMD_STATUS_NOTSUPP;
430
431 if (target_1)
432 targets.target_1 = 1;
433
434 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
435 sizeof(targets));
436
437 status = intel_sdvo_read_response(intel_output, NULL, 0);
438
439 return (status == SDVO_CMD_STATUS_SUCCESS);
440 }
441
442 /**
443 * Return whether each input is trained.
444 *
445 * This function is making an assumption about the layout of the response,
446 * which should be checked against the docs.
447 */
448 static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
449 {
450 struct intel_sdvo_get_trained_inputs_response response;
451 u8 status;
452
453 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
454 status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
455 if (status != SDVO_CMD_STATUS_SUCCESS)
456 return false;
457
458 *input_1 = response.input0_trained;
459 *input_2 = response.input1_trained;
460 return true;
461 }
462
463 static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
464 u16 *outputs)
465 {
466 u8 status;
467
468 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
469 status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
470
471 return (status == SDVO_CMD_STATUS_SUCCESS);
472 }
473
474 static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
475 u16 outputs)
476 {
477 u8 status;
478
479 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
480 sizeof(outputs));
481 status = intel_sdvo_read_response(intel_output, NULL, 0);
482 return (status == SDVO_CMD_STATUS_SUCCESS);
483 }
484
485 static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
486 int mode)
487 {
488 u8 status, state = SDVO_ENCODER_STATE_ON;
489
490 switch (mode) {
491 case DRM_MODE_DPMS_ON:
492 state = SDVO_ENCODER_STATE_ON;
493 break;
494 case DRM_MODE_DPMS_STANDBY:
495 state = SDVO_ENCODER_STATE_STANDBY;
496 break;
497 case DRM_MODE_DPMS_SUSPEND:
498 state = SDVO_ENCODER_STATE_SUSPEND;
499 break;
500 case DRM_MODE_DPMS_OFF:
501 state = SDVO_ENCODER_STATE_OFF;
502 break;
503 }
504
505 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
506 sizeof(state));
507 status = intel_sdvo_read_response(intel_output, NULL, 0);
508
509 return (status == SDVO_CMD_STATUS_SUCCESS);
510 }
511
512 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
513 int *clock_min,
514 int *clock_max)
515 {
516 struct intel_sdvo_pixel_clock_range clocks;
517 u8 status;
518
519 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
520 NULL, 0);
521
522 status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
523
524 if (status != SDVO_CMD_STATUS_SUCCESS)
525 return false;
526
527 /* Convert the values from units of 10 kHz to kHz. */
528 *clock_min = clocks.min * 10;
529 *clock_max = clocks.max * 10;
530
531 return true;
532 }
533
534 static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
535 u16 outputs)
536 {
537 u8 status;
538
539 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
540 sizeof(outputs));
541
542 status = intel_sdvo_read_response(intel_output, NULL, 0);
543 return (status == SDVO_CMD_STATUS_SUCCESS);
544 }
545
546 static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
547 struct intel_sdvo_dtd *dtd)
548 {
549 u8 status;
550
551 intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
552 status = intel_sdvo_read_response(intel_output, &dtd->part1,
553 sizeof(dtd->part1));
554 if (status != SDVO_CMD_STATUS_SUCCESS)
555 return false;
556
557 intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
558 status = intel_sdvo_read_response(intel_output, &dtd->part2,
559 sizeof(dtd->part2));
560 if (status != SDVO_CMD_STATUS_SUCCESS)
561 return false;
562
563 return true;
564 }
565
566 static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
567 struct intel_sdvo_dtd *dtd)
568 {
569 return intel_sdvo_get_timing(intel_output,
570 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
571 }
572
573 static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
574 struct intel_sdvo_dtd *dtd)
575 {
576 return intel_sdvo_get_timing(intel_output,
577 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
578 }
579
580 static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
581 struct intel_sdvo_dtd *dtd)
582 {
583 u8 status;
584
585 intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
586 status = intel_sdvo_read_response(intel_output, NULL, 0);
587 if (status != SDVO_CMD_STATUS_SUCCESS)
588 return false;
589
590 intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
591 status = intel_sdvo_read_response(intel_output, NULL, 0);
592 if (status != SDVO_CMD_STATUS_SUCCESS)
593 return false;
594
595 return true;
596 }
597
598 static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
599 struct intel_sdvo_dtd *dtd)
600 {
601 return intel_sdvo_set_timing(intel_output,
602 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
603 }
604
605 static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
606 struct intel_sdvo_dtd *dtd)
607 {
608 return intel_sdvo_set_timing(intel_output,
609 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
610 }
611
612 static bool
613 intel_sdvo_create_preferred_input_timing(struct intel_output *output,
614 uint16_t clock,
615 uint16_t width,
616 uint16_t height)
617 {
618 struct intel_sdvo_preferred_input_timing_args args;
619 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
620 uint8_t status;
621
622 memset(&args, 0, sizeof(args));
623 args.clock = clock;
624 args.width = width;
625 args.height = height;
626 args.interlace = 0;
627
628 if (sdvo_priv->is_lvds &&
629 (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
630 sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
631 args.scaled = 1;
632
633 intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
634 &args, sizeof(args));
635 status = intel_sdvo_read_response(output, NULL, 0);
636 if (status != SDVO_CMD_STATUS_SUCCESS)
637 return false;
638
639 return true;
640 }
641
642 static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
643 struct intel_sdvo_dtd *dtd)
644 {
645 bool status;
646
647 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
648 NULL, 0);
649
650 status = intel_sdvo_read_response(output, &dtd->part1,
651 sizeof(dtd->part1));
652 if (status != SDVO_CMD_STATUS_SUCCESS)
653 return false;
654
655 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
656 NULL, 0);
657
658 status = intel_sdvo_read_response(output, &dtd->part2,
659 sizeof(dtd->part2));
660 if (status != SDVO_CMD_STATUS_SUCCESS)
661 return false;
662
663 return false;
664 }
665
666 static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
667 {
668 u8 response, status;
669
670 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
671 status = intel_sdvo_read_response(intel_output, &response, 1);
672
673 if (status != SDVO_CMD_STATUS_SUCCESS) {
674 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
675 return SDVO_CLOCK_RATE_MULT_1X;
676 } else {
677 DRM_DEBUG("Current clock rate multiplier: %d\n", response);
678 }
679
680 return response;
681 }
682
683 static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
684 {
685 u8 status;
686
687 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
688 status = intel_sdvo_read_response(intel_output, NULL, 0);
689 if (status != SDVO_CMD_STATUS_SUCCESS)
690 return false;
691
692 return true;
693 }
694
695 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
696 struct drm_display_mode *mode)
697 {
698 uint16_t width, height;
699 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
700 uint16_t h_sync_offset, v_sync_offset;
701
702 width = mode->crtc_hdisplay;
703 height = mode->crtc_vdisplay;
704
705 /* do some mode translations */
706 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
707 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
708
709 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
710 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
711
712 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
713 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
714
715 dtd->part1.clock = mode->clock / 10;
716 dtd->part1.h_active = width & 0xff;
717 dtd->part1.h_blank = h_blank_len & 0xff;
718 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
719 ((h_blank_len >> 8) & 0xf);
720 dtd->part1.v_active = height & 0xff;
721 dtd->part1.v_blank = v_blank_len & 0xff;
722 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
723 ((v_blank_len >> 8) & 0xf);
724
725 dtd->part2.h_sync_off = h_sync_offset & 0xff;
726 dtd->part2.h_sync_width = h_sync_len & 0xff;
727 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
728 (v_sync_len & 0xf);
729 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
730 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
731 ((v_sync_len & 0x30) >> 4);
732
733 dtd->part2.dtd_flags = 0x18;
734 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
735 dtd->part2.dtd_flags |= 0x2;
736 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
737 dtd->part2.dtd_flags |= 0x4;
738
739 dtd->part2.sdvo_flags = 0;
740 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
741 dtd->part2.reserved = 0;
742 }
743
744 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
745 struct intel_sdvo_dtd *dtd)
746 {
747 mode->hdisplay = dtd->part1.h_active;
748 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
749 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
750 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
751 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
752 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
753 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
754 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
755
756 mode->vdisplay = dtd->part1.v_active;
757 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
758 mode->vsync_start = mode->vdisplay;
759 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
760 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
761 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
762 mode->vsync_end = mode->vsync_start +
763 (dtd->part2.v_sync_off_width & 0xf);
764 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
765 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
766 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
767
768 mode->clock = dtd->part1.clock * 10;
769
770 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
771 if (dtd->part2.dtd_flags & 0x2)
772 mode->flags |= DRM_MODE_FLAG_PHSYNC;
773 if (dtd->part2.dtd_flags & 0x4)
774 mode->flags |= DRM_MODE_FLAG_PVSYNC;
775 }
776
777 static bool intel_sdvo_get_supp_encode(struct intel_output *output,
778 struct intel_sdvo_encode *encode)
779 {
780 uint8_t status;
781
782 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
783 status = intel_sdvo_read_response(output, encode, sizeof(*encode));
784 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
785 memset(encode, 0, sizeof(*encode));
786 return false;
787 }
788
789 return true;
790 }
791
792 static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
793 {
794 uint8_t status;
795
796 intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
797 status = intel_sdvo_read_response(output, NULL, 0);
798
799 return (status == SDVO_CMD_STATUS_SUCCESS);
800 }
801
802 static bool intel_sdvo_set_colorimetry(struct intel_output *output,
803 uint8_t mode)
804 {
805 uint8_t status;
806
807 intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
808 status = intel_sdvo_read_response(output, NULL, 0);
809
810 return (status == SDVO_CMD_STATUS_SUCCESS);
811 }
812
813 #if 0
814 static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
815 {
816 int i, j;
817 uint8_t set_buf_index[2];
818 uint8_t av_split;
819 uint8_t buf_size;
820 uint8_t buf[48];
821 uint8_t *pos;
822
823 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
824 intel_sdvo_read_response(output, &av_split, 1);
825
826 for (i = 0; i <= av_split; i++) {
827 set_buf_index[0] = i; set_buf_index[1] = 0;
828 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
829 set_buf_index, 2);
830 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
831 intel_sdvo_read_response(output, &buf_size, 1);
832
833 pos = buf;
834 for (j = 0; j <= buf_size; j += 8) {
835 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
836 NULL, 0);
837 intel_sdvo_read_response(output, pos, 8);
838 pos += 8;
839 }
840 }
841 }
842 #endif
843
844 static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
845 uint8_t *data, int8_t size, uint8_t tx_rate)
846 {
847 uint8_t set_buf_index[2];
848
849 set_buf_index[0] = index;
850 set_buf_index[1] = 0;
851
852 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
853
854 for (; size > 0; size -= 8) {
855 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
856 data += 8;
857 }
858
859 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
860 }
861
862 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
863 {
864 uint8_t csum = 0;
865 int i;
866
867 for (i = 0; i < size; i++)
868 csum += data[i];
869
870 return 0x100 - csum;
871 }
872
873 #define DIP_TYPE_AVI 0x82
874 #define DIP_VERSION_AVI 0x2
875 #define DIP_LEN_AVI 13
876
877 struct dip_infoframe {
878 uint8_t type;
879 uint8_t version;
880 uint8_t len;
881 uint8_t checksum;
882 union {
883 struct {
884 /* Packet Byte #1 */
885 uint8_t S:2;
886 uint8_t B:2;
887 uint8_t A:1;
888 uint8_t Y:2;
889 uint8_t rsvd1:1;
890 /* Packet Byte #2 */
891 uint8_t R:4;
892 uint8_t M:2;
893 uint8_t C:2;
894 /* Packet Byte #3 */
895 uint8_t SC:2;
896 uint8_t Q:2;
897 uint8_t EC:3;
898 uint8_t ITC:1;
899 /* Packet Byte #4 */
900 uint8_t VIC:7;
901 uint8_t rsvd2:1;
902 /* Packet Byte #5 */
903 uint8_t PR:4;
904 uint8_t rsvd3:4;
905 /* Packet Byte #6~13 */
906 uint16_t top_bar_end;
907 uint16_t bottom_bar_start;
908 uint16_t left_bar_end;
909 uint16_t right_bar_start;
910 } avi;
911 struct {
912 /* Packet Byte #1 */
913 uint8_t channel_count:3;
914 uint8_t rsvd1:1;
915 uint8_t coding_type:4;
916 /* Packet Byte #2 */
917 uint8_t sample_size:2; /* SS0, SS1 */
918 uint8_t sample_frequency:3;
919 uint8_t rsvd2:3;
920 /* Packet Byte #3 */
921 uint8_t coding_type_private:5;
922 uint8_t rsvd3:3;
923 /* Packet Byte #4 */
924 uint8_t channel_allocation;
925 /* Packet Byte #5 */
926 uint8_t rsvd4:3;
927 uint8_t level_shift:4;
928 uint8_t downmix_inhibit:1;
929 } audio;
930 uint8_t payload[28];
931 } __attribute__ ((packed)) u;
932 } __attribute__((packed));
933
934 static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
935 struct drm_display_mode * mode)
936 {
937 struct dip_infoframe avi_if = {
938 .type = DIP_TYPE_AVI,
939 .version = DIP_VERSION_AVI,
940 .len = DIP_LEN_AVI,
941 };
942
943 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
944 4 + avi_if.len);
945 intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
946 SDVO_HBUF_TX_VSYNC);
947 }
948
949 static void intel_sdvo_set_tv_format(struct intel_output *output)
950 {
951 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
952 struct intel_sdvo_tv_format *format, unset;
953 u8 status;
954
955 format = &sdvo_priv->tv_format;
956 memset(&unset, 0, sizeof(unset));
957 if (memcmp(format, &unset, sizeof(*format))) {
958 DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n",
959 SDVO_NAME(sdvo_priv));
960 format->ntsc_m = 1;
961 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format,
962 sizeof(*format));
963 status = intel_sdvo_read_response(output, NULL, 0);
964 if (status != SDVO_CMD_STATUS_SUCCESS)
965 DRM_DEBUG("%s: Failed to set TV format\n",
966 SDVO_NAME(sdvo_priv));
967 }
968 }
969
970 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
971 struct drm_display_mode *mode,
972 struct drm_display_mode *adjusted_mode)
973 {
974 struct intel_output *output = enc_to_intel_output(encoder);
975 struct intel_sdvo_priv *dev_priv = output->dev_priv;
976
977 if (dev_priv->is_tv) {
978 struct intel_sdvo_dtd output_dtd;
979 bool success;
980
981 /* We need to construct preferred input timings based on our
982 * output timings. To do that, we have to set the output
983 * timings, even though this isn't really the right place in
984 * the sequence to do it. Oh well.
985 */
986
987
988 /* Set output timings */
989 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
990 intel_sdvo_set_target_output(output,
991 dev_priv->controlled_output);
992 intel_sdvo_set_output_timing(output, &output_dtd);
993
994 /* Set the input timing to the screen. Assume always input 0. */
995 intel_sdvo_set_target_input(output, true, false);
996
997
998 success = intel_sdvo_create_preferred_input_timing(output,
999 mode->clock / 10,
1000 mode->hdisplay,
1001 mode->vdisplay);
1002 if (success) {
1003 struct intel_sdvo_dtd input_dtd;
1004
1005 intel_sdvo_get_preferred_input_timing(output,
1006 &input_dtd);
1007 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1008 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1009
1010 drm_mode_set_crtcinfo(adjusted_mode, 0);
1011
1012 mode->clock = adjusted_mode->clock;
1013
1014 adjusted_mode->clock *=
1015 intel_sdvo_get_pixel_multiplier(mode);
1016 } else {
1017 return false;
1018 }
1019 } else if (dev_priv->is_lvds) {
1020 struct intel_sdvo_dtd output_dtd;
1021 bool success;
1022
1023 drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
1024 /* Set output timings */
1025 intel_sdvo_get_dtd_from_mode(&output_dtd,
1026 dev_priv->sdvo_lvds_fixed_mode);
1027
1028 intel_sdvo_set_target_output(output,
1029 dev_priv->controlled_output);
1030 intel_sdvo_set_output_timing(output, &output_dtd);
1031
1032 /* Set the input timing to the screen. Assume always input 0. */
1033 intel_sdvo_set_target_input(output, true, false);
1034
1035
1036 success = intel_sdvo_create_preferred_input_timing(
1037 output,
1038 mode->clock / 10,
1039 mode->hdisplay,
1040 mode->vdisplay);
1041
1042 if (success) {
1043 struct intel_sdvo_dtd input_dtd;
1044
1045 intel_sdvo_get_preferred_input_timing(output,
1046 &input_dtd);
1047 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1048 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1049
1050 drm_mode_set_crtcinfo(adjusted_mode, 0);
1051
1052 mode->clock = adjusted_mode->clock;
1053
1054 adjusted_mode->clock *=
1055 intel_sdvo_get_pixel_multiplier(mode);
1056 } else {
1057 return false;
1058 }
1059
1060 } else {
1061 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1062 * SDVO device will be told of the multiplier during mode_set.
1063 */
1064 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1065 }
1066 return true;
1067 }
1068
1069 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1070 struct drm_display_mode *mode,
1071 struct drm_display_mode *adjusted_mode)
1072 {
1073 struct drm_device *dev = encoder->dev;
1074 struct drm_i915_private *dev_priv = dev->dev_private;
1075 struct drm_crtc *crtc = encoder->crtc;
1076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1077 struct intel_output *output = enc_to_intel_output(encoder);
1078 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1079 u32 sdvox = 0;
1080 int sdvo_pixel_multiply;
1081 struct intel_sdvo_in_out_map in_out;
1082 struct intel_sdvo_dtd input_dtd;
1083 u8 status;
1084
1085 if (!mode)
1086 return;
1087
1088 /* First, set the input mapping for the first input to our controlled
1089 * output. This is only correct if we're a single-input device, in
1090 * which case the first input is the output from the appropriate SDVO
1091 * channel on the motherboard. In a two-input device, the first input
1092 * will be SDVOB and the second SDVOC.
1093 */
1094 in_out.in0 = sdvo_priv->controlled_output;
1095 in_out.in1 = 0;
1096
1097 intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
1098 &in_out, sizeof(in_out));
1099 status = intel_sdvo_read_response(output, NULL, 0);
1100
1101 if (sdvo_priv->is_hdmi) {
1102 intel_sdvo_set_avi_infoframe(output, mode);
1103 sdvox |= SDVO_AUDIO_ENABLE;
1104 }
1105
1106 /* We have tried to get input timing in mode_fixup, and filled into
1107 adjusted_mode */
1108 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
1109 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1110 input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
1111 } else
1112 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1113
1114 /* If it's a TV, we already set the output timing in mode_fixup.
1115 * Otherwise, the output timing is equal to the input timing.
1116 */
1117 if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
1118 /* Set the output timing to the screen */
1119 intel_sdvo_set_target_output(output,
1120 sdvo_priv->controlled_output);
1121 intel_sdvo_set_output_timing(output, &input_dtd);
1122 }
1123
1124 /* Set the input timing to the screen. Assume always input 0. */
1125 intel_sdvo_set_target_input(output, true, false);
1126
1127 if (sdvo_priv->is_tv)
1128 intel_sdvo_set_tv_format(output);
1129
1130 /* We would like to use intel_sdvo_create_preferred_input_timing() to
1131 * provide the device with a timing it can support, if it supports that
1132 * feature. However, presumably we would need to adjust the CRTC to
1133 * output the preferred timing, and we don't support that currently.
1134 */
1135 #if 0
1136 success = intel_sdvo_create_preferred_input_timing(output, clock,
1137 width, height);
1138 if (success) {
1139 struct intel_sdvo_dtd *input_dtd;
1140
1141 intel_sdvo_get_preferred_input_timing(output, &input_dtd);
1142 intel_sdvo_set_input_timing(output, &input_dtd);
1143 }
1144 #else
1145 intel_sdvo_set_input_timing(output, &input_dtd);
1146 #endif
1147
1148 switch (intel_sdvo_get_pixel_multiplier(mode)) {
1149 case 1:
1150 intel_sdvo_set_clock_rate_mult(output,
1151 SDVO_CLOCK_RATE_MULT_1X);
1152 break;
1153 case 2:
1154 intel_sdvo_set_clock_rate_mult(output,
1155 SDVO_CLOCK_RATE_MULT_2X);
1156 break;
1157 case 4:
1158 intel_sdvo_set_clock_rate_mult(output,
1159 SDVO_CLOCK_RATE_MULT_4X);
1160 break;
1161 }
1162
1163 /* Set the SDVO control regs. */
1164 if (IS_I965G(dev)) {
1165 sdvox |= SDVO_BORDER_ENABLE |
1166 SDVO_VSYNC_ACTIVE_HIGH |
1167 SDVO_HSYNC_ACTIVE_HIGH;
1168 } else {
1169 sdvox |= I915_READ(sdvo_priv->output_device);
1170 switch (sdvo_priv->output_device) {
1171 case SDVOB:
1172 sdvox &= SDVOB_PRESERVE_MASK;
1173 break;
1174 case SDVOC:
1175 sdvox &= SDVOC_PRESERVE_MASK;
1176 break;
1177 }
1178 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1179 }
1180 if (intel_crtc->pipe == 1)
1181 sdvox |= SDVO_PIPE_B_SELECT;
1182
1183 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1184 if (IS_I965G(dev)) {
1185 /* done in crtc_mode_set as the dpll_md reg must be written early */
1186 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1187 /* done in crtc_mode_set as it lives inside the dpll register */
1188 } else {
1189 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1190 }
1191
1192 if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
1193 sdvox |= SDVO_STALL_SELECT;
1194 intel_sdvo_write_sdvox(output, sdvox);
1195 }
1196
1197 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1198 {
1199 struct drm_device *dev = encoder->dev;
1200 struct drm_i915_private *dev_priv = dev->dev_private;
1201 struct intel_output *intel_output = enc_to_intel_output(encoder);
1202 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1203 u32 temp;
1204
1205 if (mode != DRM_MODE_DPMS_ON) {
1206 intel_sdvo_set_active_outputs(intel_output, 0);
1207 if (0)
1208 intel_sdvo_set_encoder_power_state(intel_output, mode);
1209
1210 if (mode == DRM_MODE_DPMS_OFF) {
1211 temp = I915_READ(sdvo_priv->output_device);
1212 if ((temp & SDVO_ENABLE) != 0) {
1213 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
1214 }
1215 }
1216 } else {
1217 bool input1, input2;
1218 int i;
1219 u8 status;
1220
1221 temp = I915_READ(sdvo_priv->output_device);
1222 if ((temp & SDVO_ENABLE) == 0)
1223 intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
1224 for (i = 0; i < 2; i++)
1225 intel_wait_for_vblank(dev);
1226
1227 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
1228 &input2);
1229
1230
1231 /* Warn if the device reported failure to sync.
1232 * A lot of SDVO devices fail to notify of sync, but it's
1233 * a given it the status is a success, we succeeded.
1234 */
1235 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1236 DRM_DEBUG("First %s output reported failure to sync\n",
1237 SDVO_NAME(sdvo_priv));
1238 }
1239
1240 if (0)
1241 intel_sdvo_set_encoder_power_state(intel_output, mode);
1242 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
1243 }
1244 return;
1245 }
1246
1247 static void intel_sdvo_save(struct drm_connector *connector)
1248 {
1249 struct drm_device *dev = connector->dev;
1250 struct drm_i915_private *dev_priv = dev->dev_private;
1251 struct intel_output *intel_output = to_intel_output(connector);
1252 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1253 int o;
1254
1255 sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
1256 intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
1257
1258 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1259 intel_sdvo_set_target_input(intel_output, true, false);
1260 intel_sdvo_get_input_timing(intel_output,
1261 &sdvo_priv->save_input_dtd_1);
1262 }
1263
1264 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1265 intel_sdvo_set_target_input(intel_output, false, true);
1266 intel_sdvo_get_input_timing(intel_output,
1267 &sdvo_priv->save_input_dtd_2);
1268 }
1269
1270 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1271 {
1272 u16 this_output = (1 << o);
1273 if (sdvo_priv->caps.output_flags & this_output)
1274 {
1275 intel_sdvo_set_target_output(intel_output, this_output);
1276 intel_sdvo_get_output_timing(intel_output,
1277 &sdvo_priv->save_output_dtd[o]);
1278 }
1279 }
1280 if (sdvo_priv->is_tv) {
1281 /* XXX: Save TV format/enhancements. */
1282 }
1283
1284 sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
1285 }
1286
1287 static void intel_sdvo_restore(struct drm_connector *connector)
1288 {
1289 struct drm_device *dev = connector->dev;
1290 struct intel_output *intel_output = to_intel_output(connector);
1291 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1292 int o;
1293 int i;
1294 bool input1, input2;
1295 u8 status;
1296
1297 intel_sdvo_set_active_outputs(intel_output, 0);
1298
1299 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1300 {
1301 u16 this_output = (1 << o);
1302 if (sdvo_priv->caps.output_flags & this_output) {
1303 intel_sdvo_set_target_output(intel_output, this_output);
1304 intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
1305 }
1306 }
1307
1308 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1309 intel_sdvo_set_target_input(intel_output, true, false);
1310 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
1311 }
1312
1313 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1314 intel_sdvo_set_target_input(intel_output, false, true);
1315 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
1316 }
1317
1318 intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
1319
1320 if (sdvo_priv->is_tv) {
1321 /* XXX: Restore TV format/enhancements. */
1322 }
1323
1324 intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
1325
1326 if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1327 {
1328 for (i = 0; i < 2; i++)
1329 intel_wait_for_vblank(dev);
1330 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
1331 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1332 DRM_DEBUG("First %s output reported failure to sync\n",
1333 SDVO_NAME(sdvo_priv));
1334 }
1335
1336 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
1337 }
1338
1339 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1340 struct drm_display_mode *mode)
1341 {
1342 struct intel_output *intel_output = to_intel_output(connector);
1343 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1344
1345 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1346 return MODE_NO_DBLESCAN;
1347
1348 if (sdvo_priv->pixel_clock_min > mode->clock)
1349 return MODE_CLOCK_LOW;
1350
1351 if (sdvo_priv->pixel_clock_max < mode->clock)
1352 return MODE_CLOCK_HIGH;
1353
1354 if (sdvo_priv->is_lvds == true) {
1355 if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
1356 return MODE_PANEL;
1357
1358 if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
1359 return MODE_PANEL;
1360
1361 if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
1362 return MODE_PANEL;
1363 }
1364
1365 return MODE_OK;
1366 }
1367
1368 static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
1369 {
1370 u8 status;
1371
1372 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1373 status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
1374 if (status != SDVO_CMD_STATUS_SUCCESS)
1375 return false;
1376
1377 return true;
1378 }
1379
1380 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1381 {
1382 struct drm_connector *connector = NULL;
1383 struct intel_output *iout = NULL;
1384 struct intel_sdvo_priv *sdvo;
1385
1386 /* find the sdvo connector */
1387 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1388 iout = to_intel_output(connector);
1389
1390 if (iout->type != INTEL_OUTPUT_SDVO)
1391 continue;
1392
1393 sdvo = iout->dev_priv;
1394
1395 if (sdvo->output_device == SDVOB && sdvoB)
1396 return connector;
1397
1398 if (sdvo->output_device == SDVOC && !sdvoB)
1399 return connector;
1400
1401 }
1402
1403 return NULL;
1404 }
1405
1406 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1407 {
1408 u8 response[2];
1409 u8 status;
1410 struct intel_output *intel_output;
1411 DRM_DEBUG("\n");
1412
1413 if (!connector)
1414 return 0;
1415
1416 intel_output = to_intel_output(connector);
1417
1418 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1419 status = intel_sdvo_read_response(intel_output, &response, 2);
1420
1421 if (response[0] !=0)
1422 return 1;
1423
1424 return 0;
1425 }
1426
1427 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1428 {
1429 u8 response[2];
1430 u8 status;
1431 struct intel_output *intel_output = to_intel_output(connector);
1432
1433 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1434 intel_sdvo_read_response(intel_output, &response, 2);
1435
1436 if (on) {
1437 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1438 status = intel_sdvo_read_response(intel_output, &response, 2);
1439
1440 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1441 } else {
1442 response[0] = 0;
1443 response[1] = 0;
1444 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1445 }
1446
1447 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1448 intel_sdvo_read_response(intel_output, &response, 2);
1449 }
1450
1451 static bool
1452 intel_sdvo_multifunc_encoder(struct intel_output *intel_output)
1453 {
1454 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1455 int caps = 0;
1456
1457 if (sdvo_priv->caps.output_flags &
1458 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1459 caps++;
1460 if (sdvo_priv->caps.output_flags &
1461 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1462 caps++;
1463 if (sdvo_priv->caps.output_flags &
1464 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
1465 caps++;
1466 if (sdvo_priv->caps.output_flags &
1467 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1468 caps++;
1469 if (sdvo_priv->caps.output_flags &
1470 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1471 caps++;
1472
1473 if (sdvo_priv->caps.output_flags &
1474 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1475 caps++;
1476
1477 if (sdvo_priv->caps.output_flags &
1478 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1479 caps++;
1480
1481 return (caps > 1);
1482 }
1483
1484 static struct drm_connector *
1485 intel_find_analog_connector(struct drm_device *dev)
1486 {
1487 struct drm_connector *connector;
1488 struct intel_output *intel_output;
1489
1490 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1491 intel_output = to_intel_output(connector);
1492 if (intel_output->type == INTEL_OUTPUT_ANALOG)
1493 return connector;
1494 }
1495 return NULL;
1496 }
1497
1498 static int
1499 intel_analog_is_connected(struct drm_device *dev)
1500 {
1501 struct drm_connector *analog_connector;
1502 analog_connector = intel_find_analog_connector(dev);
1503
1504 if (!analog_connector)
1505 return false;
1506
1507 if (analog_connector->funcs->detect(analog_connector) ==
1508 connector_status_disconnected)
1509 return false;
1510
1511 return true;
1512 }
1513
1514 enum drm_connector_status
1515 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
1516 {
1517 struct intel_output *intel_output = to_intel_output(connector);
1518 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1519 enum drm_connector_status status = connector_status_connected;
1520 struct edid *edid = NULL;
1521
1522 edid = drm_get_edid(&intel_output->base,
1523 intel_output->ddc_bus);
1524
1525 /* when there is no edid and no monitor is connected with VGA
1526 * port, try to use the CRT ddc to read the EDID for DVI-connector
1527 */
1528 if (edid == NULL &&
1529 sdvo_priv->analog_ddc_bus &&
1530 !intel_analog_is_connected(intel_output->base.dev))
1531 edid = drm_get_edid(&intel_output->base,
1532 sdvo_priv->analog_ddc_bus);
1533 if (edid != NULL) {
1534 /* Don't report the output as connected if it's a DVI-I
1535 * connector with a non-digital EDID coming out.
1536 */
1537 if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1538 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1539 sdvo_priv->is_hdmi =
1540 drm_detect_hdmi_monitor(edid);
1541 else
1542 status = connector_status_disconnected;
1543 }
1544
1545 kfree(edid);
1546 intel_output->base.display_info.raw_edid = NULL;
1547
1548 } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1549 status = connector_status_disconnected;
1550
1551 return status;
1552 }
1553
1554 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1555 {
1556 uint16_t response;
1557 u8 status;
1558 struct intel_output *intel_output = to_intel_output(connector);
1559 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1560
1561 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1562 status = intel_sdvo_read_response(intel_output, &response, 2);
1563
1564 DRM_DEBUG("SDVO response %d %d\n", response & 0xff, response >> 8);
1565
1566 if (status != SDVO_CMD_STATUS_SUCCESS)
1567 return connector_status_unknown;
1568
1569 if (response == 0)
1570 return connector_status_disconnected;
1571
1572 if (intel_sdvo_multifunc_encoder(intel_output) &&
1573 sdvo_priv->attached_output != response) {
1574 if (sdvo_priv->controlled_output != response &&
1575 intel_sdvo_output_setup(intel_output, response) != true)
1576 return connector_status_unknown;
1577 sdvo_priv->attached_output = response;
1578 }
1579 return intel_sdvo_hdmi_sink_detect(connector, response);
1580 }
1581
1582 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1583 {
1584 struct intel_output *intel_output = to_intel_output(connector);
1585 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1586 int num_modes;
1587
1588 /* set the bus switch and get the modes */
1589 num_modes = intel_ddc_get_modes(intel_output);
1590
1591 /*
1592 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1593 * link between analog and digital outputs. So, if the regular SDVO
1594 * DDC fails, check to see if the analog output is disconnected, in
1595 * which case we'll look there for the digital DDC data.
1596 */
1597 if (num_modes == 0 &&
1598 sdvo_priv->analog_ddc_bus &&
1599 !intel_analog_is_connected(intel_output->base.dev)) {
1600 struct i2c_adapter *digital_ddc_bus;
1601
1602 /* Switch to the analog ddc bus and try that
1603 */
1604 digital_ddc_bus = intel_output->ddc_bus;
1605 intel_output->ddc_bus = sdvo_priv->analog_ddc_bus;
1606
1607 (void) intel_ddc_get_modes(intel_output);
1608
1609 intel_output->ddc_bus = digital_ddc_bus;
1610 }
1611 }
1612
1613 /**
1614 * This function checks the current TV format, and chooses a default if
1615 * it hasn't been set.
1616 */
1617 static void
1618 intel_sdvo_check_tv_format(struct intel_output *output)
1619 {
1620 struct intel_sdvo_priv *dev_priv = output->dev_priv;
1621 struct intel_sdvo_tv_format format;
1622 uint8_t status;
1623
1624 intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0);
1625 status = intel_sdvo_read_response(output, &format, sizeof(format));
1626 if (status != SDVO_CMD_STATUS_SUCCESS)
1627 return;
1628
1629 memcpy(&dev_priv->tv_format, &format, sizeof(format));
1630 }
1631
1632 /*
1633 * Set of SDVO TV modes.
1634 * Note! This is in reply order (see loop in get_tv_modes).
1635 * XXX: all 60Hz refresh?
1636 */
1637 struct drm_display_mode sdvo_tv_modes[] = {
1638 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1639 416, 0, 200, 201, 232, 233, 0,
1640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1641 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1642 416, 0, 240, 241, 272, 273, 0,
1643 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1644 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1645 496, 0, 300, 301, 332, 333, 0,
1646 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1647 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1648 736, 0, 350, 351, 382, 383, 0,
1649 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1650 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1651 736, 0, 400, 401, 432, 433, 0,
1652 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1653 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1654 736, 0, 480, 481, 512, 513, 0,
1655 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1656 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1657 800, 0, 480, 481, 512, 513, 0,
1658 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1659 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1660 800, 0, 576, 577, 608, 609, 0,
1661 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1662 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1663 816, 0, 350, 351, 382, 383, 0,
1664 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1665 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1666 816, 0, 400, 401, 432, 433, 0,
1667 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1668 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1669 816, 0, 480, 481, 512, 513, 0,
1670 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1671 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1672 816, 0, 540, 541, 572, 573, 0,
1673 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1674 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1675 816, 0, 576, 577, 608, 609, 0,
1676 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1677 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1678 864, 0, 576, 577, 608, 609, 0,
1679 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1680 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1681 896, 0, 600, 601, 632, 633, 0,
1682 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1683 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1684 928, 0, 624, 625, 656, 657, 0,
1685 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1686 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1687 1016, 0, 766, 767, 798, 799, 0,
1688 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1689 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1690 1120, 0, 768, 769, 800, 801, 0,
1691 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1692 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1693 1376, 0, 1024, 1025, 1056, 1057, 0,
1694 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1695 };
1696
1697 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1698 {
1699 struct intel_output *output = to_intel_output(connector);
1700 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1701 struct intel_sdvo_sdtv_resolution_request tv_res;
1702 uint32_t reply = 0;
1703 uint8_t status;
1704 int i = 0;
1705
1706 intel_sdvo_check_tv_format(output);
1707
1708 /* Read the list of supported input resolutions for the selected TV
1709 * format.
1710 */
1711 memset(&tv_res, 0, sizeof(tv_res));
1712 memcpy(&tv_res, &sdvo_priv->tv_format, sizeof(tv_res));
1713 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1714 &tv_res, sizeof(tv_res));
1715 status = intel_sdvo_read_response(output, &reply, 3);
1716 if (status != SDVO_CMD_STATUS_SUCCESS)
1717 return;
1718
1719 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1720 if (reply & (1 << i)) {
1721 struct drm_display_mode *nmode;
1722 nmode = drm_mode_duplicate(connector->dev,
1723 &sdvo_tv_modes[i]);
1724 if (nmode)
1725 drm_mode_probed_add(connector, nmode);
1726 }
1727 }
1728
1729 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1730 {
1731 struct intel_output *intel_output = to_intel_output(connector);
1732 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1733 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1734 struct drm_display_mode *newmode;
1735
1736 /*
1737 * Attempt to get the mode list from DDC.
1738 * Assume that the preferred modes are
1739 * arranged in priority order.
1740 */
1741 intel_ddc_get_modes(intel_output);
1742 if (list_empty(&connector->probed_modes) == false)
1743 goto end;
1744
1745 /* Fetch modes from VBT */
1746 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
1747 newmode = drm_mode_duplicate(connector->dev,
1748 dev_priv->sdvo_lvds_vbt_mode);
1749 if (newmode != NULL) {
1750 /* Guarantee the mode is preferred */
1751 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1752 DRM_MODE_TYPE_DRIVER);
1753 drm_mode_probed_add(connector, newmode);
1754 }
1755 }
1756
1757 end:
1758 list_for_each_entry(newmode, &connector->probed_modes, head) {
1759 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1760 sdvo_priv->sdvo_lvds_fixed_mode =
1761 drm_mode_duplicate(connector->dev, newmode);
1762 break;
1763 }
1764 }
1765
1766 }
1767
1768 static int intel_sdvo_get_modes(struct drm_connector *connector)
1769 {
1770 struct intel_output *output = to_intel_output(connector);
1771 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1772
1773 if (sdvo_priv->is_tv)
1774 intel_sdvo_get_tv_modes(connector);
1775 else if (sdvo_priv->is_lvds == true)
1776 intel_sdvo_get_lvds_modes(connector);
1777 else
1778 intel_sdvo_get_ddc_modes(connector);
1779
1780 if (list_empty(&connector->probed_modes))
1781 return 0;
1782 return 1;
1783 }
1784
1785 static void intel_sdvo_destroy(struct drm_connector *connector)
1786 {
1787 struct intel_output *intel_output = to_intel_output(connector);
1788 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1789
1790 if (intel_output->i2c_bus)
1791 intel_i2c_destroy(intel_output->i2c_bus);
1792 if (intel_output->ddc_bus)
1793 intel_i2c_destroy(intel_output->ddc_bus);
1794 if (sdvo_priv->analog_ddc_bus)
1795 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
1796
1797 if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
1798 drm_mode_destroy(connector->dev,
1799 sdvo_priv->sdvo_lvds_fixed_mode);
1800
1801 drm_sysfs_connector_remove(connector);
1802 drm_connector_cleanup(connector);
1803
1804 kfree(intel_output);
1805 }
1806
1807 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1808 .dpms = intel_sdvo_dpms,
1809 .mode_fixup = intel_sdvo_mode_fixup,
1810 .prepare = intel_encoder_prepare,
1811 .mode_set = intel_sdvo_mode_set,
1812 .commit = intel_encoder_commit,
1813 };
1814
1815 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
1816 .dpms = drm_helper_connector_dpms,
1817 .save = intel_sdvo_save,
1818 .restore = intel_sdvo_restore,
1819 .detect = intel_sdvo_detect,
1820 .fill_modes = drm_helper_probe_single_connector_modes,
1821 .destroy = intel_sdvo_destroy,
1822 };
1823
1824 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1825 .get_modes = intel_sdvo_get_modes,
1826 .mode_valid = intel_sdvo_mode_valid,
1827 .best_encoder = intel_best_encoder,
1828 };
1829
1830 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
1831 {
1832 drm_encoder_cleanup(encoder);
1833 }
1834
1835 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1836 .destroy = intel_sdvo_enc_destroy,
1837 };
1838
1839
1840 /**
1841 * Choose the appropriate DDC bus for control bus switch command for this
1842 * SDVO output based on the controlled output.
1843 *
1844 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1845 * outputs, then LVDS outputs.
1846 */
1847 static void
1848 intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
1849 {
1850 uint16_t mask = 0;
1851 unsigned int num_bits;
1852
1853 /* Make a mask of outputs less than or equal to our own priority in the
1854 * list.
1855 */
1856 switch (dev_priv->controlled_output) {
1857 case SDVO_OUTPUT_LVDS1:
1858 mask |= SDVO_OUTPUT_LVDS1;
1859 case SDVO_OUTPUT_LVDS0:
1860 mask |= SDVO_OUTPUT_LVDS0;
1861 case SDVO_OUTPUT_TMDS1:
1862 mask |= SDVO_OUTPUT_TMDS1;
1863 case SDVO_OUTPUT_TMDS0:
1864 mask |= SDVO_OUTPUT_TMDS0;
1865 case SDVO_OUTPUT_RGB1:
1866 mask |= SDVO_OUTPUT_RGB1;
1867 case SDVO_OUTPUT_RGB0:
1868 mask |= SDVO_OUTPUT_RGB0;
1869 break;
1870 }
1871
1872 /* Count bits to find what number we are in the priority list. */
1873 mask &= dev_priv->caps.output_flags;
1874 num_bits = hweight16(mask);
1875 if (num_bits > 3) {
1876 /* if more than 3 outputs, default to DDC bus 3 for now */
1877 num_bits = 3;
1878 }
1879
1880 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1881 dev_priv->ddc_bus = 1 << num_bits;
1882 }
1883
1884 static bool
1885 intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
1886 {
1887 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1888 uint8_t status;
1889
1890 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1891
1892 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
1893 status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
1894 if (status != SDVO_CMD_STATUS_SUCCESS)
1895 return false;
1896 return true;
1897 }
1898
1899 static struct intel_output *
1900 intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan)
1901 {
1902 struct drm_device *dev = chan->drm_dev;
1903 struct drm_connector *connector;
1904 struct intel_output *intel_output = NULL;
1905
1906 list_for_each_entry(connector,
1907 &dev->mode_config.connector_list, head) {
1908 if (to_intel_output(connector)->ddc_bus == &chan->adapter) {
1909 intel_output = to_intel_output(connector);
1910 break;
1911 }
1912 }
1913 return intel_output;
1914 }
1915
1916 static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
1917 struct i2c_msg msgs[], int num)
1918 {
1919 struct intel_output *intel_output;
1920 struct intel_sdvo_priv *sdvo_priv;
1921 struct i2c_algo_bit_data *algo_data;
1922 const struct i2c_algorithm *algo;
1923
1924 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
1925 intel_output =
1926 intel_sdvo_chan_to_intel_output(
1927 (struct intel_i2c_chan *)(algo_data->data));
1928 if (intel_output == NULL)
1929 return -EINVAL;
1930
1931 sdvo_priv = intel_output->dev_priv;
1932 algo = intel_output->i2c_bus->algo;
1933
1934 intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
1935 return algo->master_xfer(i2c_adap, msgs, num);
1936 }
1937
1938 static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
1939 .master_xfer = intel_sdvo_master_xfer,
1940 };
1941
1942 static u8
1943 intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)
1944 {
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 struct sdvo_device_mapping *my_mapping, *other_mapping;
1947
1948 if (output_device == SDVOB) {
1949 my_mapping = &dev_priv->sdvo_mappings[0];
1950 other_mapping = &dev_priv->sdvo_mappings[1];
1951 } else {
1952 my_mapping = &dev_priv->sdvo_mappings[1];
1953 other_mapping = &dev_priv->sdvo_mappings[0];
1954 }
1955
1956 /* If the BIOS described our SDVO device, take advantage of it. */
1957 if (my_mapping->slave_addr)
1958 return my_mapping->slave_addr;
1959
1960 /* If the BIOS only described a different SDVO device, use the
1961 * address that it isn't using.
1962 */
1963 if (other_mapping->slave_addr) {
1964 if (other_mapping->slave_addr == 0x70)
1965 return 0x72;
1966 else
1967 return 0x70;
1968 }
1969
1970 /* No SDVO device info is found for another DVO port,
1971 * so use mapping assumption we had before BIOS parsing.
1972 */
1973 if (output_device == SDVOB)
1974 return 0x70;
1975 else
1976 return 0x72;
1977 }
1978
1979 static bool
1980 intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
1981 {
1982 struct drm_connector *connector = &intel_output->base;
1983 struct drm_encoder *encoder = &intel_output->enc;
1984 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1985 bool ret = true, registered = false;
1986
1987 sdvo_priv->is_tv = false;
1988 intel_output->needs_tv_clock = false;
1989 sdvo_priv->is_lvds = false;
1990
1991 if (device_is_registered(&connector->kdev)) {
1992 drm_sysfs_connector_remove(connector);
1993 registered = true;
1994 }
1995
1996 if (flags &
1997 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1998 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
1999 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
2000 else
2001 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
2002
2003 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2004 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2005
2006 if (intel_sdvo_get_supp_encode(intel_output,
2007 &sdvo_priv->encode) &&
2008 intel_sdvo_get_digital_encoding_mode(intel_output) &&
2009 sdvo_priv->is_hdmi) {
2010 /* enable hdmi encoding mode if supported */
2011 intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
2012 intel_sdvo_set_colorimetry(intel_output,
2013 SDVO_COLORIMETRY_RGB256);
2014 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2015 intel_output->clone_mask =
2016 (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2017 (1 << INTEL_ANALOG_CLONE_BIT);
2018 }
2019 } else if (flags & SDVO_OUTPUT_SVID0) {
2020
2021 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
2022 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2023 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2024 sdvo_priv->is_tv = true;
2025 intel_output->needs_tv_clock = true;
2026 intel_output->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2027 } else if (flags & SDVO_OUTPUT_RGB0) {
2028
2029 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
2030 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2031 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2032 intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2033 (1 << INTEL_ANALOG_CLONE_BIT);
2034 } else if (flags & SDVO_OUTPUT_RGB1) {
2035
2036 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
2037 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2038 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2039 } else if (flags & SDVO_OUTPUT_LVDS0) {
2040
2041 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
2042 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2043 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2044 sdvo_priv->is_lvds = true;
2045 intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2046 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2047 } else if (flags & SDVO_OUTPUT_LVDS1) {
2048
2049 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
2050 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2051 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2052 sdvo_priv->is_lvds = true;
2053 intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2054 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2055 } else {
2056
2057 unsigned char bytes[2];
2058
2059 sdvo_priv->controlled_output = 0;
2060 memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
2061 DRM_DEBUG_KMS(I915_SDVO,
2062 "%s: Unknown SDVO output type (0x%02x%02x)\n",
2063 SDVO_NAME(sdvo_priv),
2064 bytes[0], bytes[1]);
2065 ret = false;
2066 }
2067 intel_output->crtc_mask = (1 << 0) | (1 << 1);
2068
2069 if (ret && registered)
2070 ret = drm_sysfs_connector_add(connector) == 0 ? true : false;
2071
2072
2073 return ret;
2074
2075 }
2076
2077 bool intel_sdvo_init(struct drm_device *dev, int output_device)
2078 {
2079 struct drm_connector *connector;
2080 struct intel_output *intel_output;
2081 struct intel_sdvo_priv *sdvo_priv;
2082
2083 u8 ch[0x40];
2084 int i;
2085
2086 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
2087 if (!intel_output) {
2088 return false;
2089 }
2090
2091 sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
2092 sdvo_priv->output_device = output_device;
2093
2094 intel_output->dev_priv = sdvo_priv;
2095 intel_output->type = INTEL_OUTPUT_SDVO;
2096
2097 /* setup the DDC bus. */
2098 if (output_device == SDVOB)
2099 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
2100 else
2101 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
2102
2103 if (!intel_output->i2c_bus)
2104 goto err_inteloutput;
2105
2106 sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, output_device);
2107
2108 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
2109 intel_sdvo_i2c_bit_algo.functionality = intel_output->i2c_bus->algo->functionality;
2110
2111 /* Read the regs to test if we can talk to the device */
2112 for (i = 0; i < 0x40; i++) {
2113 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
2114 DRM_DEBUG_KMS(I915_SDVO,
2115 "No SDVO device found on SDVO%c\n",
2116 output_device == SDVOB ? 'B' : 'C');
2117 goto err_i2c;
2118 }
2119 }
2120
2121 /* setup the DDC bus. */
2122 if (output_device == SDVOB) {
2123 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
2124 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2125 "SDVOB/VGA DDC BUS");
2126 } else {
2127 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
2128 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2129 "SDVOC/VGA DDC BUS");
2130 }
2131
2132 if (intel_output->ddc_bus == NULL)
2133 goto err_i2c;
2134
2135 /* Wrap with our custom algo which switches to DDC mode */
2136 intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
2137
2138 /* In defaut case sdvo lvds is false */
2139 intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
2140
2141 if (intel_sdvo_output_setup(intel_output,
2142 sdvo_priv->caps.output_flags) != true) {
2143 DRM_DEBUG("SDVO output failed to setup on SDVO%c\n",
2144 output_device == SDVOB ? 'B' : 'C');
2145 goto err_i2c;
2146 }
2147
2148
2149 connector = &intel_output->base;
2150 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
2151 connector->connector_type);
2152
2153 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2154 connector->interlace_allowed = 0;
2155 connector->doublescan_allowed = 0;
2156 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2157
2158 drm_encoder_init(dev, &intel_output->enc,
2159 &intel_sdvo_enc_funcs, intel_output->enc.encoder_type);
2160
2161 drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
2162
2163 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
2164 drm_sysfs_connector_add(connector);
2165
2166 intel_sdvo_select_ddc_bus(sdvo_priv);
2167
2168 /* Set the input timing to the screen. Assume always input 0. */
2169 intel_sdvo_set_target_input(intel_output, true, false);
2170
2171 intel_sdvo_get_input_pixel_clock_range(intel_output,
2172 &sdvo_priv->pixel_clock_min,
2173 &sdvo_priv->pixel_clock_max);
2174
2175
2176 DRM_DEBUG_KMS(I915_SDVO, "%s device VID/DID: %02X:%02X.%02X, "
2177 "clock range %dMHz - %dMHz, "
2178 "input 1: %c, input 2: %c, "
2179 "output 1: %c, output 2: %c\n",
2180 SDVO_NAME(sdvo_priv),
2181 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
2182 sdvo_priv->caps.device_rev_id,
2183 sdvo_priv->pixel_clock_min / 1000,
2184 sdvo_priv->pixel_clock_max / 1000,
2185 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2186 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2187 /* check currently supported outputs */
2188 sdvo_priv->caps.output_flags &
2189 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2190 sdvo_priv->caps.output_flags &
2191 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2192
2193 return true;
2194
2195 err_i2c:
2196 if (sdvo_priv->analog_ddc_bus != NULL)
2197 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
2198 if (intel_output->ddc_bus != NULL)
2199 intel_i2c_destroy(intel_output->ddc_bus);
2200 if (intel_output->i2c_bus != NULL)
2201 intel_i2c_destroy(intel_output->i2c_bus);
2202 err_inteloutput:
2203 kfree(intel_output);
2204
2205 return false;
2206 }
2207
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