1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include <linux/sysrq.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drm.h"
33 #include "i915_drv.h"
34 #include "intel_drv.h"
35
36 #define MAX_NOPID ((u32)~0)
37
38 /**
39 * Interrupts that are always left unmasked.
40 *
41 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
42 * we leave them always unmasked in IMR and then control enabling them through
43 * PIPESTAT alone.
44 */
45 #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
46 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
47 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
48 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
49
50 /** Interrupts that we mask and unmask at runtime. */
51 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
52
53 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
54 PIPE_VBLANK_INTERRUPT_STATUS)
55
56 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
57 PIPE_VBLANK_INTERRUPT_ENABLE)
58
59 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
60 DRM_I915_VBLANK_PIPE_B)
61
62 void
63 igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
64 {
65 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
66 dev_priv->gt_irq_mask_reg &= ~mask;
67 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
68 (void) I915_READ(GTIMR);
69 }
70 }
71
72 static inline void
73 igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
74 {
75 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
76 dev_priv->gt_irq_mask_reg |= mask;
77 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
78 (void) I915_READ(GTIMR);
79 }
80 }
81
82 /* For display hotplug interrupt */
83 void
84 igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
85 {
86 if ((dev_priv->irq_mask_reg & mask) != 0) {
87 dev_priv->irq_mask_reg &= ~mask;
88 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
89 (void) I915_READ(DEIMR);
90 }
91 }
92
93 static inline void
94 igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
95 {
96 if ((dev_priv->irq_mask_reg & mask) != mask) {
97 dev_priv->irq_mask_reg |= mask;
98 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
99 (void) I915_READ(DEIMR);
100 }
101 }
102
103 void
104 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
105 {
106 if ((dev_priv->irq_mask_reg & mask) != 0) {
107 dev_priv->irq_mask_reg &= ~mask;
108 I915_WRITE(IMR, dev_priv->irq_mask_reg);
109 (void) I915_READ(IMR);
110 }
111 }
112
113 static inline void
114 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
115 {
116 if ((dev_priv->irq_mask_reg & mask) != mask) {
117 dev_priv->irq_mask_reg |= mask;
118 I915_WRITE(IMR, dev_priv->irq_mask_reg);
119 (void) I915_READ(IMR);
120 }
121 }
122
123 static inline u32
124 i915_pipestat(int pipe)
125 {
126 if (pipe == 0)
127 return PIPEASTAT;
128 if (pipe == 1)
129 return PIPEBSTAT;
130 BUG();
131 }
132
133 void
134 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
135 {
136 if ((dev_priv->pipestat[pipe] & mask) != mask) {
137 u32 reg = i915_pipestat(pipe);
138
139 dev_priv->pipestat[pipe] |= mask;
140 /* Enable the interrupt, clear any pending status */
141 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
142 (void) I915_READ(reg);
143 }
144 }
145
146 void
147 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
148 {
149 if ((dev_priv->pipestat[pipe] & mask) != 0) {
150 u32 reg = i915_pipestat(pipe);
151
152 dev_priv->pipestat[pipe] &= ~mask;
153 I915_WRITE(reg, dev_priv->pipestat[pipe]);
154 (void) I915_READ(reg);
155 }
156 }
157
158 /**
159 * i915_pipe_enabled - check if a pipe is enabled
160 * @dev: DRM device
161 * @pipe: pipe to check
162 *
163 * Reading certain registers when the pipe is disabled can hang the chip.
164 * Use this routine to make sure the PLL is running and the pipe is active
165 * before reading such registers if unsure.
166 */
167 static int
168 i915_pipe_enabled(struct drm_device *dev, int pipe)
169 {
170 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
171 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
172
173 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
174 return 1;
175
176 return 0;
177 }
178
179 /* Called from drm generic code, passed a 'crtc', which
180 * we use as a pipe index
181 */
182 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
183 {
184 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
185 unsigned long high_frame;
186 unsigned long low_frame;
187 u32 high1, high2, low, count;
188
189 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
190 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
191
192 if (!i915_pipe_enabled(dev, pipe)) {
193 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
194 return 0;
195 }
196
197 /*
198 * High & low register fields aren't synchronized, so make sure
199 * we get a low value that's stable across two reads of the high
200 * register.
201 */
202 do {
203 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
204 PIPE_FRAME_HIGH_SHIFT);
205 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
206 PIPE_FRAME_LOW_SHIFT);
207 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
208 PIPE_FRAME_HIGH_SHIFT);
209 } while (high1 != high2);
210
211 count = (high1 << 8) | low;
212
213 return count;
214 }
215
216 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
217 {
218 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
219 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
220
221 if (!i915_pipe_enabled(dev, pipe)) {
222 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
223 return 0;
224 }
225
226 return I915_READ(reg);
227 }
228
229 /*
230 * Handle hotplug events outside the interrupt handler proper.
231 */
232 static void i915_hotplug_work_func(struct work_struct *work)
233 {
234 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
235 hotplug_work);
236 struct drm_device *dev = dev_priv->dev;
237 struct drm_mode_config *mode_config = &dev->mode_config;
238 struct drm_connector *connector;
239
240 if (mode_config->num_connector) {
241 list_for_each_entry(connector, &mode_config->connector_list, head) {
242 struct intel_output *intel_output = to_intel_output(connector);
243
244 if (intel_output->hot_plug)
245 (*intel_output->hot_plug) (intel_output);
246 }
247 }
248 /* Just fire off a uevent and let userspace tell us what to do */
249 drm_sysfs_hotplug_event(dev);
250 }
251
252 irqreturn_t igdng_irq_handler(struct drm_device *dev)
253 {
254 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
255 int ret = IRQ_NONE;
256 u32 de_iir, gt_iir, de_ier;
257 u32 new_de_iir, new_gt_iir;
258 struct drm_i915_master_private *master_priv;
259
260 /* disable master interrupt before clearing iir */
261 de_ier = I915_READ(DEIER);
262 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
263 (void)I915_READ(DEIER);
264
265 de_iir = I915_READ(DEIIR);
266 gt_iir = I915_READ(GTIIR);
267
268 for (;;) {
269 if (de_iir == 0 && gt_iir == 0)
270 break;
271
272 ret = IRQ_HANDLED;
273
274 I915_WRITE(DEIIR, de_iir);
275 new_de_iir = I915_READ(DEIIR);
276 I915_WRITE(GTIIR, gt_iir);
277 new_gt_iir = I915_READ(GTIIR);
278
279 if (dev->primary->master) {
280 master_priv = dev->primary->master->driver_priv;
281 if (master_priv->sarea_priv)
282 master_priv->sarea_priv->last_dispatch =
283 READ_BREADCRUMB(dev_priv);
284 }
285
286 if (gt_iir & GT_USER_INTERRUPT) {
287 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
288 DRM_WAKEUP(&dev_priv->irq_queue);
289 }
290
291 de_iir = new_de_iir;
292 gt_iir = new_gt_iir;
293 }
294
295 I915_WRITE(DEIER, de_ier);
296 (void)I915_READ(DEIER);
297
298 return ret;
299 }
300
301 /**
302 * i915_error_work_func - do process context error handling work
303 * @work: work struct
304 *
305 * Fire an error uevent so userspace can see that a hang or error
306 * was detected.
307 */
308 static void i915_error_work_func(struct work_struct *work)
309 {
310 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
311 error_work);
312 struct drm_device *dev = dev_priv->dev;
313 char *event_string = "ERROR=1";
314 char *envp[] = { event_string, NULL };
315
316 DRM_DEBUG("generating error event\n");
317
318 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, envp);
319 }
320
321 /**
322 * i915_capture_error_state - capture an error record for later analysis
323 * @dev: drm device
324 *
325 * Should be called when an error is detected (either a hang or an error
326 * interrupt) to capture error state from the time of the error. Fills
327 * out a structure which becomes available in debugfs for user level tools
328 * to pick up.
329 */
330 static void i915_capture_error_state(struct drm_device *dev)
331 {
332 struct drm_i915_private *dev_priv = dev->dev_private;
333 struct drm_i915_error_state *error;
334 unsigned long flags;
335
336 spin_lock_irqsave(&dev_priv->error_lock, flags);
337 if (dev_priv->first_error)
338 goto out;
339
340 error = kmalloc(sizeof(*error), GFP_ATOMIC);
341 if (!error) {
342 DRM_DEBUG("out ot memory, not capturing error state\n");
343 goto out;
344 }
345
346 error->eir = I915_READ(EIR);
347 error->pgtbl_er = I915_READ(PGTBL_ER);
348 error->pipeastat = I915_READ(PIPEASTAT);
349 error->pipebstat = I915_READ(PIPEBSTAT);
350 error->instpm = I915_READ(INSTPM);
351 if (!IS_I965G(dev)) {
352 error->ipeir = I915_READ(IPEIR);
353 error->ipehr = I915_READ(IPEHR);
354 error->instdone = I915_READ(INSTDONE);
355 error->acthd = I915_READ(ACTHD);
356 } else {
357 error->ipeir = I915_READ(IPEIR_I965);
358 error->ipehr = I915_READ(IPEHR_I965);
359 error->instdone = I915_READ(INSTDONE_I965);
360 error->instps = I915_READ(INSTPS);
361 error->instdone1 = I915_READ(INSTDONE1);
362 error->acthd = I915_READ(ACTHD_I965);
363 }
364
365 do_gettimeofday(&error->time);
366
367 dev_priv->first_error = error;
368
369 out:
370 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
371 }
372
373 /**
374 * i915_handle_error - handle an error interrupt
375 * @dev: drm device
376 *
377 * Do some basic checking of regsiter state at error interrupt time and
378 * dump it to the syslog. Also call i915_capture_error_state() to make
379 * sure we get a record and make it available in debugfs. Fire a uevent
380 * so userspace knows something bad happened (should trigger collection
381 * of a ring dump etc.).
382 */
383 static void i915_handle_error(struct drm_device *dev)
384 {
385 struct drm_i915_private *dev_priv = dev->dev_private;
386 u32 eir = I915_READ(EIR);
387 u32 pipea_stats = I915_READ(PIPEASTAT);
388 u32 pipeb_stats = I915_READ(PIPEBSTAT);
389
390 i915_capture_error_state(dev);
391
392 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
393 eir);
394
395 if (IS_G4X(dev)) {
396 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
397 u32 ipeir = I915_READ(IPEIR_I965);
398
399 printk(KERN_ERR " IPEIR: 0x%08x\n",
400 I915_READ(IPEIR_I965));
401 printk(KERN_ERR " IPEHR: 0x%08x\n",
402 I915_READ(IPEHR_I965));
403 printk(KERN_ERR " INSTDONE: 0x%08x\n",
404 I915_READ(INSTDONE_I965));
405 printk(KERN_ERR " INSTPS: 0x%08x\n",
406 I915_READ(INSTPS));
407 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
408 I915_READ(INSTDONE1));
409 printk(KERN_ERR " ACTHD: 0x%08x\n",
410 I915_READ(ACTHD_I965));
411 I915_WRITE(IPEIR_I965, ipeir);
412 (void)I915_READ(IPEIR_I965);
413 }
414 if (eir & GM45_ERROR_PAGE_TABLE) {
415 u32 pgtbl_err = I915_READ(PGTBL_ER);
416 printk(KERN_ERR "page table error\n");
417 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
418 pgtbl_err);
419 I915_WRITE(PGTBL_ER, pgtbl_err);
420 (void)I915_READ(PGTBL_ER);
421 }
422 }
423
424 if (IS_I9XX(dev)) {
425 if (eir & I915_ERROR_PAGE_TABLE) {
426 u32 pgtbl_err = I915_READ(PGTBL_ER);
427 printk(KERN_ERR "page table error\n");
428 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
429 pgtbl_err);
430 I915_WRITE(PGTBL_ER, pgtbl_err);
431 (void)I915_READ(PGTBL_ER);
432 }
433 }
434
435 if (eir & I915_ERROR_MEMORY_REFRESH) {
436 printk(KERN_ERR "memory refresh error\n");
437 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
438 pipea_stats);
439 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
440 pipeb_stats);
441 /* pipestat has already been acked */
442 }
443 if (eir & I915_ERROR_INSTRUCTION) {
444 printk(KERN_ERR "instruction error\n");
445 printk(KERN_ERR " INSTPM: 0x%08x\n",
446 I915_READ(INSTPM));
447 if (!IS_I965G(dev)) {
448 u32 ipeir = I915_READ(IPEIR);
449
450 printk(KERN_ERR " IPEIR: 0x%08x\n",
451 I915_READ(IPEIR));
452 printk(KERN_ERR " IPEHR: 0x%08x\n",
453 I915_READ(IPEHR));
454 printk(KERN_ERR " INSTDONE: 0x%08x\n",
455 I915_READ(INSTDONE));
456 printk(KERN_ERR " ACTHD: 0x%08x\n",
457 I915_READ(ACTHD));
458 I915_WRITE(IPEIR, ipeir);
459 (void)I915_READ(IPEIR);
460 } else {
461 u32 ipeir = I915_READ(IPEIR_I965);
462
463 printk(KERN_ERR " IPEIR: 0x%08x\n",
464 I915_READ(IPEIR_I965));
465 printk(KERN_ERR " IPEHR: 0x%08x\n",
466 I915_READ(IPEHR_I965));
467 printk(KERN_ERR " INSTDONE: 0x%08x\n",
468 I915_READ(INSTDONE_I965));
469 printk(KERN_ERR " INSTPS: 0x%08x\n",
470 I915_READ(INSTPS));
471 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
472 I915_READ(INSTDONE1));
473 printk(KERN_ERR " ACTHD: 0x%08x\n",
474 I915_READ(ACTHD_I965));
475 I915_WRITE(IPEIR_I965, ipeir);
476 (void)I915_READ(IPEIR_I965);
477 }
478 }
479
480 I915_WRITE(EIR, eir);
481 (void)I915_READ(EIR);
482 eir = I915_READ(EIR);
483 if (eir) {
484 /*
485 * some errors might have become stuck,
486 * mask them.
487 */
488 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
489 I915_WRITE(EMR, I915_READ(EMR) | eir);
490 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
491 }
492
493 queue_work(dev_priv->wq, &dev_priv->error_work);
494 }
495
496 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
497 {
498 struct drm_device *dev = (struct drm_device *) arg;
499 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
500 struct drm_i915_master_private *master_priv;
501 u32 iir, new_iir;
502 u32 pipea_stats, pipeb_stats;
503 u32 vblank_status;
504 u32 vblank_enable;
505 int vblank = 0;
506 unsigned long irqflags;
507 int irq_received;
508 int ret = IRQ_NONE;
509
510 atomic_inc(&dev_priv->irq_received);
511
512 if (IS_IGDNG(dev))
513 return igdng_irq_handler(dev);
514
515 iir = I915_READ(IIR);
516
517 if (IS_I965G(dev)) {
518 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
519 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
520 } else {
521 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
522 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
523 }
524
525 for (;;) {
526 irq_received = iir != 0;
527
528 /* Can't rely on pipestat interrupt bit in iir as it might
529 * have been cleared after the pipestat interrupt was received.
530 * It doesn't set the bit in iir again, but it still produces
531 * interrupts (for non-MSI).
532 */
533 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
534 pipea_stats = I915_READ(PIPEASTAT);
535 pipeb_stats = I915_READ(PIPEBSTAT);
536
537 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
538 i915_handle_error(dev);
539
540 /*
541 * Clear the PIPE(A|B)STAT regs before the IIR
542 */
543 if (pipea_stats & 0x8000ffff) {
544 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
545 DRM_DEBUG("pipe a underrun\n");
546 I915_WRITE(PIPEASTAT, pipea_stats);
547 irq_received = 1;
548 }
549
550 if (pipeb_stats & 0x8000ffff) {
551 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
552 DRM_DEBUG("pipe b underrun\n");
553 I915_WRITE(PIPEBSTAT, pipeb_stats);
554 irq_received = 1;
555 }
556 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
557
558 if (!irq_received)
559 break;
560
561 ret = IRQ_HANDLED;
562
563 /* Consume port. Then clear IIR or we'll miss events */
564 if ((I915_HAS_HOTPLUG(dev)) &&
565 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
566 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
567
568 DRM_DEBUG("hotplug event received, stat 0x%08x\n",
569 hotplug_status);
570 if (hotplug_status & dev_priv->hotplug_supported_mask)
571 queue_work(dev_priv->wq,
572 &dev_priv->hotplug_work);
573
574 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
575 I915_READ(PORT_HOTPLUG_STAT);
576 }
577
578 I915_WRITE(IIR, iir);
579 new_iir = I915_READ(IIR); /* Flush posted writes */
580
581 if (dev->primary->master) {
582 master_priv = dev->primary->master->driver_priv;
583 if (master_priv->sarea_priv)
584 master_priv->sarea_priv->last_dispatch =
585 READ_BREADCRUMB(dev_priv);
586 }
587
588 if (iir & I915_USER_INTERRUPT) {
589 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
590 DRM_WAKEUP(&dev_priv->irq_queue);
591 }
592
593 if (pipea_stats & vblank_status) {
594 vblank++;
595 drm_handle_vblank(dev, 0);
596 }
597
598 if (pipeb_stats & vblank_status) {
599 vblank++;
600 drm_handle_vblank(dev, 1);
601 }
602
603 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
604 (iir & I915_ASLE_INTERRUPT))
605 opregion_asle_intr(dev);
606
607 /* With MSI, interrupts are only generated when iir
608 * transitions from zero to nonzero. If another bit got
609 * set while we were handling the existing iir bits, then
610 * we would never get another interrupt.
611 *
612 * This is fine on non-MSI as well, as if we hit this path
613 * we avoid exiting the interrupt handler only to generate
614 * another one.
615 *
616 * Note that for MSI this could cause a stray interrupt report
617 * if an interrupt landed in the time between writing IIR and
618 * the posting read. This should be rare enough to never
619 * trigger the 99% of 100,000 interrupts test for disabling
620 * stray interrupts.
621 */
622 iir = new_iir;
623 }
624
625 return ret;
626 }
627
628 static int i915_emit_irq(struct drm_device * dev)
629 {
630 drm_i915_private_t *dev_priv = dev->dev_private;
631 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
632 RING_LOCALS;
633
634 i915_kernel_lost_context(dev);
635
636 DRM_DEBUG("\n");
637
638 dev_priv->counter++;
639 if (dev_priv->counter > 0x7FFFFFFFUL)
640 dev_priv->counter = 1;
641 if (master_priv->sarea_priv)
642 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
643
644 BEGIN_LP_RING(4);
645 OUT_RING(MI_STORE_DWORD_INDEX);
646 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
647 OUT_RING(dev_priv->counter);
648 OUT_RING(MI_USER_INTERRUPT);
649 ADVANCE_LP_RING();
650
651 return dev_priv->counter;
652 }
653
654 void i915_user_irq_get(struct drm_device *dev)
655 {
656 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
657 unsigned long irqflags;
658
659 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
660 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
661 if (IS_IGDNG(dev))
662 igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
663 else
664 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
665 }
666 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
667 }
668
669 void i915_user_irq_put(struct drm_device *dev)
670 {
671 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
672 unsigned long irqflags;
673
674 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
675 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
676 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
677 if (IS_IGDNG(dev))
678 igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
679 else
680 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
681 }
682 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
683 }
684
685 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
686 {
687 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
688 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
689 int ret = 0;
690
691 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
692 READ_BREADCRUMB(dev_priv));
693
694 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
695 if (master_priv->sarea_priv)
696 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
697 return 0;
698 }
699
700 if (master_priv->sarea_priv)
701 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
702
703 i915_user_irq_get(dev);
704 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
705 READ_BREADCRUMB(dev_priv) >= irq_nr);
706 i915_user_irq_put(dev);
707
708 if (ret == -EBUSY) {
709 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
710 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
711 }
712
713 return ret;
714 }
715
716 /* Needs the lock as it touches the ring.
717 */
718 int i915_irq_emit(struct drm_device *dev, void *data,
719 struct drm_file *file_priv)
720 {
721 drm_i915_private_t *dev_priv = dev->dev_private;
722 drm_i915_irq_emit_t *emit = data;
723 int result;
724
725 if (!dev_priv || !dev_priv->ring.virtual_start) {
726 DRM_ERROR("called with no initialization\n");
727 return -EINVAL;
728 }
729
730 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
731
732 mutex_lock(&dev->struct_mutex);
733 result = i915_emit_irq(dev);
734 mutex_unlock(&dev->struct_mutex);
735
736 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
737 DRM_ERROR("copy_to_user\n");
738 return -EFAULT;
739 }
740
741 return 0;
742 }
743
744 /* Doesn't need the hardware lock.
745 */
746 int i915_irq_wait(struct drm_device *dev, void *data,
747 struct drm_file *file_priv)
748 {
749 drm_i915_private_t *dev_priv = dev->dev_private;
750 drm_i915_irq_wait_t *irqwait = data;
751
752 if (!dev_priv) {
753 DRM_ERROR("called with no initialization\n");
754 return -EINVAL;
755 }
756
757 return i915_wait_irq(dev, irqwait->irq_seq);
758 }
759
760 /* Called from drm generic code, passed 'crtc' which
761 * we use as a pipe index
762 */
763 int i915_enable_vblank(struct drm_device *dev, int pipe)
764 {
765 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
766 unsigned long irqflags;
767 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
768 u32 pipeconf;
769
770 pipeconf = I915_READ(pipeconf_reg);
771 if (!(pipeconf & PIPEACONF_ENABLE))
772 return -EINVAL;
773
774 if (IS_IGDNG(dev))
775 return 0;
776
777 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
778 if (IS_I965G(dev))
779 i915_enable_pipestat(dev_priv, pipe,
780 PIPE_START_VBLANK_INTERRUPT_ENABLE);
781 else
782 i915_enable_pipestat(dev_priv, pipe,
783 PIPE_VBLANK_INTERRUPT_ENABLE);
784 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
785 return 0;
786 }
787
788 /* Called from drm generic code, passed 'crtc' which
789 * we use as a pipe index
790 */
791 void i915_disable_vblank(struct drm_device *dev, int pipe)
792 {
793 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
794 unsigned long irqflags;
795
796 if (IS_IGDNG(dev))
797 return;
798
799 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
800 i915_disable_pipestat(dev_priv, pipe,
801 PIPE_VBLANK_INTERRUPT_ENABLE |
802 PIPE_START_VBLANK_INTERRUPT_ENABLE);
803 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
804 }
805
806 void i915_enable_interrupt (struct drm_device *dev)
807 {
808 struct drm_i915_private *dev_priv = dev->dev_private;
809
810 if (!IS_IGDNG(dev))
811 opregion_enable_asle(dev);
812 dev_priv->irq_enabled = 1;
813 }
814
815
816 /* Set the vblank monitor pipe
817 */
818 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
819 struct drm_file *file_priv)
820 {
821 drm_i915_private_t *dev_priv = dev->dev_private;
822
823 if (!dev_priv) {
824 DRM_ERROR("called with no initialization\n");
825 return -EINVAL;
826 }
827
828 return 0;
829 }
830
831 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
832 struct drm_file *file_priv)
833 {
834 drm_i915_private_t *dev_priv = dev->dev_private;
835 drm_i915_vblank_pipe_t *pipe = data;
836
837 if (!dev_priv) {
838 DRM_ERROR("called with no initialization\n");
839 return -EINVAL;
840 }
841
842 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
843
844 return 0;
845 }
846
847 /**
848 * Schedule buffer swap at given vertical blank.
849 */
850 int i915_vblank_swap(struct drm_device *dev, void *data,
851 struct drm_file *file_priv)
852 {
853 /* The delayed swap mechanism was fundamentally racy, and has been
854 * removed. The model was that the client requested a delayed flip/swap
855 * from the kernel, then waited for vblank before continuing to perform
856 * rendering. The problem was that the kernel might wake the client
857 * up before it dispatched the vblank swap (since the lock has to be
858 * held while touching the ringbuffer), in which case the client would
859 * clear and start the next frame before the swap occurred, and
860 * flicker would occur in addition to likely missing the vblank.
861 *
862 * In the absence of this ioctl, userland falls back to a correct path
863 * of waiting for a vblank, then dispatching the swap on its own.
864 * Context switching to userland and back is plenty fast enough for
865 * meeting the requirements of vblank swapping.
866 */
867 return -EINVAL;
868 }
869
870 /* drm_dma.h hooks
871 */
872 static void igdng_irq_preinstall(struct drm_device *dev)
873 {
874 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
875
876 I915_WRITE(HWSTAM, 0xeffe);
877
878 /* XXX hotplug from PCH */
879
880 I915_WRITE(DEIMR, 0xffffffff);
881 I915_WRITE(DEIER, 0x0);
882 (void) I915_READ(DEIER);
883
884 /* and GT */
885 I915_WRITE(GTIMR, 0xffffffff);
886 I915_WRITE(GTIER, 0x0);
887 (void) I915_READ(GTIER);
888 }
889
890 static int igdng_irq_postinstall(struct drm_device *dev)
891 {
892 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
893 /* enable kind of interrupts always enabled */
894 u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */;
895 u32 render_mask = GT_USER_INTERRUPT;
896
897 dev_priv->irq_mask_reg = ~display_mask;
898 dev_priv->de_irq_enable_reg = display_mask;
899
900 /* should always can generate irq */
901 I915_WRITE(DEIIR, I915_READ(DEIIR));
902 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
903 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
904 (void) I915_READ(DEIER);
905
906 /* user interrupt should be enabled, but masked initial */
907 dev_priv->gt_irq_mask_reg = 0xffffffff;
908 dev_priv->gt_irq_enable_reg = render_mask;
909
910 I915_WRITE(GTIIR, I915_READ(GTIIR));
911 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
912 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
913 (void) I915_READ(GTIER);
914
915 return 0;
916 }
917
918 void i915_driver_irq_preinstall(struct drm_device * dev)
919 {
920 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
921
922 atomic_set(&dev_priv->irq_received, 0);
923
924 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
925 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
926
927 if (IS_IGDNG(dev)) {
928 igdng_irq_preinstall(dev);
929 return;
930 }
931
932 if (I915_HAS_HOTPLUG(dev)) {
933 I915_WRITE(PORT_HOTPLUG_EN, 0);
934 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
935 }
936
937 I915_WRITE(HWSTAM, 0xeffe);
938 I915_WRITE(PIPEASTAT, 0);
939 I915_WRITE(PIPEBSTAT, 0);
940 I915_WRITE(IMR, 0xffffffff);
941 I915_WRITE(IER, 0x0);
942 (void) I915_READ(IER);
943 }
944
945 int i915_driver_irq_postinstall(struct drm_device *dev)
946 {
947 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
948 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
949 u32 error_mask;
950
951 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
952
953 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
954
955 if (IS_IGDNG(dev))
956 return igdng_irq_postinstall(dev);
957
958 /* Unmask the interrupts that we always want on. */
959 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
960
961 dev_priv->pipestat[0] = 0;
962 dev_priv->pipestat[1] = 0;
963
964 if (I915_HAS_HOTPLUG(dev)) {
965 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
966
967 /* Leave other bits alone */
968 hotplug_en |= HOTPLUG_EN_MASK;
969 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
970
971 dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS |
972 TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS |
973 SDVOB_HOTPLUG_INT_STATUS;
974 if (IS_G4X(dev)) {
975 dev_priv->hotplug_supported_mask |=
976 HDMIB_HOTPLUG_INT_STATUS |
977 HDMIC_HOTPLUG_INT_STATUS |
978 HDMID_HOTPLUG_INT_STATUS;
979 }
980 /* Enable in IER... */
981 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
982 /* and unmask in IMR */
983 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
984 }
985
986 /*
987 * Enable some error detection, note the instruction error mask
988 * bit is reserved, so we leave it masked.
989 */
990 if (IS_G4X(dev)) {
991 error_mask = ~(GM45_ERROR_PAGE_TABLE |
992 GM45_ERROR_MEM_PRIV |
993 GM45_ERROR_CP_PRIV |
994 I915_ERROR_MEMORY_REFRESH);
995 } else {
996 error_mask = ~(I915_ERROR_PAGE_TABLE |
997 I915_ERROR_MEMORY_REFRESH);
998 }
999 I915_WRITE(EMR, error_mask);
1000
1001 /* Disable pipe interrupt enables, clear pending pipe status */
1002 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1003 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1004 /* Clear pending interrupt status */
1005 I915_WRITE(IIR, I915_READ(IIR));
1006
1007 I915_WRITE(IER, enable_mask);
1008 I915_WRITE(IMR, dev_priv->irq_mask_reg);
1009 (void) I915_READ(IER);
1010
1011 opregion_enable_asle(dev);
1012
1013 return 0;
1014 }
1015
1016 static void igdng_irq_uninstall(struct drm_device *dev)
1017 {
1018 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1019 I915_WRITE(HWSTAM, 0xffffffff);
1020
1021 I915_WRITE(DEIMR, 0xffffffff);
1022 I915_WRITE(DEIER, 0x0);
1023 I915_WRITE(DEIIR, I915_READ(DEIIR));
1024
1025 I915_WRITE(GTIMR, 0xffffffff);
1026 I915_WRITE(GTIER, 0x0);
1027 I915_WRITE(GTIIR, I915_READ(GTIIR));
1028 }
1029
1030 void i915_driver_irq_uninstall(struct drm_device * dev)
1031 {
1032 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1033
1034 if (!dev_priv)
1035 return;
1036
1037 dev_priv->vblank_pipe = 0;
1038
1039 if (IS_IGDNG(dev)) {
1040 igdng_irq_uninstall(dev);
1041 return;
1042 }
1043
1044 if (I915_HAS_HOTPLUG(dev)) {
1045 I915_WRITE(PORT_HOTPLUG_EN, 0);
1046 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1047 }
1048
1049 I915_WRITE(HWSTAM, 0xffffffff);
1050 I915_WRITE(PIPEASTAT, 0);
1051 I915_WRITE(PIPEBSTAT, 0);
1052 I915_WRITE(IMR, 0xffffffff);
1053 I915_WRITE(IER, 0x0);
1054
1055 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1056 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1057 I915_WRITE(IIR, I915_READ(IIR));
1058 }
1059
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