1 /*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
3 *
4 * Author:
5 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
6 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
7 *
8 * This is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14 #ifndef __DMA_FSLDMA_H
15 #define __DMA_FSLDMA_H
16
17 #include <linux/device.h>
18 #include <linux/dmapool.h>
19 #include <linux/dmaengine.h>
20
21 /* Define data structures needed by Freescale
22 * MPC8540 and MPC8349 DMA controller.
23 */
24 #define FSL_DMA_MR_CS 0x00000001
25 #define FSL_DMA_MR_CC 0x00000002
26 #define FSL_DMA_MR_CA 0x00000008
27 #define FSL_DMA_MR_EIE 0x00000040
28 #define FSL_DMA_MR_XFE 0x00000020
29 #define FSL_DMA_MR_EOLNIE 0x00000100
30 #define FSL_DMA_MR_EOLSIE 0x00000080
31 #define FSL_DMA_MR_EOSIE 0x00000200
32 #define FSL_DMA_MR_CDSM 0x00000010
33 #define FSL_DMA_MR_CTM 0x00000004
34 #define FSL_DMA_MR_EMP_EN 0x00200000
35 #define FSL_DMA_MR_EMS_EN 0x00040000
36 #define FSL_DMA_MR_DAHE 0x00002000
37 #define FSL_DMA_MR_SAHE 0x00001000
38
39 /* Special MR definition for MPC8349 */
40 #define FSL_DMA_MR_EOTIE 0x00000080
41
42 #define FSL_DMA_SR_CH 0x00000020
43 #define FSL_DMA_SR_PE 0x00000010
44 #define FSL_DMA_SR_CB 0x00000004
45 #define FSL_DMA_SR_TE 0x00000080
46 #define FSL_DMA_SR_EOSI 0x00000002
47 #define FSL_DMA_SR_EOLSI 0x00000001
48 #define FSL_DMA_SR_EOCDI 0x00000001
49 #define FSL_DMA_SR_EOLNI 0x00000008
50
51 #define FSL_DMA_SATR_SBPATMU 0x20000000
52 #define FSL_DMA_SATR_STRANSINT_RIO 0x00c00000
53 #define FSL_DMA_SATR_SREADTYPE_SNOOP_READ 0x00050000
54 #define FSL_DMA_SATR_SREADTYPE_BP_IORH 0x00020000
55 #define FSL_DMA_SATR_SREADTYPE_BP_NREAD 0x00040000
56 #define FSL_DMA_SATR_SREADTYPE_BP_MREAD 0x00070000
57
58 #define FSL_DMA_DATR_DBPATMU 0x20000000
59 #define FSL_DMA_DATR_DTRANSINT_RIO 0x00c00000
60 #define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE 0x00050000
61 #define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH 0x00010000
62
63 #define FSL_DMA_EOL ((u64)0x1)
64 #define FSL_DMA_SNEN ((u64)0x10)
65 #define FSL_DMA_EOSIE 0x8
66 #define FSL_DMA_NLDA_MASK (~(u64)0x1f)
67
68 #define FSL_DMA_BCR_MAX_CNT 0x03ffffffu
69
70 #define FSL_DMA_DGSR_TE 0x80
71 #define FSL_DMA_DGSR_CH 0x20
72 #define FSL_DMA_DGSR_PE 0x10
73 #define FSL_DMA_DGSR_EOLNI 0x08
74 #define FSL_DMA_DGSR_CB 0x04
75 #define FSL_DMA_DGSR_EOSI 0x02
76 #define FSL_DMA_DGSR_EOLSI 0x01
77
78 typedef u64 __bitwise v64;
79 typedef u32 __bitwise v32;
80
81 struct fsl_dma_ld_hw {
82 v64 src_addr;
83 v64 dst_addr;
84 v64 next_ln_addr;
85 v32 count;
86 v32 reserve;
87 } __attribute__((aligned(32)));
88
89 struct fsl_desc_sw {
90 struct fsl_dma_ld_hw hw;
91 struct list_head node;
92 struct dma_async_tx_descriptor async_tx;
93 struct list_head *ld;
94 void *priv;
95 } __attribute__((aligned(32)));
96
97 struct fsl_dma_chan_regs {
98 u32 mr; /* 0x00 - Mode Register */
99 u32 sr; /* 0x04 - Status Register */
100 u64 cdar; /* 0x08 - Current descriptor address register */
101 u64 sar; /* 0x10 - Source Address Register */
102 u64 dar; /* 0x18 - Destination Address Register */
103 u32 bcr; /* 0x20 - Byte Count Register */
104 u64 ndar; /* 0x24 - Next Descriptor Address Register */
105 };
106
107 struct fsl_dma_chan;
108 #define FSL_DMA_MAX_CHANS_PER_DEVICE 4
109
110 struct fsl_dma_device {
111 void __iomem *reg_base; /* DGSR register base */
112 struct resource reg; /* Resource for register */
113 struct device *dev;
114 struct dma_device common;
115 struct fsl_dma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE];
116 u32 feature; /* The same as DMA channels */
117 };
118
119 /* Define macros for fsl_dma_chan->feature property */
120 #define FSL_DMA_LITTLE_ENDIAN 0x00000000
121 #define FSL_DMA_BIG_ENDIAN 0x00000001
122
123 #define FSL_DMA_IP_MASK 0x00000ff0
124 #define FSL_DMA_IP_85XX 0x00000010
125 #define FSL_DMA_IP_83XX 0x00000020
126
127 #define FSL_DMA_CHAN_PAUSE_EXT 0x00001000
128 #define FSL_DMA_CHAN_START_EXT 0x00002000
129
130 struct fsl_dma_chan {
131 struct fsl_dma_chan_regs __iomem *reg_base;
132 dma_cookie_t completed_cookie; /* The maximum cookie completed */
133 spinlock_t desc_lock; /* Descriptor operation lock */
134 struct list_head ld_queue; /* Link descriptors queue */
135 struct dma_chan common; /* DMA common channel */
136 struct dma_pool *desc_pool; /* Descriptors pool */
137 struct device *dev; /* Channel device */
138 struct resource reg; /* Resource for register */
139 int irq; /* Channel IRQ */
140 int id; /* Raw id of this channel */
141 struct tasklet_struct tasklet;
142 u32 feature;
143
144 void (*toggle_ext_pause)(struct fsl_dma_chan *fsl_chan, int size);
145 void (*toggle_ext_start)(struct fsl_dma_chan *fsl_chan, int enable);
146 void (*set_src_loop_size)(struct fsl_dma_chan *fsl_chan, int size);
147 void (*set_dest_loop_size)(struct fsl_dma_chan *fsl_chan, int size);
148 };
149
150 #define to_fsl_chan(chan) container_of(chan, struct fsl_dma_chan, common)
151 #define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node)
152 #define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx)
153
154 #ifndef __powerpc64__
155 static u64 in_be64(const u64 __iomem *addr)
156 {
157 return ((u64)in_be32((u32 __iomem *)addr) << 32) |
158 (in_be32((u32 __iomem *)addr + 1));
159 }
160
161 static void out_be64(u64 __iomem *addr, u64 val)
162 {
163 out_be32((u32 __iomem *)addr, val >> 32);
164 out_be32((u32 __iomem *)addr + 1, (u32)val);
165 }
166
167 /* There is no asm instructions for 64 bits reverse loads and stores */
168 static u64 in_le64(const u64 __iomem *addr)
169 {
170 return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) |
171 (in_le32((u32 __iomem *)addr));
172 }
173
174 static void out_le64(u64 __iomem *addr, u64 val)
175 {
176 out_le32((u32 __iomem *)addr + 1, val >> 32);
177 out_le32((u32 __iomem *)addr, (u32)val);
178 }
179 #endif
180
181 #define DMA_IN(fsl_chan, addr, width) \
182 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
183 in_be##width(addr) : in_le##width(addr))
184 #define DMA_OUT(fsl_chan, addr, val, width) \
185 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
186 out_be##width(addr, val) : out_le##width(addr, val))
187
188 #define DMA_TO_CPU(fsl_chan, d, width) \
189 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
190 be##width##_to_cpu((__force __be##width)(v##width)d) : \
191 le##width##_to_cpu((__force __le##width)(v##width)d))
192 #define CPU_TO_DMA(fsl_chan, c, width) \
193 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
194 (__force v##width)cpu_to_be##width(c) : \
195 (__force v##width)cpu_to_le##width(c))
196
197 #endif /* __DMA_FSLDMA_H */
198
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