1 /************************************************************************/
2 /* */
3 /* Title : SX/SI/XIO Board Hardware Definitions */
4 /* */
5 /* Author : N.P.Vassallo */
6 /* */
7 /* Creation : 16th March 1998 */
8 /* */
9 /* Version : 3.0.0 */
10 /* */
11 /* Copyright : (c) Specialix International Ltd. 1998 */
12 /* */
13 /* Description : Prototypes, structures and definitions */
14 /* describing the SX/SI/XIO board hardware */
15 /* */
16 /************************************************************************/
17
18 /* History...
19
20 3.0.0 16/03/98 NPV Creation.
21
22 */
23
24 #ifndef _sxboards_h /* If SXBOARDS.H not already defined */
25 #define _sxboards_h 1
26
27 /*****************************************************************************
28 ******************************* ******************************
29 ******************************* Board Types ******************************
30 ******************************* ******************************
31 *****************************************************************************/
32
33 /* BUS types... */
34 #define BUS_ISA 0
35 #define BUS_MCA 1
36 #define BUS_EISA 2
37 #define BUS_PCI 3
38
39 /* Board phases... */
40 #define SI1_Z280 1
41 #define SI2_Z280 2
42 #define SI3_T225 3
43
44 /* Board types... */
45 #define CARD_TYPE(bus,phase) (bus<<4|phase)
46 #define CARD_BUS(type) ((type>>4)&0xF)
47 #define CARD_PHASE(type) (type&0xF)
48
49 #define TYPE_SI1_ISA CARD_TYPE(BUS_ISA,SI1_Z280)
50 #define TYPE_SI2_ISA CARD_TYPE(BUS_ISA,SI2_Z280)
51 #define TYPE_SI2_EISA CARD_TYPE(BUS_EISA,SI2_Z280)
52 #define TYPE_SI2_PCI CARD_TYPE(BUS_PCI,SI2_Z280)
53
54 #define TYPE_SX_ISA CARD_TYPE(BUS_ISA,SI3_T225)
55 #define TYPE_SX_PCI CARD_TYPE(BUS_PCI,SI3_T225)
56 /*****************************************************************************
57 ****************************** ******************************
58 ****************************** Phase 1 Z280 ******************************
59 ****************************** ******************************
60 *****************************************************************************/
61
62 /* ISA board details... */
63 #define SI1_ISA_WINDOW_LEN 0x10000 /* 64 Kbyte shared memory window */
64 //#define SI1_ISA_MEMORY_LEN 0x8000 /* Usable memory - unused define*/
65 //#define SI1_ISA_ADDR_LOW 0x0A0000 /* Lowest address = 640 Kbyte */
66 //#define SI1_ISA_ADDR_HIGH 0xFF8000 /* Highest address = 16Mbyte - 32Kbyte */
67 //#define SI2_ISA_ADDR_STEP SI2_ISA_WINDOW_LEN/* ISA board address step */
68 //#define SI2_ISA_IRQ_MASK 0x9800 /* IRQs 15,12,11 */
69
70 /* ISA board, register definitions... */
71 //#define SI2_ISA_ID_BASE 0x7FF8 /* READ: Board ID string */
72 #define SI1_ISA_RESET 0x8000 /* WRITE: Host Reset */
73 #define SI1_ISA_RESET_CLEAR 0xc000 /* WRITE: Host Reset clear*/
74 #define SI1_ISA_WAIT 0x9000 /* WRITE: Host wait */
75 #define SI1_ISA_WAIT_CLEAR 0xd000 /* WRITE: Host wait clear */
76 #define SI1_ISA_INTCL 0xa000 /* WRITE: Host Reset */
77 #define SI1_ISA_INTCL_CLEAR 0xe000 /* WRITE: Host Reset */
78
79
80 /*****************************************************************************
81 ****************************** ******************************
82 ****************************** Phase 2 Z280 ******************************
83 ****************************** ******************************
84 *****************************************************************************/
85
86 /* ISA board details... */
87 #define SI2_ISA_WINDOW_LEN 0x8000 /* 32 Kbyte shared memory window */
88 #define SI2_ISA_MEMORY_LEN 0x7FF8 /* Usable memory */
89 #define SI2_ISA_ADDR_LOW 0x0A0000 /* Lowest address = 640 Kbyte */
90 #define SI2_ISA_ADDR_HIGH 0xFF8000 /* Highest address = 16Mbyte - 32Kbyte */
91 #define SI2_ISA_ADDR_STEP SI2_ISA_WINDOW_LEN/* ISA board address step */
92 #define SI2_ISA_IRQ_MASK 0x9800 /* IRQs 15,12,11 */
93
94 /* ISA board, register definitions... */
95 #define SI2_ISA_ID_BASE 0x7FF8 /* READ: Board ID string */
96 #define SI2_ISA_RESET SI2_ISA_ID_BASE /* WRITE: Host Reset */
97 #define SI2_ISA_IRQ11 (SI2_ISA_ID_BASE+1) /* WRITE: Set IRQ11 */
98 #define SI2_ISA_IRQ12 (SI2_ISA_ID_BASE+2) /* WRITE: Set IRQ12 */
99 #define SI2_ISA_IRQ15 (SI2_ISA_ID_BASE+3) /* WRITE: Set IRQ15 */
100 #define SI2_ISA_IRQSET (SI2_ISA_ID_BASE+4) /* WRITE: Set Host Interrupt */
101 #define SI2_ISA_INTCLEAR (SI2_ISA_ID_BASE+5) /* WRITE: Enable Host Interrupt */
102
103 #define SI2_ISA_IRQ11_SET 0x10
104 #define SI2_ISA_IRQ11_CLEAR 0x00
105 #define SI2_ISA_IRQ12_SET 0x10
106 #define SI2_ISA_IRQ12_CLEAR 0x00
107 #define SI2_ISA_IRQ15_SET 0x10
108 #define SI2_ISA_IRQ15_CLEAR 0x00
109 #define SI2_ISA_INTCLEAR_SET 0x10
110 #define SI2_ISA_INTCLEAR_CLEAR 0x00
111 #define SI2_ISA_IRQSET_CLEAR 0x10
112 #define SI2_ISA_IRQSET_SET 0x00
113 #define SI2_ISA_RESET_SET 0x00
114 #define SI2_ISA_RESET_CLEAR 0x10
115
116 /* PCI board details... */
117 #define SI2_PCI_WINDOW_LEN 0x100000 /* 1 Mbyte memory window */
118
119 /* PCI board register definitions... */
120 #define SI2_PCI_SET_IRQ 0x40001 /* Set Host Interrupt */
121 #define SI2_PCI_RESET 0xC0001 /* Host Reset */
122
123 /*****************************************************************************
124 ****************************** ******************************
125 ****************************** Phase 3 T225 ******************************
126 ****************************** ******************************
127 *****************************************************************************/
128
129 /* General board details... */
130 #define SX_WINDOW_LEN 64*1024 /* 64 Kbyte memory window */
131
132 /* ISA board details... */
133 #define SX_ISA_ADDR_LOW 0x0A0000 /* Lowest address = 640 Kbyte */
134 #define SX_ISA_ADDR_HIGH 0xFF8000 /* Highest address = 16Mbyte - 32Kbyte */
135 #define SX_ISA_ADDR_STEP SX_WINDOW_LEN /* ISA board address step */
136 #define SX_ISA_IRQ_MASK 0x9E00 /* IRQs 15,12,11,10,9 */
137
138 /* Hardware register definitions... */
139 #define SX_EVENT_STATUS 0x7800 /* READ: T225 Event Status */
140 #define SX_EVENT_STROBE 0x7800 /* WRITE: T225 Event Strobe */
141 #define SX_EVENT_ENABLE 0x7880 /* WRITE: T225 Event Enable */
142 #define SX_VPD_ROM 0x7C00 /* READ: Vital Product Data ROM */
143 #define SX_CONFIG 0x7C00 /* WRITE: Host Configuration Register */
144 #define SX_IRQ_STATUS 0x7C80 /* READ: Host Interrupt Status */
145 #define SX_SET_IRQ 0x7C80 /* WRITE: Set Host Interrupt */
146 #define SX_RESET_STATUS 0x7D00 /* READ: Host Reset Status */
147 #define SX_RESET 0x7D00 /* WRITE: Host Reset */
148 #define SX_RESET_IRQ 0x7D80 /* WRITE: Reset Host Interrupt */
149
150 /* SX_VPD_ROM definitions... */
151 #define SX_VPD_SLX_ID1 0x00
152 #define SX_VPD_SLX_ID2 0x01
153 #define SX_VPD_HW_REV 0x02
154 #define SX_VPD_HW_ASSEM 0x03
155 #define SX_VPD_UNIQUEID4 0x04
156 #define SX_VPD_UNIQUEID3 0x05
157 #define SX_VPD_UNIQUEID2 0x06
158 #define SX_VPD_UNIQUEID1 0x07
159 #define SX_VPD_MANU_YEAR 0x08
160 #define SX_VPD_MANU_WEEK 0x09
161 #define SX_VPD_IDENT 0x10
162 #define SX_VPD_IDENT_STRING "JET HOST BY KEV#"
163
164 /* SX unique identifiers... */
165 #define SX_UNIQUEID_MASK 0xF0
166 #define SX_ISA_UNIQUEID1 0x20
167 #define SX_PCI_UNIQUEID1 0x50
168
169 /* SX_CONFIG definitions... */
170 #define SX_CONF_BUSEN 0x02 /* Enable T225 memory and I/O */
171 #define SX_CONF_HOSTIRQ 0x04 /* Enable board to host interrupt */
172
173 /* SX bootstrap... */
174 #define SX_BOOTSTRAP "\x28\x20\x21\x02\x60\x0a"
175 #define SX_BOOTSTRAP_SIZE 6
176 #define SX_BOOTSTRAP_ADDR (0x8000-SX_BOOTSTRAP_SIZE)
177
178 /*****************************************************************************
179 ********************************** **********************************
180 ********************************** EISA **********************************
181 ********************************** **********************************
182 *****************************************************************************/
183
184 #define SI2_EISA_OFF 0x42
185 #define SI2_EISA_VAL 0x01
186 #define SI2_EISA_WINDOW_LEN 0x10000
187
188 /*****************************************************************************
189 *********************************** **********************************
190 *********************************** PCI **********************************
191 *********************************** **********************************
192 *****************************************************************************/
193
194 /* General definitions... */
195
196 #define SPX_VENDOR_ID 0x11CB /* Assigned by the PCI SIG */
197 #define SPX_DEVICE_ID 0x4000 /* SI/XIO boards */
198 #define SPX_PLXDEVICE_ID 0x2000 /* SX boards */
199
200 #define SPX_SUB_VENDOR_ID SPX_VENDOR_ID /* Same as vendor id */
201 #define SI2_SUB_SYS_ID 0x400 /* Phase 2 (Z280) board */
202 #define SX_SUB_SYS_ID 0x200 /* Phase 3 (t225) board */
203
204 #endif /*_sxboards_h */
205
206 /* End of SXBOARDS.H */
207
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