1 /*
2 ** -----------------------------------------------------------------------------
3 **
4 ** Perle Specialix driver for Linux
5 ** Ported from existing RIO Driver for SCO sources.
6 *
7 * (C) 1990 - 2000 Specialix International Ltd., Byfleet, Surrey, UK.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 **
23 ** Module : board.h
24 ** SID : 1.2
25 ** Last Modified : 11/6/98 11:34:07
26 ** Retrieved : 11/6/98 11:34:20
27 **
28 ** ident @(#)board.h 1.2
29 **
30 ** -----------------------------------------------------------------------------
31 */
32
33 #ifndef __rio_board_h__
34 #define __rio_board_h__
35
36 #ifdef SCCS_LABELS
37 static char *_board_h_sccs_ = "@(#)board.h 1.2";
38 #endif
39
40 /*
41 ** board.h contains the definitions for the *hardware* of the host cards.
42 ** It describes the memory overlay for the dual port RAM area.
43 */
44
45 #define DP_SRAM1_SIZE 0x7C00
46 #define DP_SRAM2_SIZE 0x0200
47 #define DP_SRAM3_SIZE 0x7000
48 #define DP_SCRATCH_SIZE 0x1000
49 #define DP_PARMMAP_ADDR 0x01FE /* offset into SRAM2 */
50 #define DP_STARTUP_ADDR 0x01F8 /* offset into SRAM2 */
51
52 /*
53 ** The shape of the Host Control area, at offset 0x7C00, Write Only
54 */
55 struct s_Ctrl
56 {
57 BYTE DpCtl; /* 7C00 */
58 BYTE Dp_Unused2_[127];
59 BYTE DpIntSet; /* 7C80 */
60 BYTE Dp_Unused3_[127];
61 BYTE DpTpuReset; /* 7D00 */
62 BYTE Dp_Unused4_[127];
63 BYTE DpIntReset; /* 7D80 */
64 BYTE Dp_Unused5_[127];
65 };
66
67 /*
68 ** The PROM data area on the host (0x7C00), Read Only
69 */
70 struct s_Prom
71 {
72 WORD DpSlxCode[2];
73 WORD DpRev;
74 WORD Dp_Unused6_;
75 WORD DpUniq[4];
76 WORD DpJahre;
77 WORD DpWoche;
78 WORD DpHwFeature[5];
79 WORD DpOemId;
80 WORD DpSiggy[16];
81 };
82
83 /*
84 ** Union of the Ctrl and Prom areas
85 */
86 union u_CtrlProm /* This is the control/PROM area (0x7C00) */
87 {
88 struct s_Ctrl DpCtrl;
89 struct s_Prom DpProm;
90 };
91
92 /*
93 ** The top end of memory!
94 */
95 struct s_ParmMapS /* Area containing Parm Map Pointer */
96 {
97 BYTE Dp_Unused8_[DP_PARMMAP_ADDR];
98 WORD DpParmMapAd;
99 };
100
101 struct s_StartUpS
102 {
103 BYTE Dp_Unused9_[DP_STARTUP_ADDR];
104 BYTE Dp_LongJump[0x4];
105 BYTE Dp_Unused10_[2];
106 BYTE Dp_ShortJump[0x2];
107 };
108
109 union u_Sram2ParmMap /* This is the top of memory (0x7E00-0x7FFF) */
110 {
111 BYTE DpSramMem[DP_SRAM2_SIZE];
112 struct s_ParmMapS DpParmMapS;
113 struct s_StartUpS DpStartUpS;
114 };
115
116 /*
117 ** This is the DP RAM overlay.
118 */
119 struct DpRam
120 {
121 BYTE DpSram1[DP_SRAM1_SIZE]; /* 0000 - 7BFF */
122 union u_CtrlProm DpCtrlProm; /* 7C00 - 7DFF */
123 union u_Sram2ParmMap DpSram2ParmMap; /* 7E00 - 7FFF */
124 BYTE DpScratch[DP_SCRATCH_SIZE]; /* 8000 - 8FFF */
125 BYTE DpSram3[DP_SRAM3_SIZE]; /* 9000 - FFFF */
126 };
127
128 #define DpControl DpCtrlProm.DpCtrl.DpCtl
129 #define DpSetInt DpCtrlProm.DpCtrl.DpIntSet
130 #define DpResetTpu DpCtrlProm.DpCtrl.DpTpuReset
131 #define DpResetInt DpCtrlProm.DpCtrl.DpIntReset
132
133 #define DpSlx DpCtrlProm.DpProm.DpSlxCode
134 #define DpRevision DpCtrlProm.DpProm.DpRev
135 #define DpUnique DpCtrlProm.DpProm.DpUniq
136 #define DpYear DpCtrlProm.DpProm.DpJahre
137 #define DpWeek DpCtrlProm.DpProm.DpWoche
138 #define DpSignature DpCtrlProm.DpProm.DpSiggy
139
140 #define DpParmMapR DpSram2ParmMap.DpParmMapS.DpParmMapAd
141 #define DpSram2 DpSram2ParmMap.DpSramMem
142
143 #endif
144
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