1 /* i830_drv.h -- Private header for the I830 driver -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
28 * Jeff Hartmann <jhartmann@valinux.com>
29 *
30 */
31
32 #ifndef _I830_DRV_H_
33 #define _I830_DRV_H_
34
35 /* General customization:
36 */
37
38 #define DRIVER_AUTHOR "VA Linux Systems Inc."
39
40 #define DRIVER_NAME "i830"
41 #define DRIVER_DESC "Intel 830M"
42 #define DRIVER_DATE "20021108"
43
44 /* Interface history:
45 *
46 * 1.1: Original.
47 * 1.2: ?
48 * 1.3: New irq emit/wait ioctls.
49 * New pageflip ioctl.
50 * New getparam ioctl.
51 * State for texunits 3&4 in sarea.
52 * New (alternative) layout for texture state.
53 */
54 #define DRIVER_MAJOR 1
55 #define DRIVER_MINOR 3
56 #define DRIVER_PATCHLEVEL 2
57
58 /* Driver will work either way: IRQ's save cpu time when waiting for
59 * the card, but are subject to subtle interactions between bios,
60 * hardware and the driver.
61 */
62 /* XXX: Add vblank support? */
63 #define USE_IRQS 0
64
65 typedef struct drm_i830_buf_priv {
66 u32 *in_use;
67 int my_use_idx;
68 int currently_mapped;
69 void __user *virtual;
70 void *kernel_virtual;
71 } drm_i830_buf_priv_t;
72
73 typedef struct _drm_i830_ring_buffer{
74 int tail_mask;
75 unsigned long Start;
76 unsigned long End;
77 unsigned long Size;
78 u8 *virtual_start;
79 int head;
80 int tail;
81 int space;
82 } drm_i830_ring_buffer_t;
83
84 typedef struct drm_i830_private {
85 drm_map_t *sarea_map;
86 drm_map_t *mmio_map;
87
88 drm_i830_sarea_t *sarea_priv;
89 drm_i830_ring_buffer_t ring;
90
91 void * hw_status_page;
92 unsigned long counter;
93
94 dma_addr_t dma_status_page;
95
96 drm_buf_t *mmap_buffer;
97
98 u32 front_di1, back_di1, zi1;
99
100 int back_offset;
101 int depth_offset;
102 int front_offset;
103 int w, h;
104 int pitch;
105 int back_pitch;
106 int depth_pitch;
107 unsigned int cpp;
108
109 int do_boxes;
110 int dma_used;
111
112 int current_page;
113 int page_flipping;
114
115 wait_queue_head_t irq_queue;
116 atomic_t irq_received;
117 atomic_t irq_emitted;
118
119 int use_mi_batchbuffer_start;
120
121 } drm_i830_private_t;
122
123 /* i830_dma.c */
124 extern int i830_dma_schedule(drm_device_t *dev, int locked);
125 extern int i830_getbuf(struct inode *inode, struct file *filp,
126 unsigned int cmd, unsigned long arg);
127 extern int i830_dma_init(struct inode *inode, struct file *filp,
128 unsigned int cmd, unsigned long arg);
129 extern int i830_dma_cleanup(drm_device_t *dev);
130 extern int i830_flush_ioctl(struct inode *inode, struct file *filp,
131 unsigned int cmd, unsigned long arg);
132 extern void i830_reclaim_buffers(drm_device_t *dev, struct file *filp);
133 extern int i830_getage(struct inode *inode, struct file *filp, unsigned int cmd,
134 unsigned long arg);
135 extern int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma);
136 extern int i830_copybuf(struct inode *inode, struct file *filp,
137 unsigned int cmd, unsigned long arg);
138 extern int i830_docopy(struct inode *inode, struct file *filp,
139 unsigned int cmd, unsigned long arg);
140
141 extern void i830_dma_quiescent(drm_device_t *dev);
142
143 extern int i830_dma_vertex(struct inode *inode, struct file *filp,
144 unsigned int cmd, unsigned long arg);
145
146 extern int i830_swap_bufs(struct inode *inode, struct file *filp,
147 unsigned int cmd, unsigned long arg);
148
149 extern int i830_clear_bufs(struct inode *inode, struct file *filp,
150 unsigned int cmd, unsigned long arg);
151
152 extern int i830_flip_bufs(struct inode *inode, struct file *filp,
153 unsigned int cmd, unsigned long arg);
154
155 extern int i830_getparam( struct inode *inode, struct file *filp,
156 unsigned int cmd, unsigned long arg );
157
158 extern int i830_setparam( struct inode *inode, struct file *filp,
159 unsigned int cmd, unsigned long arg );
160
161 /* i830_irq.c */
162 extern int i830_irq_emit( struct inode *inode, struct file *filp,
163 unsigned int cmd, unsigned long arg );
164 extern int i830_irq_wait( struct inode *inode, struct file *filp,
165 unsigned int cmd, unsigned long arg );
166 extern int i830_wait_irq(drm_device_t *dev, int irq_nr);
167 extern int i830_emit_irq(drm_device_t *dev);
168
169 extern irqreturn_t i830_driver_irq_handler( DRM_IRQ_ARGS );
170 extern void i830_driver_irq_preinstall( drm_device_t *dev );
171 extern void i830_driver_irq_postinstall( drm_device_t *dev );
172 extern void i830_driver_irq_uninstall( drm_device_t *dev );
173 extern void i830_driver_pretakedown(drm_device_t *dev);
174 extern void i830_driver_release(drm_device_t *dev, struct file *filp);
175 extern int i830_driver_dma_quiescent(drm_device_t *dev);
176
177 #define I830_BASE(reg) ((unsigned long) \
178 dev_priv->mmio_map->handle)
179 #define I830_ADDR(reg) (I830_BASE(reg) + reg)
180 #define I830_DEREF(reg) *(__volatile__ unsigned int *)I830_ADDR(reg)
181 #define I830_READ(reg) readl((volatile u32 *)I830_ADDR(reg))
182 #define I830_WRITE(reg,val) writel(val, (volatile u32 *)I830_ADDR(reg))
183 #define I830_DEREF16(reg) *(__volatile__ u16 *)I830_ADDR(reg)
184 #define I830_READ16(reg) I830_DEREF16(reg)
185 #define I830_WRITE16(reg,val) do { I830_DEREF16(reg) = val; } while (0)
186
187
188
189 #define I830_VERBOSE 0
190
191 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
192 volatile char *virt;
193
194 #define BEGIN_LP_RING(n) do { \
195 if (I830_VERBOSE) \
196 printk("BEGIN_LP_RING(%d) in %s\n", \
197 n, __FUNCTION__); \
198 if (dev_priv->ring.space < n*4) \
199 i830_wait_ring(dev, n*4, __FUNCTION__); \
200 outcount = 0; \
201 outring = dev_priv->ring.tail; \
202 ringmask = dev_priv->ring.tail_mask; \
203 virt = dev_priv->ring.virtual_start; \
204 } while (0)
205
206
207 #define OUT_RING(n) do { \
208 if (I830_VERBOSE) printk(" OUT_RING %x\n", (int)(n)); \
209 *(volatile unsigned int *)(virt + outring) = n; \
210 outcount++; \
211 outring += 4; \
212 outring &= ringmask; \
213 } while (0)
214
215 #define ADVANCE_LP_RING() do { \
216 if (I830_VERBOSE) printk("ADVANCE_LP_RING %x\n", outring); \
217 dev_priv->ring.tail = outring; \
218 dev_priv->ring.space -= outcount * 4; \
219 I830_WRITE(LP_RING + RING_TAIL, outring); \
220 } while(0)
221
222 extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller);
223
224
225 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
226 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
227 #define CMD_REPORT_HEAD (7<<23)
228 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
229 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
230
231 #define STATE3D_LOAD_STATE_IMMEDIATE_2 ((0x3<<29)|(0x1d<<24)|(0x03<<16))
232 #define LOAD_TEXTURE_MAP0 (1<<11)
233
234 #define INST_PARSER_CLIENT 0x00000000
235 #define INST_OP_FLUSH 0x02000000
236 #define INST_FLUSH_MAP_CACHE 0x00000001
237
238
239 #define BB1_START_ADDR_MASK (~0x7)
240 #define BB1_PROTECTED (1<<0)
241 #define BB1_UNPROTECTED (0<<0)
242 #define BB2_END_ADDR_MASK (~0x7)
243
244 #define I830REG_HWSTAM 0x02098
245 #define I830REG_INT_IDENTITY_R 0x020a4
246 #define I830REG_INT_MASK_R 0x020a8
247 #define I830REG_INT_ENABLE_R 0x020a0
248
249 #define I830_IRQ_RESERVED ((1<<13)|(3<<2))
250
251
252 #define LP_RING 0x2030
253 #define HP_RING 0x2040
254 #define RING_TAIL 0x00
255 #define TAIL_ADDR 0x001FFFF8
256 #define RING_HEAD 0x04
257 #define HEAD_WRAP_COUNT 0xFFE00000
258 #define HEAD_WRAP_ONE 0x00200000
259 #define HEAD_ADDR 0x001FFFFC
260 #define RING_START 0x08
261 #define START_ADDR 0x0xFFFFF000
262 #define RING_LEN 0x0C
263 #define RING_NR_PAGES 0x001FF000
264 #define RING_REPORT_MASK 0x00000006
265 #define RING_REPORT_64K 0x00000002
266 #define RING_REPORT_128K 0x00000004
267 #define RING_NO_REPORT 0x00000000
268 #define RING_VALID_MASK 0x00000001
269 #define RING_VALID 0x00000001
270 #define RING_INVALID 0x00000000
271
272 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
273 #define SC_UPDATE_SCISSOR (0x1<<1)
274 #define SC_ENABLE_MASK (0x1<<0)
275 #define SC_ENABLE (0x1<<0)
276
277 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
278 #define SCI_YMIN_MASK (0xffff<<16)
279 #define SCI_XMIN_MASK (0xffff<<0)
280 #define SCI_YMAX_MASK (0xffff<<16)
281 #define SCI_XMAX_MASK (0xffff<<0)
282
283 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
284 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
285 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
286 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
287 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
288 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
289 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
290 #define GFX_OP_PRIMITIVE ((0x3<<29)|(0x1f<<24))
291
292 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
293
294 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
295 #define ASYNC_FLIP (1<<22)
296
297 #define CMD_3D (0x3<<29)
298 #define STATE3D_CONST_BLEND_COLOR_CMD (CMD_3D|(0x1d<<24)|(0x88<<16))
299 #define STATE3D_MAP_COORD_SETBIND_CMD (CMD_3D|(0x1d<<24)|(0x02<<16))
300
301 #define BR00_BITBLT_CLIENT 0x40000000
302 #define BR00_OP_COLOR_BLT 0x10000000
303 #define BR00_OP_SRC_COPY_BLT 0x10C00000
304 #define BR13_SOLID_PATTERN 0x80000000
305
306 #define BUF_3D_ID_COLOR_BACK (0x3<<24)
307 #define BUF_3D_ID_DEPTH (0x7<<24)
308 #define BUF_3D_USE_FENCE (1<<23)
309 #define BUF_3D_PITCH(x) (((x)/4)<<2)
310
311 #define CMD_OP_MAP_PALETTE_LOAD ((3<<29)|(0x1d<<24)|(0x82<<16)|255)
312 #define MAP_PALETTE_NUM(x) ((x<<8) & (1<<8))
313 #define MAP_PALETTE_BOTH (1<<11)
314
315 #define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|0x4)
316 #define XY_COLOR_BLT_WRITE_ALPHA (1<<21)
317 #define XY_COLOR_BLT_WRITE_RGB (1<<20)
318
319 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
320 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
321 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
322
323 #define MI_BATCH_BUFFER ((0x30<<23)|1)
324 #define MI_BATCH_BUFFER_START (0x31<<23)
325 #define MI_BATCH_BUFFER_END (0xA<<23)
326 #define MI_BATCH_NON_SECURE (1)
327
328 #define MI_WAIT_FOR_EVENT ((0x3<<23))
329 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
330 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
331
332 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
333
334 #endif
335
336
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