Linux kernel & device driver programming

Cross-Referenced Linux and Device Driver Code

[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ]
Version: [ 2.6.11.8 ] [ 2.6.25 ] [ 2.6.25.8 ] [ 2.6.31.13 ] Architecture: [ i386 ]
  1 /*
  2  * Serverworks AGPGART routines.
  3  */
  4 
  5 #include <linux/module.h>
  6 #include <linux/pci.h>
  7 #include <linux/init.h>
  8 #include <linux/string.h>
  9 #include <linux/slab.h>
 10 #include <linux/jiffies.h>
 11 #include <linux/agp_backend.h>
 12 #include "agp.h"
 13 
 14 #define SVWRKS_COMMAND          0x04
 15 #define SVWRKS_APSIZE           0x10
 16 #define SVWRKS_MMBASE           0x14
 17 #define SVWRKS_CACHING          0x4b
 18 #define SVWRKS_AGP_ENABLE       0x60
 19 #define SVWRKS_FEATURE          0x68
 20 
 21 #define SVWRKS_SIZE_MASK        0xfe000000
 22 
 23 /* Memory mapped registers */
 24 #define SVWRKS_GART_CACHE       0x02
 25 #define SVWRKS_GATTBASE         0x04
 26 #define SVWRKS_TLBFLUSH         0x10
 27 #define SVWRKS_POSTFLUSH        0x14
 28 #define SVWRKS_DIRFLUSH         0x0c
 29 
 30 
 31 struct serverworks_page_map {
 32         unsigned long *real;
 33         unsigned long __iomem *remapped;
 34 };
 35 
 36 static struct _serverworks_private {
 37         struct pci_dev *svrwrks_dev;    /* device one */
 38         volatile u8 __iomem *registers;
 39         struct serverworks_page_map **gatt_pages;
 40         int num_tables;
 41         struct serverworks_page_map scratch_dir;
 42 
 43         int gart_addr_ofs;
 44         int mm_addr_ofs;
 45 } serverworks_private;
 46 
 47 static int serverworks_create_page_map(struct serverworks_page_map *page_map)
 48 {
 49         int i;
 50 
 51         page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
 52         if (page_map->real == NULL) {
 53                 return -ENOMEM;
 54         }
 55 
 56         set_memory_uc((unsigned long)page_map->real, 1);
 57         page_map->remapped = page_map->real;
 58 
 59         for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++)
 60                 writel(agp_bridge->scratch_page, page_map->remapped+i);
 61                 /* Red Pen: Everyone else does pci posting flush here */
 62 
 63         return 0;
 64 }
 65 
 66 static void serverworks_free_page_map(struct serverworks_page_map *page_map)
 67 {
 68         set_memory_wb((unsigned long)page_map->real, 1);
 69         free_page((unsigned long) page_map->real);
 70 }
 71 
 72 static void serverworks_free_gatt_pages(void)
 73 {
 74         int i;
 75         struct serverworks_page_map **tables;
 76         struct serverworks_page_map *entry;
 77 
 78         tables = serverworks_private.gatt_pages;
 79         for (i = 0; i < serverworks_private.num_tables; i++) {
 80                 entry = tables[i];
 81                 if (entry != NULL) {
 82                         if (entry->real != NULL) {
 83                                 serverworks_free_page_map(entry);
 84                         }
 85                         kfree(entry);
 86                 }
 87         }
 88         kfree(tables);
 89 }
 90 
 91 static int serverworks_create_gatt_pages(int nr_tables)
 92 {
 93         struct serverworks_page_map **tables;
 94         struct serverworks_page_map *entry;
 95         int retval = 0;
 96         int i;
 97 
 98         tables = kzalloc((nr_tables + 1) * sizeof(struct serverworks_page_map *),
 99                          GFP_KERNEL);
100         if (tables == NULL)
101                 return -ENOMEM;
102 
103         for (i = 0; i < nr_tables; i++) {
104                 entry = kzalloc(sizeof(struct serverworks_page_map), GFP_KERNEL);
105                 if (entry == NULL) {
106                         retval = -ENOMEM;
107                         break;
108                 }
109                 tables[i] = entry;
110                 retval = serverworks_create_page_map(entry);
111                 if (retval != 0) break;
112         }
113         serverworks_private.num_tables = nr_tables;
114         serverworks_private.gatt_pages = tables;
115 
116         if (retval != 0) serverworks_free_gatt_pages();
117 
118         return retval;
119 }
120 
121 #define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\
122         GET_PAGE_DIR_IDX(addr)]->remapped)
123 
124 #ifndef GET_PAGE_DIR_OFF
125 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
126 #endif
127 
128 #ifndef GET_PAGE_DIR_IDX
129 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
130         GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
131 #endif
132 
133 #ifndef GET_GATT_OFF
134 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
135 #endif
136 
137 static int serverworks_create_gatt_table(struct agp_bridge_data *bridge)
138 {
139         struct aper_size_info_lvl2 *value;
140         struct serverworks_page_map page_dir;
141         int retval;
142         u32 temp;
143         int i;
144 
145         value = A_SIZE_LVL2(agp_bridge->current_size);
146         retval = serverworks_create_page_map(&page_dir);
147         if (retval != 0) {
148                 return retval;
149         }
150         retval = serverworks_create_page_map(&serverworks_private.scratch_dir);
151         if (retval != 0) {
152                 serverworks_free_page_map(&page_dir);
153                 return retval;
154         }
155         /* Create a fake scratch directory */
156         for (i = 0; i < 1024; i++) {
157                 writel(agp_bridge->scratch_page, serverworks_private.scratch_dir.remapped+i);
158                 writel(virt_to_gart(serverworks_private.scratch_dir.real) | 1, page_dir.remapped+i);
159         }
160 
161         retval = serverworks_create_gatt_pages(value->num_entries / 1024);
162         if (retval != 0) {
163                 serverworks_free_page_map(&page_dir);
164                 serverworks_free_page_map(&serverworks_private.scratch_dir);
165                 return retval;
166         }
167 
168         agp_bridge->gatt_table_real = (u32 *)page_dir.real;
169         agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
170         agp_bridge->gatt_bus_addr = virt_to_gart(page_dir.real);
171 
172         /* Get the address for the gart region.
173          * This is a bus address even on the alpha, b/c its
174          * used to program the agp master not the cpu
175          */
176 
177         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
178         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
179 
180         /* Calculate the agp offset */
181         for (i = 0; i < value->num_entries / 1024; i++)
182                 writel(virt_to_gart(serverworks_private.gatt_pages[i]->real)|1, page_dir.remapped+i);
183 
184         return 0;
185 }
186 
187 static int serverworks_free_gatt_table(struct agp_bridge_data *bridge)
188 {
189         struct serverworks_page_map page_dir;
190 
191         page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
192         page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
193 
194         serverworks_free_gatt_pages();
195         serverworks_free_page_map(&page_dir);
196         serverworks_free_page_map(&serverworks_private.scratch_dir);
197         return 0;
198 }
199 
200 static int serverworks_fetch_size(void)
201 {
202         int i;
203         u32 temp;
204         u32 temp2;
205         struct aper_size_info_lvl2 *values;
206 
207         values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
208         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
209         pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
210                                         SVWRKS_SIZE_MASK);
211         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
212         pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
213         temp2 &= SVWRKS_SIZE_MASK;
214 
215         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
216                 if (temp2 == values[i].size_value) {
217                         agp_bridge->previous_size =
218                             agp_bridge->current_size = (void *) (values + i);
219 
220                         agp_bridge->aperture_size_idx = i;
221                         return values[i].size;
222                 }
223         }
224 
225         return 0;
226 }
227 
228 /*
229  * This routine could be implemented by taking the addresses
230  * written to the GATT, and flushing them individually.  However
231  * currently it just flushes the whole table.  Which is probably
232  * more efficent, since agp_memory blocks can be a large number of
233  * entries.
234  */
235 static void serverworks_tlbflush(struct agp_memory *temp)
236 {
237         unsigned long timeout;
238 
239         writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH);
240         timeout = jiffies + 3*HZ;
241         while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) {
242                 cpu_relax();
243                 if (time_after(jiffies, timeout)) {
244                         printk(KERN_ERR PFX "TLB post flush took more than 3 seconds\n");
245                         break;
246                 }
247         }
248 
249         writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH);
250         timeout = jiffies + 3*HZ;
251         while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) {
252                 cpu_relax();
253                 if (time_after(jiffies, timeout)) {
254                         printk(KERN_ERR PFX "TLB Dir flush took more than 3 seconds\n");
255                         break;
256                 }
257         }
258 }
259 
260 static int serverworks_configure(void)
261 {
262         struct aper_size_info_lvl2 *current_size;
263         u32 temp;
264         u8 enable_reg;
265         u16 cap_reg;
266 
267         current_size = A_SIZE_LVL2(agp_bridge->current_size);
268 
269         /* Get the memory mapped registers */
270         pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
271         temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
272         serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
273         if (!serverworks_private.registers) {
274                 printk (KERN_ERR PFX "Unable to ioremap() memory.\n");
275                 return -ENOMEM;
276         }
277 
278         writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE);
279         readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */
280 
281         writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE);
282         readl(serverworks_private.registers+SVWRKS_GATTBASE);   /* PCI Posting. */
283 
284         cap_reg = readw(serverworks_private.registers+SVWRKS_COMMAND);
285         cap_reg &= ~0x0007;
286         cap_reg |= 0x4;
287         writew(cap_reg, serverworks_private.registers+SVWRKS_COMMAND);
288         readw(serverworks_private.registers+SVWRKS_COMMAND);
289 
290         pci_read_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, &enable_reg);
291         enable_reg |= 0x1; /* Agp Enable bit */
292         pci_write_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, enable_reg);
293         serverworks_tlbflush(NULL);
294 
295         agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
296 
297         /* Fill in the mode register */
298         pci_read_config_dword(serverworks_private.svrwrks_dev,
299                               agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
300 
301         pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);
302         enable_reg &= ~0x3;
303         pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);
304 
305         pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);
306         enable_reg |= (1<<6);
307         pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);
308 
309         return 0;
310 }
311 
312 static void serverworks_cleanup(void)
313 {
314         iounmap((void __iomem *) serverworks_private.registers);
315 }
316 
317 static int serverworks_insert_memory(struct agp_memory *mem,
318                              off_t pg_start, int type)
319 {
320         int i, j, num_entries;
321         unsigned long __iomem *cur_gatt;
322         unsigned long addr;
323 
324         num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
325 
326         if (type != 0 || mem->type != 0) {
327                 return -EINVAL;
328         }
329         if ((pg_start + mem->page_count) > num_entries) {
330                 return -EINVAL;
331         }
332 
333         j = pg_start;
334         while (j < (pg_start + mem->page_count)) {
335                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
336                 cur_gatt = SVRWRKS_GET_GATT(addr);
337                 if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
338                         return -EBUSY;
339                 j++;
340         }
341 
342         if (mem->is_flushed == FALSE) {
343                 global_cache_flush();
344                 mem->is_flushed = TRUE;
345         }
346 
347         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
348                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
349                 cur_gatt = SVRWRKS_GET_GATT(addr);
350                 writel(agp_bridge->driver->mask_memory(agp_bridge, mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
351         }
352         serverworks_tlbflush(mem);
353         return 0;
354 }
355 
356 static int serverworks_remove_memory(struct agp_memory *mem, off_t pg_start,
357                              int type)
358 {
359         int i;
360         unsigned long __iomem *cur_gatt;
361         unsigned long addr;
362 
363         if (type != 0 || mem->type != 0) {
364                 return -EINVAL;
365         }
366 
367         global_cache_flush();
368         serverworks_tlbflush(mem);
369 
370         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
371                 addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
372                 cur_gatt = SVRWRKS_GET_GATT(addr);
373                 writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
374         }
375 
376         serverworks_tlbflush(mem);
377         return 0;
378 }
379 
380 static const struct gatt_mask serverworks_masks[] =
381 {
382         {.mask = 1, .type = 0}
383 };
384 
385 static const struct aper_size_info_lvl2 serverworks_sizes[7] =
386 {
387         {2048, 524288, 0x80000000},
388         {1024, 262144, 0xc0000000},
389         {512, 131072, 0xe0000000},
390         {256, 65536, 0xf0000000},
391         {128, 32768, 0xf8000000},
392         {64, 16384, 0xfc000000},
393         {32, 8192, 0xfe000000}
394 };
395 
396 static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode)
397 {
398         u32 command;
399 
400         pci_read_config_dword(serverworks_private.svrwrks_dev,
401                               bridge->capndx + PCI_AGP_STATUS,
402                               &command);
403 
404         command = agp_collect_device_status(bridge, mode, command);
405 
406         command &= ~0x10;       /* disable FW */
407         command &= ~0x08;
408 
409         command |= 0x100;
410 
411         pci_write_config_dword(serverworks_private.svrwrks_dev,
412                                bridge->capndx + PCI_AGP_COMMAND,
413                                command);
414 
415         agp_device_command(command, 0);
416 }
417 
418 static const struct agp_bridge_driver sworks_driver = {
419         .owner                  = THIS_MODULE,
420         .aperture_sizes         = serverworks_sizes,
421         .size_type              = LVL2_APER_SIZE,
422         .num_aperture_sizes     = 7,
423         .configure              = serverworks_configure,
424         .fetch_size             = serverworks_fetch_size,
425         .cleanup                = serverworks_cleanup,
426         .tlb_flush              = serverworks_tlbflush,
427         .mask_memory            = agp_generic_mask_memory,
428         .masks                  = serverworks_masks,
429         .agp_enable             = serverworks_agp_enable,
430         .cache_flush            = global_cache_flush,
431         .create_gatt_table      = serverworks_create_gatt_table,
432         .free_gatt_table        = serverworks_free_gatt_table,
433         .insert_memory          = serverworks_insert_memory,
434         .remove_memory          = serverworks_remove_memory,
435         .alloc_by_type          = agp_generic_alloc_by_type,
436         .free_by_type           = agp_generic_free_by_type,
437         .agp_alloc_page         = agp_generic_alloc_page,
438         .agp_destroy_page       = agp_generic_destroy_page,
439         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
440 };
441 
442 static int __devinit agp_serverworks_probe(struct pci_dev *pdev,
443                                            const struct pci_device_id *ent)
444 {
445         struct agp_bridge_data *bridge;
446         struct pci_dev *bridge_dev;
447         u32 temp, temp2;
448         u8 cap_ptr = 0;
449 
450         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
451 
452         switch (pdev->device) {
453         case 0x0006:
454                 printk (KERN_ERR PFX "ServerWorks CNB20HE is unsupported due to lack of documentation.\n");
455                 return -ENODEV;
456 
457         case PCI_DEVICE_ID_SERVERWORKS_HE:
458         case PCI_DEVICE_ID_SERVERWORKS_LE:
459         case 0x0007:
460                 break;
461 
462         default:
463                 if (cap_ptr)
464                         printk(KERN_ERR PFX "Unsupported Serverworks chipset "
465                                         "(device id: %04x)\n", pdev->device);
466                 return -ENODEV;
467         }
468 
469         /* Everything is on func 1 here so we are hardcoding function one */
470         bridge_dev = pci_get_bus_and_slot((unsigned int)pdev->bus->number,
471                         PCI_DEVFN(0, 1));
472         if (!bridge_dev) {
473                 printk(KERN_INFO PFX "Detected a Serverworks chipset "
474                        "but could not find the secondary device.\n");
475                 return -ENODEV;
476         }
477 
478         serverworks_private.svrwrks_dev = bridge_dev;
479         serverworks_private.gart_addr_ofs = 0x10;
480 
481         pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp);
482         if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
483                 pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2);
484                 if (temp2 != 0) {
485                         printk(KERN_INFO PFX "Detected 64 bit aperture address, "
486                                "but top bits are not zero.  Disabling agp\n");
487                         return -ENODEV;
488                 }
489                 serverworks_private.mm_addr_ofs = 0x18;
490         } else
491                 serverworks_private.mm_addr_ofs = 0x14;
492 
493         pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp);
494         if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
495                 pci_read_config_dword(pdev,
496                                 serverworks_private.mm_addr_ofs + 4, &temp2);
497                 if (temp2 != 0) {
498                         printk(KERN_INFO PFX "Detected 64 bit MMIO address, "
499                                "but top bits are not zero.  Disabling agp\n");
500                         return -ENODEV;
501                 }
502         }
503 
504         bridge = agp_alloc_bridge();
505         if (!bridge)
506                 return -ENOMEM;
507 
508         bridge->driver = &sworks_driver;
509         bridge->dev_private_data = &serverworks_private,
510         bridge->dev = pci_dev_get(pdev);
511 
512         pci_set_drvdata(pdev, bridge);
513         return agp_add_bridge(bridge);
514 }
515 
516 static void __devexit agp_serverworks_remove(struct pci_dev *pdev)
517 {
518         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
519 
520         pci_dev_put(bridge->dev);
521         agp_remove_bridge(bridge);
522         agp_put_bridge(bridge);
523         pci_dev_put(serverworks_private.svrwrks_dev);
524         serverworks_private.svrwrks_dev = NULL;
525 }
526 
527 static struct pci_device_id agp_serverworks_pci_table[] = {
528         {
529         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
530         .class_mask     = ~0,
531         .vendor         = PCI_VENDOR_ID_SERVERWORKS,
532         .device         = PCI_ANY_ID,
533         .subvendor      = PCI_ANY_ID,
534         .subdevice      = PCI_ANY_ID,
535         },
536         { }
537 };
538 
539 MODULE_DEVICE_TABLE(pci, agp_serverworks_pci_table);
540 
541 static struct pci_driver agp_serverworks_pci_driver = {
542         .name           = "agpgart-serverworks",
543         .id_table       = agp_serverworks_pci_table,
544         .probe          = agp_serverworks_probe,
545         .remove         = agp_serverworks_remove,
546 };
547 
548 static int __init agp_serverworks_init(void)
549 {
550         if (agp_off)
551                 return -EINVAL;
552         return pci_register_driver(&agp_serverworks_pci_driver);
553 }
554 
555 static void __exit agp_serverworks_cleanup(void)
556 {
557         pci_unregister_driver(&agp_serverworks_pci_driver);
558 }
559 
560 module_init(agp_serverworks_init);
561 module_exit(agp_serverworks_cleanup);
562 
563 MODULE_LICENSE("GPL and additional rights");
564 
565 
  This page was automatically generated by the LXR engine.