1 /*
2 * Intel AGPGART routines.
3 */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
11 #include "agp.h"
12
13 #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
14 #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
15 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
16 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
17 #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
18 #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
19 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
20 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
21 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
22 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
23 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
24 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
25 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
26 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
27 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
28 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
29 #define PCI_DEVICE_ID_INTEL_IGDGM_HB 0xA010
30 #define PCI_DEVICE_ID_INTEL_IGDGM_IG 0xA011
31 #define PCI_DEVICE_ID_INTEL_IGDG_HB 0xA000
32 #define PCI_DEVICE_ID_INTEL_IGDG_IG 0xA001
33 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
34 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
35 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
36 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
37 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
38 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
39 #define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40
40 #define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42
41 #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
42 #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
43 #define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
44 #define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
45 #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
46 #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
47 #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
48 #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
49 #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
50 #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
51 #define PCI_DEVICE_ID_INTEL_IGDNG_D_HB 0x0040
52 #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG 0x0042
53 #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB 0x0044
54 #define PCI_DEVICE_ID_INTEL_IGDNG_MA_HB 0x0062
55 #define PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB 0x006a
56 #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG 0x0046
57
58 /* cover 915 and 945 variants */
59 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
60 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
61 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
62 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
63 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
64 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
65
66 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
67 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
68 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
69 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
70 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
71 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
72
73 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
74 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
75 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
76 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
77 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
78
79 #define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
80 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
81
82 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
83 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
84 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
85 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
86 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
87 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
88 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \
89 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB || \
90 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB || \
91 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB)
92
93 extern int agp_memory_reserved;
94
95
96 /* Intel 815 register */
97 #define INTEL_815_APCONT 0x51
98 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
99
100 /* Intel i820 registers */
101 #define INTEL_I820_RDCR 0x51
102 #define INTEL_I820_ERRSTS 0xc8
103
104 /* Intel i840 registers */
105 #define INTEL_I840_MCHCFG 0x50
106 #define INTEL_I840_ERRSTS 0xc8
107
108 /* Intel i850 registers */
109 #define INTEL_I850_MCHCFG 0x50
110 #define INTEL_I850_ERRSTS 0xc8
111
112 /* intel 915G registers */
113 #define I915_GMADDR 0x18
114 #define I915_MMADDR 0x10
115 #define I915_PTEADDR 0x1C
116 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
117 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
118 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
119 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
120 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
121 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
122 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
123 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
124
125 #define I915_IFPADDR 0x60
126
127 /* Intel 965G registers */
128 #define I965_MSAC 0x62
129 #define I965_IFPADDR 0x70
130
131 /* Intel 7505 registers */
132 #define INTEL_I7505_APSIZE 0x74
133 #define INTEL_I7505_NCAPID 0x60
134 #define INTEL_I7505_NISTAT 0x6c
135 #define INTEL_I7505_ATTBASE 0x78
136 #define INTEL_I7505_ERRSTS 0x42
137 #define INTEL_I7505_AGPCTRL 0x70
138 #define INTEL_I7505_MCHCFG 0x50
139
140 static const struct aper_size_info_fixed intel_i810_sizes[] =
141 {
142 {64, 16384, 4},
143 /* The 32M mode still requires a 64k gatt */
144 {32, 8192, 4}
145 };
146
147 #define AGP_DCACHE_MEMORY 1
148 #define AGP_PHYS_MEMORY 2
149 #define INTEL_AGP_CACHED_MEMORY 3
150
151 static struct gatt_mask intel_i810_masks[] =
152 {
153 {.mask = I810_PTE_VALID, .type = 0},
154 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
155 {.mask = I810_PTE_VALID, .type = 0},
156 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
157 .type = INTEL_AGP_CACHED_MEMORY}
158 };
159
160 static struct _intel_private {
161 struct pci_dev *pcidev; /* device one */
162 u8 __iomem *registers;
163 u32 __iomem *gtt; /* I915G */
164 int num_dcache_entries;
165 /* gtt_entries is the number of gtt entries that are already mapped
166 * to stolen memory. Stolen memory is larger than the memory mapped
167 * through gtt_entries, as it includes some reserved space for the BIOS
168 * popup and for the GTT.
169 */
170 int gtt_entries; /* i830+ */
171 union {
172 void __iomem *i9xx_flush_page;
173 void *i8xx_flush_page;
174 };
175 struct page *i8xx_page;
176 struct resource ifp_resource;
177 int resource_valid;
178 } intel_private;
179
180 static int intel_i810_fetch_size(void)
181 {
182 u32 smram_miscc;
183 struct aper_size_info_fixed *values;
184
185 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
186 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
187
188 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
189 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
190 return 0;
191 }
192 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
193 agp_bridge->previous_size =
194 agp_bridge->current_size = (void *) (values + 1);
195 agp_bridge->aperture_size_idx = 1;
196 return values[1].size;
197 } else {
198 agp_bridge->previous_size =
199 agp_bridge->current_size = (void *) (values);
200 agp_bridge->aperture_size_idx = 0;
201 return values[0].size;
202 }
203
204 return 0;
205 }
206
207 static int intel_i810_configure(void)
208 {
209 struct aper_size_info_fixed *current_size;
210 u32 temp;
211 int i;
212
213 current_size = A_SIZE_FIX(agp_bridge->current_size);
214
215 if (!intel_private.registers) {
216 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
217 temp &= 0xfff80000;
218
219 intel_private.registers = ioremap(temp, 128 * 4096);
220 if (!intel_private.registers) {
221 dev_err(&intel_private.pcidev->dev,
222 "can't remap memory\n");
223 return -ENOMEM;
224 }
225 }
226
227 if ((readl(intel_private.registers+I810_DRAM_CTL)
228 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
229 /* This will need to be dynamically assigned */
230 dev_info(&intel_private.pcidev->dev,
231 "detected 4MB dedicated video ram\n");
232 intel_private.num_dcache_entries = 1024;
233 }
234 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
235 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
236 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
237 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
238
239 if (agp_bridge->driver->needs_scratch_page) {
240 for (i = 0; i < current_size->num_entries; i++) {
241 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
242 }
243 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
244 }
245 global_cache_flush();
246 return 0;
247 }
248
249 static void intel_i810_cleanup(void)
250 {
251 writel(0, intel_private.registers+I810_PGETBL_CTL);
252 readl(intel_private.registers); /* PCI Posting. */
253 iounmap(intel_private.registers);
254 }
255
256 static void intel_i810_tlbflush(struct agp_memory *mem)
257 {
258 return;
259 }
260
261 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
262 {
263 return;
264 }
265
266 /* Exists to support ARGB cursors */
267 static struct page *i8xx_alloc_pages(void)
268 {
269 struct page *page;
270
271 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
272 if (page == NULL)
273 return NULL;
274
275 if (set_pages_uc(page, 4) < 0) {
276 set_pages_wb(page, 4);
277 __free_pages(page, 2);
278 return NULL;
279 }
280 get_page(page);
281 atomic_inc(&agp_bridge->current_memory_agp);
282 return page;
283 }
284
285 static void i8xx_destroy_pages(struct page *page)
286 {
287 if (page == NULL)
288 return;
289
290 set_pages_wb(page, 4);
291 put_page(page);
292 __free_pages(page, 2);
293 atomic_dec(&agp_bridge->current_memory_agp);
294 }
295
296 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
297 int type)
298 {
299 if (type < AGP_USER_TYPES)
300 return type;
301 else if (type == AGP_USER_CACHED_MEMORY)
302 return INTEL_AGP_CACHED_MEMORY;
303 else
304 return 0;
305 }
306
307 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
308 int type)
309 {
310 int i, j, num_entries;
311 void *temp;
312 int ret = -EINVAL;
313 int mask_type;
314
315 if (mem->page_count == 0)
316 goto out;
317
318 temp = agp_bridge->current_size;
319 num_entries = A_SIZE_FIX(temp)->num_entries;
320
321 if ((pg_start + mem->page_count) > num_entries)
322 goto out_err;
323
324
325 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
326 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
327 ret = -EBUSY;
328 goto out_err;
329 }
330 }
331
332 if (type != mem->type)
333 goto out_err;
334
335 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
336
337 switch (mask_type) {
338 case AGP_DCACHE_MEMORY:
339 if (!mem->is_flushed)
340 global_cache_flush();
341 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
342 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
343 intel_private.registers+I810_PTE_BASE+(i*4));
344 }
345 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
346 break;
347 case AGP_PHYS_MEMORY:
348 case AGP_NORMAL_MEMORY:
349 if (!mem->is_flushed)
350 global_cache_flush();
351 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
352 writel(agp_bridge->driver->mask_memory(agp_bridge,
353 mem->pages[i],
354 mask_type),
355 intel_private.registers+I810_PTE_BASE+(j*4));
356 }
357 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
358 break;
359 default:
360 goto out_err;
361 }
362
363 agp_bridge->driver->tlb_flush(mem);
364 out:
365 ret = 0;
366 out_err:
367 mem->is_flushed = true;
368 return ret;
369 }
370
371 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
372 int type)
373 {
374 int i;
375
376 if (mem->page_count == 0)
377 return 0;
378
379 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
380 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
381 }
382 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
383
384 agp_bridge->driver->tlb_flush(mem);
385 return 0;
386 }
387
388 /*
389 * The i810/i830 requires a physical address to program its mouse
390 * pointer into hardware.
391 * However the Xserver still writes to it through the agp aperture.
392 */
393 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
394 {
395 struct agp_memory *new;
396 struct page *page;
397
398 switch (pg_count) {
399 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
400 break;
401 case 4:
402 /* kludge to get 4 physical pages for ARGB cursor */
403 page = i8xx_alloc_pages();
404 break;
405 default:
406 return NULL;
407 }
408
409 if (page == NULL)
410 return NULL;
411
412 new = agp_create_memory(pg_count);
413 if (new == NULL)
414 return NULL;
415
416 new->pages[0] = page;
417 if (pg_count == 4) {
418 /* kludge to get 4 physical pages for ARGB cursor */
419 new->pages[1] = new->pages[0] + 1;
420 new->pages[2] = new->pages[1] + 1;
421 new->pages[3] = new->pages[2] + 1;
422 }
423 new->page_count = pg_count;
424 new->num_scratch_pages = pg_count;
425 new->type = AGP_PHYS_MEMORY;
426 new->physical = page_to_phys(new->pages[0]);
427 return new;
428 }
429
430 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
431 {
432 struct agp_memory *new;
433
434 if (type == AGP_DCACHE_MEMORY) {
435 if (pg_count != intel_private.num_dcache_entries)
436 return NULL;
437
438 new = agp_create_memory(1);
439 if (new == NULL)
440 return NULL;
441
442 new->type = AGP_DCACHE_MEMORY;
443 new->page_count = pg_count;
444 new->num_scratch_pages = 0;
445 agp_free_page_array(new);
446 return new;
447 }
448 if (type == AGP_PHYS_MEMORY)
449 return alloc_agpphysmem_i8xx(pg_count, type);
450 return NULL;
451 }
452
453 static void intel_i810_free_by_type(struct agp_memory *curr)
454 {
455 agp_free_key(curr->key);
456 if (curr->type == AGP_PHYS_MEMORY) {
457 if (curr->page_count == 4)
458 i8xx_destroy_pages(curr->pages[0]);
459 else {
460 agp_bridge->driver->agp_destroy_page(curr->pages[0],
461 AGP_PAGE_DESTROY_UNMAP);
462 agp_bridge->driver->agp_destroy_page(curr->pages[0],
463 AGP_PAGE_DESTROY_FREE);
464 }
465 agp_free_page_array(curr);
466 }
467 kfree(curr);
468 }
469
470 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
471 struct page *page, int type)
472 {
473 unsigned long addr = phys_to_gart(page_to_phys(page));
474 /* Type checking must be done elsewhere */
475 return addr | bridge->driver->masks[type].mask;
476 }
477
478 static struct aper_size_info_fixed intel_i830_sizes[] =
479 {
480 {128, 32768, 5},
481 /* The 64M mode still requires a 128k gatt */
482 {64, 16384, 5},
483 {256, 65536, 6},
484 {512, 131072, 7},
485 };
486
487 static void intel_i830_init_gtt_entries(void)
488 {
489 u16 gmch_ctrl;
490 int gtt_entries;
491 u8 rdct;
492 int local = 0;
493 static const int ddt[4] = { 0, 16, 32, 64 };
494 int size; /* reserved space (in kb) at the top of stolen memory */
495
496 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
497
498 if (IS_I965) {
499 u32 pgetbl_ctl;
500 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
501
502 /* The 965 has a field telling us the size of the GTT,
503 * which may be larger than what is necessary to map the
504 * aperture.
505 */
506 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
507 case I965_PGETBL_SIZE_128KB:
508 size = 128;
509 break;
510 case I965_PGETBL_SIZE_256KB:
511 size = 256;
512 break;
513 case I965_PGETBL_SIZE_512KB:
514 size = 512;
515 break;
516 case I965_PGETBL_SIZE_1MB:
517 size = 1024;
518 break;
519 case I965_PGETBL_SIZE_2MB:
520 size = 2048;
521 break;
522 case I965_PGETBL_SIZE_1_5MB:
523 size = 1024 + 512;
524 break;
525 default:
526 dev_info(&intel_private.pcidev->dev,
527 "unknown page table size, assuming 512KB\n");
528 size = 512;
529 }
530 size += 4; /* add in BIOS popup space */
531 } else if (IS_G33 && !IS_IGD) {
532 /* G33's GTT size defined in gmch_ctrl */
533 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
534 case G33_PGETBL_SIZE_1M:
535 size = 1024;
536 break;
537 case G33_PGETBL_SIZE_2M:
538 size = 2048;
539 break;
540 default:
541 dev_info(&agp_bridge->dev->dev,
542 "unknown page table size 0x%x, assuming 512KB\n",
543 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
544 size = 512;
545 }
546 size += 4;
547 } else if (IS_G4X || IS_IGD) {
548 /* On 4 series hardware, GTT stolen is separate from graphics
549 * stolen, ignore it in stolen gtt entries counting. However,
550 * 4KB of the stolen memory doesn't get mapped to the GTT.
551 */
552 size = 4;
553 } else {
554 /* On previous hardware, the GTT size was just what was
555 * required to map the aperture.
556 */
557 size = agp_bridge->driver->fetch_size() + 4;
558 }
559
560 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
561 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
562 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
563 case I830_GMCH_GMS_STOLEN_512:
564 gtt_entries = KB(512) - KB(size);
565 break;
566 case I830_GMCH_GMS_STOLEN_1024:
567 gtt_entries = MB(1) - KB(size);
568 break;
569 case I830_GMCH_GMS_STOLEN_8192:
570 gtt_entries = MB(8) - KB(size);
571 break;
572 case I830_GMCH_GMS_LOCAL:
573 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
574 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
575 MB(ddt[I830_RDRAM_DDT(rdct)]);
576 local = 1;
577 break;
578 default:
579 gtt_entries = 0;
580 break;
581 }
582 } else {
583 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
584 case I855_GMCH_GMS_STOLEN_1M:
585 gtt_entries = MB(1) - KB(size);
586 break;
587 case I855_GMCH_GMS_STOLEN_4M:
588 gtt_entries = MB(4) - KB(size);
589 break;
590 case I855_GMCH_GMS_STOLEN_8M:
591 gtt_entries = MB(8) - KB(size);
592 break;
593 case I855_GMCH_GMS_STOLEN_16M:
594 gtt_entries = MB(16) - KB(size);
595 break;
596 case I855_GMCH_GMS_STOLEN_32M:
597 gtt_entries = MB(32) - KB(size);
598 break;
599 case I915_GMCH_GMS_STOLEN_48M:
600 /* Check it's really I915G */
601 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
602 gtt_entries = MB(48) - KB(size);
603 else
604 gtt_entries = 0;
605 break;
606 case I915_GMCH_GMS_STOLEN_64M:
607 /* Check it's really I915G */
608 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
609 gtt_entries = MB(64) - KB(size);
610 else
611 gtt_entries = 0;
612 break;
613 case G33_GMCH_GMS_STOLEN_128M:
614 if (IS_G33 || IS_I965 || IS_G4X)
615 gtt_entries = MB(128) - KB(size);
616 else
617 gtt_entries = 0;
618 break;
619 case G33_GMCH_GMS_STOLEN_256M:
620 if (IS_G33 || IS_I965 || IS_G4X)
621 gtt_entries = MB(256) - KB(size);
622 else
623 gtt_entries = 0;
624 break;
625 case INTEL_GMCH_GMS_STOLEN_96M:
626 if (IS_I965 || IS_G4X)
627 gtt_entries = MB(96) - KB(size);
628 else
629 gtt_entries = 0;
630 break;
631 case INTEL_GMCH_GMS_STOLEN_160M:
632 if (IS_I965 || IS_G4X)
633 gtt_entries = MB(160) - KB(size);
634 else
635 gtt_entries = 0;
636 break;
637 case INTEL_GMCH_GMS_STOLEN_224M:
638 if (IS_I965 || IS_G4X)
639 gtt_entries = MB(224) - KB(size);
640 else
641 gtt_entries = 0;
642 break;
643 case INTEL_GMCH_GMS_STOLEN_352M:
644 if (IS_I965 || IS_G4X)
645 gtt_entries = MB(352) - KB(size);
646 else
647 gtt_entries = 0;
648 break;
649 default:
650 gtt_entries = 0;
651 break;
652 }
653 }
654 if (gtt_entries > 0) {
655 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
656 gtt_entries / KB(1), local ? "local" : "stolen");
657 gtt_entries /= KB(4);
658 } else {
659 dev_info(&agp_bridge->dev->dev,
660 "no pre-allocated video memory detected\n");
661 gtt_entries = 0;
662 }
663
664 intel_private.gtt_entries = gtt_entries;
665 }
666
667 static void intel_i830_fini_flush(void)
668 {
669 kunmap(intel_private.i8xx_page);
670 intel_private.i8xx_flush_page = NULL;
671 unmap_page_from_agp(intel_private.i8xx_page);
672
673 __free_page(intel_private.i8xx_page);
674 intel_private.i8xx_page = NULL;
675 }
676
677 static void intel_i830_setup_flush(void)
678 {
679 /* return if we've already set the flush mechanism up */
680 if (intel_private.i8xx_page)
681 return;
682
683 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
684 if (!intel_private.i8xx_page)
685 return;
686
687 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
688 if (!intel_private.i8xx_flush_page)
689 intel_i830_fini_flush();
690 }
691
692 static void
693 do_wbinvd(void *null)
694 {
695 wbinvd();
696 }
697
698 /* The chipset_flush interface needs to get data that has already been
699 * flushed out of the CPU all the way out to main memory, because the GPU
700 * doesn't snoop those buffers.
701 *
702 * The 8xx series doesn't have the same lovely interface for flushing the
703 * chipset write buffers that the later chips do. According to the 865
704 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
705 * that buffer out, we just fill 1KB and clflush it out, on the assumption
706 * that it'll push whatever was in there out. It appears to work.
707 */
708 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
709 {
710 unsigned int *pg = intel_private.i8xx_flush_page;
711
712 memset(pg, 0, 1024);
713
714 if (cpu_has_clflush) {
715 clflush_cache_range(pg, 1024);
716 } else {
717 if (on_each_cpu(do_wbinvd, NULL, 1) != 0)
718 printk(KERN_ERR "Timed out waiting for cache flush.\n");
719 }
720 }
721
722 /* The intel i830 automatically initializes the agp aperture during POST.
723 * Use the memory already set aside for in the GTT.
724 */
725 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
726 {
727 int page_order;
728 struct aper_size_info_fixed *size;
729 int num_entries;
730 u32 temp;
731
732 size = agp_bridge->current_size;
733 page_order = size->page_order;
734 num_entries = size->num_entries;
735 agp_bridge->gatt_table_real = NULL;
736
737 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
738 temp &= 0xfff80000;
739
740 intel_private.registers = ioremap(temp, 128 * 4096);
741 if (!intel_private.registers)
742 return -ENOMEM;
743
744 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
745 global_cache_flush(); /* FIXME: ?? */
746
747 /* we have to call this as early as possible after the MMIO base address is known */
748 intel_i830_init_gtt_entries();
749
750 agp_bridge->gatt_table = NULL;
751
752 agp_bridge->gatt_bus_addr = temp;
753
754 return 0;
755 }
756
757 /* Return the gatt table to a sane state. Use the top of stolen
758 * memory for the GTT.
759 */
760 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
761 {
762 return 0;
763 }
764
765 static int intel_i830_fetch_size(void)
766 {
767 u16 gmch_ctrl;
768 struct aper_size_info_fixed *values;
769
770 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
771
772 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
773 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
774 /* 855GM/852GM/865G has 128MB aperture size */
775 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
776 agp_bridge->aperture_size_idx = 0;
777 return values[0].size;
778 }
779
780 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
781
782 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
783 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
784 agp_bridge->aperture_size_idx = 0;
785 return values[0].size;
786 } else {
787 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
788 agp_bridge->aperture_size_idx = 1;
789 return values[1].size;
790 }
791
792 return 0;
793 }
794
795 static int intel_i830_configure(void)
796 {
797 struct aper_size_info_fixed *current_size;
798 u32 temp;
799 u16 gmch_ctrl;
800 int i;
801
802 current_size = A_SIZE_FIX(agp_bridge->current_size);
803
804 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
805 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
806
807 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
808 gmch_ctrl |= I830_GMCH_ENABLED;
809 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
810
811 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
812 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
813
814 if (agp_bridge->driver->needs_scratch_page) {
815 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
816 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
817 }
818 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
819 }
820
821 global_cache_flush();
822
823 intel_i830_setup_flush();
824 return 0;
825 }
826
827 static void intel_i830_cleanup(void)
828 {
829 iounmap(intel_private.registers);
830 }
831
832 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
833 int type)
834 {
835 int i, j, num_entries;
836 void *temp;
837 int ret = -EINVAL;
838 int mask_type;
839
840 if (mem->page_count == 0)
841 goto out;
842
843 temp = agp_bridge->current_size;
844 num_entries = A_SIZE_FIX(temp)->num_entries;
845
846 if (pg_start < intel_private.gtt_entries) {
847 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
848 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
849 pg_start, intel_private.gtt_entries);
850
851 dev_info(&intel_private.pcidev->dev,
852 "trying to insert into local/stolen memory\n");
853 goto out_err;
854 }
855
856 if ((pg_start + mem->page_count) > num_entries)
857 goto out_err;
858
859 /* The i830 can't check the GTT for entries since its read only,
860 * depend on the caller to make the correct offset decisions.
861 */
862
863 if (type != mem->type)
864 goto out_err;
865
866 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
867
868 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
869 mask_type != INTEL_AGP_CACHED_MEMORY)
870 goto out_err;
871
872 if (!mem->is_flushed)
873 global_cache_flush();
874
875 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
876 writel(agp_bridge->driver->mask_memory(agp_bridge,
877 mem->pages[i], mask_type),
878 intel_private.registers+I810_PTE_BASE+(j*4));
879 }
880 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
881 agp_bridge->driver->tlb_flush(mem);
882
883 out:
884 ret = 0;
885 out_err:
886 mem->is_flushed = true;
887 return ret;
888 }
889
890 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
891 int type)
892 {
893 int i;
894
895 if (mem->page_count == 0)
896 return 0;
897
898 if (pg_start < intel_private.gtt_entries) {
899 dev_info(&intel_private.pcidev->dev,
900 "trying to disable local/stolen memory\n");
901 return -EINVAL;
902 }
903
904 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
905 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
906 }
907 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
908
909 agp_bridge->driver->tlb_flush(mem);
910 return 0;
911 }
912
913 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
914 {
915 if (type == AGP_PHYS_MEMORY)
916 return alloc_agpphysmem_i8xx(pg_count, type);
917 /* always return NULL for other allocation types for now */
918 return NULL;
919 }
920
921 static int intel_alloc_chipset_flush_resource(void)
922 {
923 int ret;
924 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
925 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
926 pcibios_align_resource, agp_bridge->dev);
927
928 return ret;
929 }
930
931 static void intel_i915_setup_chipset_flush(void)
932 {
933 int ret;
934 u32 temp;
935
936 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
937 if (!(temp & 0x1)) {
938 intel_alloc_chipset_flush_resource();
939 intel_private.resource_valid = 1;
940 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
941 } else {
942 temp &= ~1;
943
944 intel_private.resource_valid = 1;
945 intel_private.ifp_resource.start = temp;
946 intel_private.ifp_resource.end = temp + PAGE_SIZE;
947 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
948 /* some BIOSes reserve this area in a pnp some don't */
949 if (ret)
950 intel_private.resource_valid = 0;
951 }
952 }
953
954 static void intel_i965_g33_setup_chipset_flush(void)
955 {
956 u32 temp_hi, temp_lo;
957 int ret;
958
959 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
960 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
961
962 if (!(temp_lo & 0x1)) {
963
964 intel_alloc_chipset_flush_resource();
965
966 intel_private.resource_valid = 1;
967 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
968 upper_32_bits(intel_private.ifp_resource.start));
969 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
970 } else {
971 u64 l64;
972
973 temp_lo &= ~0x1;
974 l64 = ((u64)temp_hi << 32) | temp_lo;
975
976 intel_private.resource_valid = 1;
977 intel_private.ifp_resource.start = l64;
978 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
979 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
980 /* some BIOSes reserve this area in a pnp some don't */
981 if (ret)
982 intel_private.resource_valid = 0;
983 }
984 }
985
986 static void intel_i9xx_setup_flush(void)
987 {
988 /* return if already configured */
989 if (intel_private.ifp_resource.start)
990 return;
991
992 /* setup a resource for this object */
993 intel_private.ifp_resource.name = "Intel Flush Page";
994 intel_private.ifp_resource.flags = IORESOURCE_MEM;
995
996 /* Setup chipset flush for 915 */
997 if (IS_I965 || IS_G33 || IS_G4X) {
998 intel_i965_g33_setup_chipset_flush();
999 } else {
1000 intel_i915_setup_chipset_flush();
1001 }
1002
1003 if (intel_private.ifp_resource.start) {
1004 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1005 if (!intel_private.i9xx_flush_page)
1006 dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
1007 }
1008 }
1009
1010 static int intel_i915_configure(void)
1011 {
1012 struct aper_size_info_fixed *current_size;
1013 u32 temp;
1014 u16 gmch_ctrl;
1015 int i;
1016
1017 current_size = A_SIZE_FIX(agp_bridge->current_size);
1018
1019 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1020
1021 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1022
1023 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1024 gmch_ctrl |= I830_GMCH_ENABLED;
1025 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1026
1027 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1028 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1029
1030 if (agp_bridge->driver->needs_scratch_page) {
1031 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
1032 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1033 }
1034 readl(intel_private.gtt+i-1); /* PCI Posting. */
1035 }
1036
1037 global_cache_flush();
1038
1039 intel_i9xx_setup_flush();
1040
1041 return 0;
1042 }
1043
1044 static void intel_i915_cleanup(void)
1045 {
1046 if (intel_private.i9xx_flush_page)
1047 iounmap(intel_private.i9xx_flush_page);
1048 if (intel_private.resource_valid)
1049 release_resource(&intel_private.ifp_resource);
1050 intel_private.ifp_resource.start = 0;
1051 intel_private.resource_valid = 0;
1052 iounmap(intel_private.gtt);
1053 iounmap(intel_private.registers);
1054 }
1055
1056 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1057 {
1058 if (intel_private.i9xx_flush_page)
1059 writel(1, intel_private.i9xx_flush_page);
1060 }
1061
1062 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1063 int type)
1064 {
1065 int i, j, num_entries;
1066 void *temp;
1067 int ret = -EINVAL;
1068 int mask_type;
1069
1070 if (mem->page_count == 0)
1071 goto out;
1072
1073 temp = agp_bridge->current_size;
1074 num_entries = A_SIZE_FIX(temp)->num_entries;
1075
1076 if (pg_start < intel_private.gtt_entries) {
1077 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1078 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1079 pg_start, intel_private.gtt_entries);
1080
1081 dev_info(&intel_private.pcidev->dev,
1082 "trying to insert into local/stolen memory\n");
1083 goto out_err;
1084 }
1085
1086 if ((pg_start + mem->page_count) > num_entries)
1087 goto out_err;
1088
1089 /* The i915 can't check the GTT for entries since its read only,
1090 * depend on the caller to make the correct offset decisions.
1091 */
1092
1093 if (type != mem->type)
1094 goto out_err;
1095
1096 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1097
1098 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1099 mask_type != INTEL_AGP_CACHED_MEMORY)
1100 goto out_err;
1101
1102 if (!mem->is_flushed)
1103 global_cache_flush();
1104
1105 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1106 writel(agp_bridge->driver->mask_memory(agp_bridge,
1107 mem->pages[i], mask_type), intel_private.gtt+j);
1108 }
1109
1110 readl(intel_private.gtt+j-1);
1111 agp_bridge->driver->tlb_flush(mem);
1112
1113 out:
1114 ret = 0;
1115 out_err:
1116 mem->is_flushed = true;
1117 return ret;
1118 }
1119
1120 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1121 int type)
1122 {
1123 int i;
1124
1125 if (mem->page_count == 0)
1126 return 0;
1127
1128 if (pg_start < intel_private.gtt_entries) {
1129 dev_info(&intel_private.pcidev->dev,
1130 "trying to disable local/stolen memory\n");
1131 return -EINVAL;
1132 }
1133
1134 for (i = pg_start; i < (mem->page_count + pg_start); i++)
1135 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1136
1137 readl(intel_private.gtt+i-1);
1138
1139 agp_bridge->driver->tlb_flush(mem);
1140 return 0;
1141 }
1142
1143 /* Return the aperture size by just checking the resource length. The effect
1144 * described in the spec of the MSAC registers is just changing of the
1145 * resource size.
1146 */
1147 static int intel_i9xx_fetch_size(void)
1148 {
1149 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1150 int aper_size; /* size in megabytes */
1151 int i;
1152
1153 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1154
1155 for (i = 0; i < num_sizes; i++) {
1156 if (aper_size == intel_i830_sizes[i].size) {
1157 agp_bridge->current_size = intel_i830_sizes + i;
1158 agp_bridge->previous_size = agp_bridge->current_size;
1159 return aper_size;
1160 }
1161 }
1162
1163 return 0;
1164 }
1165
1166 /* The intel i915 automatically initializes the agp aperture during POST.
1167 * Use the memory already set aside for in the GTT.
1168 */
1169 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1170 {
1171 int page_order;
1172 struct aper_size_info_fixed *size;
1173 int num_entries;
1174 u32 temp, temp2;
1175 int gtt_map_size = 256 * 1024;
1176
1177 size = agp_bridge->current_size;
1178 page_order = size->page_order;
1179 num_entries = size->num_entries;
1180 agp_bridge->gatt_table_real = NULL;
1181
1182 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1183 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1184
1185 if (IS_G33)
1186 gtt_map_size = 1024 * 1024; /* 1M on G33 */
1187 intel_private.gtt = ioremap(temp2, gtt_map_size);
1188 if (!intel_private.gtt)
1189 return -ENOMEM;
1190
1191 temp &= 0xfff80000;
1192
1193 intel_private.registers = ioremap(temp, 128 * 4096);
1194 if (!intel_private.registers) {
1195 iounmap(intel_private.gtt);
1196 return -ENOMEM;
1197 }
1198
1199 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1200 global_cache_flush(); /* FIXME: ? */
1201
1202 /* we have to call this as early as possible after the MMIO base address is known */
1203 intel_i830_init_gtt_entries();
1204
1205 agp_bridge->gatt_table = NULL;
1206
1207 agp_bridge->gatt_bus_addr = temp;
1208
1209 return 0;
1210 }
1211
1212 /*
1213 * The i965 supports 36-bit physical addresses, but to keep
1214 * the format of the GTT the same, the bits that don't fit
1215 * in a 32-bit word are shifted down to bits 4..7.
1216 *
1217 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1218 * is always zero on 32-bit architectures, so no need to make
1219 * this conditional.
1220 */
1221 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1222 struct page *page, int type)
1223 {
1224 dma_addr_t addr = phys_to_gart(page_to_phys(page));
1225 /* Shift high bits down */
1226 addr |= (addr >> 28) & 0xf0;
1227
1228 /* Type checking must be done elsewhere */
1229 return addr | bridge->driver->masks[type].mask;
1230 }
1231
1232 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1233 {
1234 switch (agp_bridge->dev->device) {
1235 case PCI_DEVICE_ID_INTEL_GM45_HB:
1236 case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1237 case PCI_DEVICE_ID_INTEL_Q45_HB:
1238 case PCI_DEVICE_ID_INTEL_G45_HB:
1239 case PCI_DEVICE_ID_INTEL_G41_HB:
1240 case PCI_DEVICE_ID_INTEL_B43_HB:
1241 case PCI_DEVICE_ID_INTEL_IGDNG_D_HB:
1242 case PCI_DEVICE_ID_INTEL_IGDNG_M_HB:
1243 case PCI_DEVICE_ID_INTEL_IGDNG_MA_HB:
1244 case PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB:
1245 *gtt_offset = *gtt_size = MB(2);
1246 break;
1247 default:
1248 *gtt_offset = *gtt_size = KB(512);
1249 }
1250 }
1251
1252 /* The intel i965 automatically initializes the agp aperture during POST.
1253 * Use the memory already set aside for in the GTT.
1254 */
1255 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1256 {
1257 int page_order;
1258 struct aper_size_info_fixed *size;
1259 int num_entries;
1260 u32 temp;
1261 int gtt_offset, gtt_size;
1262
1263 size = agp_bridge->current_size;
1264 page_order = size->page_order;
1265 num_entries = size->num_entries;
1266 agp_bridge->gatt_table_real = NULL;
1267
1268 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1269
1270 temp &= 0xfff00000;
1271
1272 intel_i965_get_gtt_range(>t_offset, >t_size);
1273
1274 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1275
1276 if (!intel_private.gtt)
1277 return -ENOMEM;
1278
1279 intel_private.registers = ioremap(temp, 128 * 4096);
1280 if (!intel_private.registers) {
1281 iounmap(intel_private.gtt);
1282 return -ENOMEM;
1283 }
1284
1285 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1286 global_cache_flush(); /* FIXME: ? */
1287
1288 /* we have to call this as early as possible after the MMIO base address is known */
1289 intel_i830_init_gtt_entries();
1290
1291 agp_bridge->gatt_table = NULL;
1292
1293 agp_bridge->gatt_bus_addr = temp;
1294
1295 return 0;
1296 }
1297
1298
1299 static int intel_fetch_size(void)
1300 {
1301 int i;
1302 u16 temp;
1303 struct aper_size_info_16 *values;
1304
1305 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1306 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1307
1308 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1309 if (temp == values[i].size_value) {
1310 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1311 agp_bridge->aperture_size_idx = i;
1312 return values[i].size;
1313 }
1314 }
1315
1316 return 0;
1317 }
1318
1319 static int __intel_8xx_fetch_size(u8 temp)
1320 {
1321 int i;
1322 struct aper_size_info_8 *values;
1323
1324 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1325
1326 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1327 if (temp == values[i].size_value) {
1328 agp_bridge->previous_size =
1329 agp_bridge->current_size = (void *) (values + i);
1330 agp_bridge->aperture_size_idx = i;
1331 return values[i].size;
1332 }
1333 }
1334 return 0;
1335 }
1336
1337 static int intel_8xx_fetch_size(void)
1338 {
1339 u8 temp;
1340
1341 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1342 return __intel_8xx_fetch_size(temp);
1343 }
1344
1345 static int intel_815_fetch_size(void)
1346 {
1347 u8 temp;
1348
1349 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1350 * one non-reserved bit, so mask the others out ... */
1351 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1352 temp &= (1 << 3);
1353
1354 return __intel_8xx_fetch_size(temp);
1355 }
1356
1357 static void intel_tlbflush(struct agp_memory *mem)
1358 {
1359 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1360 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1361 }
1362
1363
1364 static void intel_8xx_tlbflush(struct agp_memory *mem)
1365 {
1366 u32 temp;
1367 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1368 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1369 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1370 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1371 }
1372
1373
1374 static void intel_cleanup(void)
1375 {
1376 u16 temp;
1377 struct aper_size_info_16 *previous_size;
1378
1379 previous_size = A_SIZE_16(agp_bridge->previous_size);
1380 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1381 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1382 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1383 }
1384
1385
1386 static void intel_8xx_cleanup(void)
1387 {
1388 u16 temp;
1389 struct aper_size_info_8 *previous_size;
1390
1391 previous_size = A_SIZE_8(agp_bridge->previous_size);
1392 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1393 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1394 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1395 }
1396
1397
1398 static int intel_configure(void)
1399 {
1400 u32 temp;
1401 u16 temp2;
1402 struct aper_size_info_16 *current_size;
1403
1404 current_size = A_SIZE_16(agp_bridge->current_size);
1405
1406 /* aperture size */
1407 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1408
1409 /* address to map to */
1410 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1411 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1412
1413 /* attbase - aperture base */
1414 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1415
1416 /* agpctrl */
1417 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1418
1419 /* paccfg/nbxcfg */
1420 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1421 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1422 (temp2 & ~(1 << 10)) | (1 << 9));
1423 /* clear any possible error conditions */
1424 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1425 return 0;
1426 }
1427
1428 static int intel_815_configure(void)
1429 {
1430 u32 temp, addr;
1431 u8 temp2;
1432 struct aper_size_info_8 *current_size;
1433
1434 /* attbase - aperture base */
1435 /* the Intel 815 chipset spec. says that bits 29-31 in the
1436 * ATTBASE register are reserved -> try not to write them */
1437 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1438 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
1439 return -EINVAL;
1440 }
1441
1442 current_size = A_SIZE_8(agp_bridge->current_size);
1443
1444 /* aperture size */
1445 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1446 current_size->size_value);
1447
1448 /* address to map to */
1449 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1450 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1451
1452 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1453 addr &= INTEL_815_ATTBASE_MASK;
1454 addr |= agp_bridge->gatt_bus_addr;
1455 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1456
1457 /* agpctrl */
1458 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1459
1460 /* apcont */
1461 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1462 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1463
1464 /* clear any possible error conditions */
1465 /* Oddness : this chipset seems to have no ERRSTS register ! */
1466 return 0;
1467 }
1468
1469 static void intel_820_tlbflush(struct agp_memory *mem)
1470 {
1471 return;
1472 }
1473
1474 static void intel_820_cleanup(void)
1475 {
1476 u8 temp;
1477 struct aper_size_info_8 *previous_size;
1478
1479 previous_size = A_SIZE_8(agp_bridge->previous_size);
1480 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1481 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1482 temp & ~(1 << 1));
1483 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1484 previous_size->size_value);
1485 }
1486
1487
1488 static int intel_820_configure(void)
1489 {
1490 u32 temp;
1491 u8 temp2;
1492 struct aper_size_info_8 *current_size;
1493
1494 current_size = A_SIZE_8(agp_bridge->current_size);
1495
1496 /* aperture size */
1497 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1498
1499 /* address to map to */
1500 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1501 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1502
1503 /* attbase - aperture base */
1504 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1505
1506 /* agpctrl */
1507 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1508
1509 /* global enable aperture access */
1510 /* This flag is not accessed through MCHCFG register as in */
1511 /* i850 chipset. */
1512 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1513 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1514 /* clear any possible AGP-related error conditions */
1515 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1516 return 0;
1517 }
1518
1519 static int intel_840_configure(void)
1520 {
1521 u32 temp;
1522 u16 temp2;
1523 struct aper_size_info_8 *current_size;
1524
1525 current_size = A_SIZE_8(agp_bridge->current_size);
1526
1527 /* aperture size */
1528 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1529
1530 /* address to map to */
1531 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1532 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1533
1534 /* attbase - aperture base */
1535 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1536
1537 /* agpctrl */
1538 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1539
1540 /* mcgcfg */
1541 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1542 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1543 /* clear any possible error conditions */
1544 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1545 return 0;
1546 }
1547
1548 static int intel_845_configure(void)
1549 {
1550 u32 temp;
1551 u8 temp2;
1552 struct aper_size_info_8 *current_size;
1553
1554 current_size = A_SIZE_8(agp_bridge->current_size);
1555
1556 /* aperture size */
1557 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1558
1559 if (agp_bridge->apbase_config != 0) {
1560 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1561 agp_bridge->apbase_config);
1562 } else {
1563 /* address to map to */
1564 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1565 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1566 agp_bridge->apbase_config = temp;
1567 }
1568
1569 /* attbase - aperture base */
1570 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1571
1572 /* agpctrl */
1573 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1574
1575 /* agpm */
1576 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1577 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1578 /* clear any possible error conditions */
1579 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1580
1581 intel_i830_setup_flush();
1582 return 0;
1583 }
1584
1585 static int intel_850_configure(void)
1586 {
1587 u32 temp;
1588 u16 temp2;
1589 struct aper_size_info_8 *current_size;
1590
1591 current_size = A_SIZE_8(agp_bridge->current_size);
1592
1593 /* aperture size */
1594 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1595
1596 /* address to map to */
1597 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1598 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1599
1600 /* attbase - aperture base */
1601 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1602
1603 /* agpctrl */
1604 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1605
1606 /* mcgcfg */
1607 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1608 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1609 /* clear any possible AGP-related error conditions */
1610 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1611 return 0;
1612 }
1613
1614 static int intel_860_configure(void)
1615 {
1616 u32 temp;
1617 u16 temp2;
1618 struct aper_size_info_8 *current_size;
1619
1620 current_size = A_SIZE_8(agp_bridge->current_size);
1621
1622 /* aperture size */
1623 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1624
1625 /* address to map to */
1626 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1627 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1628
1629 /* attbase - aperture base */
1630 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1631
1632 /* agpctrl */
1633 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1634
1635 /* mcgcfg */
1636 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1637 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1638 /* clear any possible AGP-related error conditions */
1639 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1640 return 0;
1641 }
1642
1643 static int intel_830mp_configure(void)
1644 {
1645 u32 temp;
1646 u16 temp2;
1647 struct aper_size_info_8 *current_size;
1648
1649 current_size = A_SIZE_8(agp_bridge->current_size);
1650
1651 /* aperture size */
1652 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1653
1654 /* address to map to */
1655 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1656 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1657
1658 /* attbase - aperture base */
1659 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1660
1661 /* agpctrl */
1662 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1663
1664 /* gmch */
1665 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1666 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1667 /* clear any possible AGP-related error conditions */
1668 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1669 return 0;
1670 }
1671
1672 static int intel_7505_configure(void)
1673 {
1674 u32 temp;
1675 u16 temp2;
1676 struct aper_size_info_8 *current_size;
1677
1678 current_size = A_SIZE_8(agp_bridge->current_size);
1679
1680 /* aperture size */
1681 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1682
1683 /* address to map to */
1684 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1685 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1686
1687 /* attbase - aperture base */
1688 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1689
1690 /* agpctrl */
1691 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1692
1693 /* mchcfg */
1694 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1695 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1696
1697 return 0;
1698 }
1699
1700 /* Setup function */
1701 static const struct gatt_mask intel_generic_masks[] =
1702 {
1703 {.mask = 0x00000017, .type = 0}
1704 };
1705
1706 static const struct aper_size_info_8 intel_815_sizes[2] =
1707 {
1708 {64, 16384, 4, 0},
1709 {32, 8192, 3, 8},
1710 };
1711
1712 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1713 {
1714 {256, 65536, 6, 0},
1715 {128, 32768, 5, 32},
1716 {64, 16384, 4, 48},
1717 {32, 8192, 3, 56},
1718 {16, 4096, 2, 60},
1719 {8, 2048, 1, 62},
1720 {4, 1024, 0, 63}
1721 };
1722
1723 static const struct aper_size_info_16 intel_generic_sizes[7] =
1724 {
1725 {256, 65536, 6, 0},
1726 {128, 32768, 5, 32},
1727 {64, 16384, 4, 48},
1728 {32, 8192, 3, 56},
1729 {16, 4096, 2, 60},
1730 {8, 2048, 1, 62},
1731 {4, 1024, 0, 63}
1732 };
1733
1734 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1735 {
1736 {256, 65536, 6, 0},
1737 {128, 32768, 5, 32},
1738 {64, 16384, 4, 48},
1739 {32, 8192, 3, 56}
1740 };
1741
1742 static const struct agp_bridge_driver intel_generic_driver = {
1743 .owner = THIS_MODULE,
1744 .aperture_sizes = intel_generic_sizes,
1745 .size_type = U16_APER_SIZE,
1746 .num_aperture_sizes = 7,
1747 .configure = intel_configure,
1748 .fetch_size = intel_fetch_size,
1749 .cleanup = intel_cleanup,
1750 .tlb_flush = intel_tlbflush,
1751 .mask_memory = agp_generic_mask_memory,
1752 .masks = intel_generic_masks,
1753 .agp_enable = agp_generic_enable,
1754 .cache_flush = global_cache_flush,
1755 .create_gatt_table = agp_generic_create_gatt_table,
1756 .free_gatt_table = agp_generic_free_gatt_table,
1757 .insert_memory = agp_generic_insert_memory,
1758 .remove_memory = agp_generic_remove_memory,
1759 .alloc_by_type = agp_generic_alloc_by_type,
1760 .free_by_type = agp_generic_free_by_type,
1761 .agp_alloc_page = agp_generic_alloc_page,
1762 .agp_alloc_pages = agp_generic_alloc_pages,
1763 .agp_destroy_page = agp_generic_destroy_page,
1764 .agp_destroy_pages = agp_generic_destroy_pages,
1765 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1766 };
1767
1768 static const struct agp_bridge_driver intel_810_driver = {
1769 .owner = THIS_MODULE,
1770 .aperture_sizes = intel_i810_sizes,
1771 .size_type = FIXED_APER_SIZE,
1772 .num_aperture_sizes = 2,
1773 .needs_scratch_page = true,
1774 .configure = intel_i810_configure,
1775 .fetch_size = intel_i810_fetch_size,
1776 .cleanup = intel_i810_cleanup,
1777 .tlb_flush = intel_i810_tlbflush,
1778 .mask_memory = intel_i810_mask_memory,
1779 .masks = intel_i810_masks,
1780 .agp_enable = intel_i810_agp_enable,
1781 .cache_flush = global_cache_flush,
1782 .create_gatt_table = agp_generic_create_gatt_table,
1783 .free_gatt_table = agp_generic_free_gatt_table,
1784 .insert_memory = intel_i810_insert_entries,
1785 .remove_memory = intel_i810_remove_entries,
1786 .alloc_by_type = intel_i810_alloc_by_type,
1787 .free_by_type = intel_i810_free_by_type,
1788 .agp_alloc_page = agp_generic_alloc_page,
1789 .agp_alloc_pages = agp_generic_alloc_pages,
1790 .agp_destroy_page = agp_generic_destroy_page,
1791 .agp_destroy_pages = agp_generic_destroy_pages,
1792 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1793 };
1794
1795 static const struct agp_bridge_driver intel_815_driver = {
1796 .owner = THIS_MODULE,
1797 .aperture_sizes = intel_815_sizes,
1798 .size_type = U8_APER_SIZE,
1799 .num_aperture_sizes = 2,
1800 .configure = intel_815_configure,
1801 .fetch_size = intel_815_fetch_size,
1802 .cleanup = intel_8xx_cleanup,
1803 .tlb_flush = intel_8xx_tlbflush,
1804 .mask_memory = agp_generic_mask_memory,
1805 .masks = intel_generic_masks,
1806 .agp_enable = agp_generic_enable,
1807 .cache_flush = global_cache_flush,
1808 .create_gatt_table = agp_generic_create_gatt_table,
1809 .free_gatt_table = agp_generic_free_gatt_table,
1810 .insert_memory = agp_generic_insert_memory,
1811 .remove_memory = agp_generic_remove_memory,
1812 .alloc_by_type = agp_generic_alloc_by_type,
1813 .free_by_type = agp_generic_free_by_type,
1814 .agp_alloc_page = agp_generic_alloc_page,
1815 .agp_alloc_pages = agp_generic_alloc_pages,
1816 .agp_destroy_page = agp_generic_destroy_page,
1817 .agp_destroy_pages = agp_generic_destroy_pages,
1818 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1819 };
1820
1821 static const struct agp_bridge_driver intel_830_driver = {
1822 .owner = THIS_MODULE,
1823 .aperture_sizes = intel_i830_sizes,
1824 .size_type = FIXED_APER_SIZE,
1825 .num_aperture_sizes = 4,
1826 .needs_scratch_page = true,
1827 .configure = intel_i830_configure,
1828 .fetch_size = intel_i830_fetch_size,
1829 .cleanup = intel_i830_cleanup,
1830 .tlb_flush = intel_i810_tlbflush,
1831 .mask_memory = intel_i810_mask_memory,
1832 .masks = intel_i810_masks,
1833 .agp_enable = intel_i810_agp_enable,
1834 .cache_flush = global_cache_flush,
1835 .create_gatt_table = intel_i830_create_gatt_table,
1836 .free_gatt_table = intel_i830_free_gatt_table,
1837 .insert_memory = intel_i830_insert_entries,
1838 .remove_memory = intel_i830_remove_entries,
1839 .alloc_by_type = intel_i830_alloc_by_type,
1840 .free_by_type = intel_i810_free_by_type,
1841 .agp_alloc_page = agp_generic_alloc_page,
1842 .agp_alloc_pages = agp_generic_alloc_pages,
1843 .agp_destroy_page = agp_generic_destroy_page,
1844 .agp_destroy_pages = agp_generic_destroy_pages,
1845 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1846 .chipset_flush = intel_i830_chipset_flush,
1847 };
1848
1849 static const struct agp_bridge_driver intel_820_driver = {
1850 .owner = THIS_MODULE,
1851 .aperture_sizes = intel_8xx_sizes,
1852 .size_type = U8_APER_SIZE,
1853 .num_aperture_sizes = 7,
1854 .configure = intel_820_configure,
1855 .fetch_size = intel_8xx_fetch_size,
1856 .cleanup = intel_820_cleanup,
1857 .tlb_flush = intel_820_tlbflush,
1858 .mask_memory = agp_generic_mask_memory,
1859 .masks = intel_generic_masks,
1860 .agp_enable = agp_generic_enable,
1861 .cache_flush = global_cache_flush,
1862 .create_gatt_table = agp_generic_create_gatt_table,
1863 .free_gatt_table = agp_generic_free_gatt_table,
1864 .insert_memory = agp_generic_insert_memory,
1865 .remove_memory = agp_generic_remove_memory,
1866 .alloc_by_type = agp_generic_alloc_by_type,
1867 .free_by_type = agp_generic_free_by_type,
1868 .agp_alloc_page = agp_generic_alloc_page,
1869 .agp_alloc_pages = agp_generic_alloc_pages,
1870 .agp_destroy_page = agp_generic_destroy_page,
1871 .agp_destroy_pages = agp_generic_destroy_pages,
1872 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1873 };
1874
1875 static const struct agp_bridge_driver intel_830mp_driver = {
1876 .owner = THIS_MODULE,
1877 .aperture_sizes = intel_830mp_sizes,
1878 .size_type = U8_APER_SIZE,
1879 .num_aperture_sizes = 4,
1880 .configure = intel_830mp_configure,
1881 .fetch_size = intel_8xx_fetch_size,
1882 .cleanup = intel_8xx_cleanup,
1883 .tlb_flush = intel_8xx_tlbflush,
1884 .mask_memory = agp_generic_mask_memory,
1885 .masks = intel_generic_masks,
1886 .agp_enable = agp_generic_enable,
1887 .cache_flush = global_cache_flush,
1888 .create_gatt_table = agp_generic_create_gatt_table,
1889 .free_gatt_table = agp_generic_free_gatt_table,
1890 .insert_memory = agp_generic_insert_memory,
1891 .remove_memory = agp_generic_remove_memory,
1892 .alloc_by_type = agp_generic_alloc_by_type,
1893 .free_by_type = agp_generic_free_by_type,
1894 .agp_alloc_page = agp_generic_alloc_page,
1895 .agp_alloc_pages = agp_generic_alloc_pages,
1896 .agp_destroy_page = agp_generic_destroy_page,
1897 .agp_destroy_pages = agp_generic_destroy_pages,
1898 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1899 };
1900
1901 static const struct agp_bridge_driver intel_840_driver = {
1902 .owner = THIS_MODULE,
1903 .aperture_sizes = intel_8xx_sizes,
1904 .size_type = U8_APER_SIZE,
1905 .num_aperture_sizes = 7,
1906 .configure = intel_840_configure,
1907 .fetch_size = intel_8xx_fetch_size,
1908 .cleanup = intel_8xx_cleanup,
1909 .tlb_flush = intel_8xx_tlbflush,
1910 .mask_memory = agp_generic_mask_memory,
1911 .masks = intel_generic_masks,
1912 .agp_enable = agp_generic_enable,
1913 .cache_flush = global_cache_flush,
1914 .create_gatt_table = agp_generic_create_gatt_table,
1915 .free_gatt_table = agp_generic_free_gatt_table,
1916 .insert_memory = agp_generic_insert_memory,
1917 .remove_memory = agp_generic_remove_memory,
1918 .alloc_by_type = agp_generic_alloc_by_type,
1919 .free_by_type = agp_generic_free_by_type,
1920 .agp_alloc_page = agp_generic_alloc_page,
1921 .agp_alloc_pages = agp_generic_alloc_pages,
1922 .agp_destroy_page = agp_generic_destroy_page,
1923 .agp_destroy_pages = agp_generic_destroy_pages,
1924 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1925 };
1926
1927 static const struct agp_bridge_driver intel_845_driver = {
1928 .owner = THIS_MODULE,
1929 .aperture_sizes = intel_8xx_sizes,
1930 .size_type = U8_APER_SIZE,
1931 .num_aperture_sizes = 7,
1932 .configure = intel_845_configure,
1933 .fetch_size = intel_8xx_fetch_size,
1934 .cleanup = intel_8xx_cleanup,
1935 .tlb_flush = intel_8xx_tlbflush,
1936 .mask_memory = agp_generic_mask_memory,
1937 .masks = intel_generic_masks,
1938 .agp_enable = agp_generic_enable,
1939 .cache_flush = global_cache_flush,
1940 .create_gatt_table = agp_generic_create_gatt_table,
1941 .free_gatt_table = agp_generic_free_gatt_table,
1942 .insert_memory = agp_generic_insert_memory,
1943 .remove_memory = agp_generic_remove_memory,
1944 .alloc_by_type = agp_generic_alloc_by_type,
1945 .free_by_type = agp_generic_free_by_type,
1946 .agp_alloc_page = agp_generic_alloc_page,
1947 .agp_alloc_pages = agp_generic_alloc_pages,
1948 .agp_destroy_page = agp_generic_destroy_page,
1949 .agp_destroy_pages = agp_generic_destroy_pages,
1950 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1951 .chipset_flush = intel_i830_chipset_flush,
1952 };
1953
1954 static const struct agp_bridge_driver intel_850_driver = {
1955 .owner = THIS_MODULE,
1956 .aperture_sizes = intel_8xx_sizes,
1957 .size_type = U8_APER_SIZE,
1958 .num_aperture_sizes = 7,
1959 .configure = intel_850_configure,
1960 .fetch_size = intel_8xx_fetch_size,
1961 .cleanup = intel_8xx_cleanup,
1962 .tlb_flush = intel_8xx_tlbflush,
1963 .mask_memory = agp_generic_mask_memory,
1964 .masks = intel_generic_masks,
1965 .agp_enable = agp_generic_enable,
1966 .cache_flush = global_cache_flush,
1967 .create_gatt_table = agp_generic_create_gatt_table,
1968 .free_gatt_table = agp_generic_free_gatt_table,
1969 .insert_memory = agp_generic_insert_memory,
1970 .remove_memory = agp_generic_remove_memory,
1971 .alloc_by_type = agp_generic_alloc_by_type,
1972 .free_by_type = agp_generic_free_by_type,
1973 .agp_alloc_page = agp_generic_alloc_page,
1974 .agp_alloc_pages = agp_generic_alloc_pages,
1975 .agp_destroy_page = agp_generic_destroy_page,
1976 .agp_destroy_pages = agp_generic_destroy_pages,
1977 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1978 };
1979
1980 static const struct agp_bridge_driver intel_860_driver = {
1981 .owner = THIS_MODULE,
1982 .aperture_sizes = intel_8xx_sizes,
1983 .size_type = U8_APER_SIZE,
1984 .num_aperture_sizes = 7,
1985 .configure = intel_860_configure,
1986 .fetch_size = intel_8xx_fetch_size,
1987 .cleanup = intel_8xx_cleanup,
1988 .tlb_flush = intel_8xx_tlbflush,
1989 .mask_memory = agp_generic_mask_memory,
1990 .masks = intel_generic_masks,
1991 .agp_enable = agp_generic_enable,
1992 .cache_flush = global_cache_flush,
1993 .create_gatt_table = agp_generic_create_gatt_table,
1994 .free_gatt_table = agp_generic_free_gatt_table,
1995 .insert_memory = agp_generic_insert_memory,
1996 .remove_memory = agp_generic_remove_memory,
1997 .alloc_by_type = agp_generic_alloc_by_type,
1998 .free_by_type = agp_generic_free_by_type,
1999 .agp_alloc_page = agp_generic_alloc_page,
2000 .agp_alloc_pages = agp_generic_alloc_pages,
2001 .agp_destroy_page = agp_generic_destroy_page,
2002 .agp_destroy_pages = agp_generic_destroy_pages,
2003 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2004 };
2005
2006 static const struct agp_bridge_driver intel_915_driver = {
2007 .owner = THIS_MODULE,
2008 .aperture_sizes = intel_i830_sizes,
2009 .size_type = FIXED_APER_SIZE,
2010 .num_aperture_sizes = 4,
2011 .needs_scratch_page = true,
2012 .configure = intel_i915_configure,
2013 .fetch_size = intel_i9xx_fetch_size,
2014 .cleanup = intel_i915_cleanup,
2015 .tlb_flush = intel_i810_tlbflush,
2016 .mask_memory = intel_i810_mask_memory,
2017 .masks = intel_i810_masks,
2018 .agp_enable = intel_i810_agp_enable,
2019 .cache_flush = global_cache_flush,
2020 .create_gatt_table = intel_i915_create_gatt_table,
2021 .free_gatt_table = intel_i830_free_gatt_table,
2022 .insert_memory = intel_i915_insert_entries,
2023 .remove_memory = intel_i915_remove_entries,
2024 .alloc_by_type = intel_i830_alloc_by_type,
2025 .free_by_type = intel_i810_free_by_type,
2026 .agp_alloc_page = agp_generic_alloc_page,
2027 .agp_alloc_pages = agp_generic_alloc_pages,
2028 .agp_destroy_page = agp_generic_destroy_page,
2029 .agp_destroy_pages = agp_generic_destroy_pages,
2030 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2031 .chipset_flush = intel_i915_chipset_flush,
2032 };
2033
2034 static const struct agp_bridge_driver intel_i965_driver = {
2035 .owner = THIS_MODULE,
2036 .aperture_sizes = intel_i830_sizes,
2037 .size_type = FIXED_APER_SIZE,
2038 .num_aperture_sizes = 4,
2039 .needs_scratch_page = true,
2040 .configure = intel_i915_configure,
2041 .fetch_size = intel_i9xx_fetch_size,
2042 .cleanup = intel_i915_cleanup,
2043 .tlb_flush = intel_i810_tlbflush,
2044 .mask_memory = intel_i965_mask_memory,
2045 .masks = intel_i810_masks,
2046 .agp_enable = intel_i810_agp_enable,
2047 .cache_flush = global_cache_flush,
2048 .create_gatt_table = intel_i965_create_gatt_table,
2049 .free_gatt_table = intel_i830_free_gatt_table,
2050 .insert_memory = intel_i915_insert_entries,
2051 .remove_memory = intel_i915_remove_entries,
2052 .alloc_by_type = intel_i830_alloc_by_type,
2053 .free_by_type = intel_i810_free_by_type,
2054 .agp_alloc_page = agp_generic_alloc_page,
2055 .agp_alloc_pages = agp_generic_alloc_pages,
2056 .agp_destroy_page = agp_generic_destroy_page,
2057 .agp_destroy_pages = agp_generic_destroy_pages,
2058 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2059 .chipset_flush = intel_i915_chipset_flush,
2060 };
2061
2062 static const struct agp_bridge_driver intel_7505_driver = {
2063 .owner = THIS_MODULE,
2064 .aperture_sizes = intel_8xx_sizes,
2065 .size_type = U8_APER_SIZE,
2066 .num_aperture_sizes = 7,
2067 .configure = intel_7505_configure,
2068 .fetch_size = intel_8xx_fetch_size,
2069 .cleanup = intel_8xx_cleanup,
2070 .tlb_flush = intel_8xx_tlbflush,
2071 .mask_memory = agp_generic_mask_memory,
2072 .masks = intel_generic_masks,
2073 .agp_enable = agp_generic_enable,
2074 .cache_flush = global_cache_flush,
2075 .create_gatt_table = agp_generic_create_gatt_table,
2076 .free_gatt_table = agp_generic_free_gatt_table,
2077 .insert_memory = agp_generic_insert_memory,
2078 .remove_memory = agp_generic_remove_memory,
2079 .alloc_by_type = agp_generic_alloc_by_type,
2080 .free_by_type = agp_generic_free_by_type,
2081 .agp_alloc_page = agp_generic_alloc_page,
2082 .agp_alloc_pages = agp_generic_alloc_pages,
2083 .agp_destroy_page = agp_generic_destroy_page,
2084 .agp_destroy_pages = agp_generic_destroy_pages,
2085 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2086 };
2087
2088 static const struct agp_bridge_driver intel_g33_driver = {
2089 .owner = THIS_MODULE,
2090 .aperture_sizes = intel_i830_sizes,
2091 .size_type = FIXED_APER_SIZE,
2092 .num_aperture_sizes = 4,
2093 .needs_scratch_page = true,
2094 .configure = intel_i915_configure,
2095 .fetch_size = intel_i9xx_fetch_size,
2096 .cleanup = intel_i915_cleanup,
2097 .tlb_flush = intel_i810_tlbflush,
2098 .mask_memory = intel_i965_mask_memory,
2099 .masks = intel_i810_masks,
2100 .agp_enable = intel_i810_agp_enable,
2101 .cache_flush = global_cache_flush,
2102 .create_gatt_table = intel_i915_create_gatt_table,
2103 .free_gatt_table = intel_i830_free_gatt_table,
2104 .insert_memory = intel_i915_insert_entries,
2105 .remove_memory = intel_i915_remove_entries,
2106 .alloc_by_type = intel_i830_alloc_by_type,
2107 .free_by_type = intel_i810_free_by_type,
2108 .agp_alloc_page = agp_generic_alloc_page,
2109 .agp_alloc_pages = agp_generic_alloc_pages,
2110 .agp_destroy_page = agp_generic_destroy_page,
2111 .agp_destroy_pages = agp_generic_destroy_pages,
2112 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2113 .chipset_flush = intel_i915_chipset_flush,
2114 };
2115
2116 static int find_gmch(u16 device)
2117 {
2118 struct pci_dev *gmch_device;
2119
2120 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2121 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2122 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
2123 device, gmch_device);
2124 }
2125
2126 if (!gmch_device)
2127 return 0;
2128
2129 intel_private.pcidev = gmch_device;
2130 return 1;
2131 }
2132
2133 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
2134 * driver and gmch_driver must be non-null, and find_gmch will determine
2135 * which one should be used if a gmch_chip_id is present.
2136 */
2137 static const struct intel_driver_description {
2138 unsigned int chip_id;
2139 unsigned int gmch_chip_id;
2140 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2141 char *name;
2142 const struct agp_bridge_driver *driver;
2143 const struct agp_bridge_driver *gmch_driver;
2144 } intel_agp_chipsets[] = {
2145 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2146 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2147 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2148 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2149 NULL, &intel_810_driver },
2150 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2151 NULL, &intel_810_driver },
2152 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2153 NULL, &intel_810_driver },
2154 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2155 &intel_815_driver, &intel_810_driver },
2156 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2157 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2158 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2159 &intel_830mp_driver, &intel_830_driver },
2160 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2161 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2162 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2163 &intel_845_driver, &intel_830_driver },
2164 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2165 { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
2166 &intel_845_driver, &intel_830_driver },
2167 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2168 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2169 &intel_845_driver, &intel_830_driver },
2170 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2171 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2172 &intel_845_driver, &intel_830_driver },
2173 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2174 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2175 NULL, &intel_915_driver },
2176 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2177 NULL, &intel_915_driver },
2178 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2179 NULL, &intel_915_driver },
2180 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2181 NULL, &intel_915_driver },
2182 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2183 NULL, &intel_915_driver },
2184 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2185 NULL, &intel_915_driver },
2186 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2187 NULL, &intel_i965_driver },
2188 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2189 NULL, &intel_i965_driver },
2190 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2191 NULL, &intel_i965_driver },
2192 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2193 NULL, &intel_i965_driver },
2194 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2195 NULL, &intel_i965_driver },
2196 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2197 NULL, &intel_i965_driver },
2198 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2199 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2200 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2201 NULL, &intel_g33_driver },
2202 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2203 NULL, &intel_g33_driver },
2204 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2205 NULL, &intel_g33_driver },
2206 { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD",
2207 NULL, &intel_g33_driver },
2208 { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD",
2209 NULL, &intel_g33_driver },
2210 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2211 "Mobile Intel® GM45 Express", NULL, &intel_i965_driver },
2212 { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2213 "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2214 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2215 "Q45/Q43", NULL, &intel_i965_driver },
2216 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2217 "G45/G43", NULL, &intel_i965_driver },
2218 { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0,
2219 "B43", NULL, &intel_i965_driver },
2220 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2221 "G41", NULL, &intel_i965_driver },
2222 { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0,
2223 "IGDNG/D", NULL, &intel_i965_driver },
2224 { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2225 "IGDNG/M", NULL, &intel_i965_driver },
2226 { PCI_DEVICE_ID_INTEL_IGDNG_MA_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2227 "IGDNG/MA", NULL, &intel_i965_driver },
2228 { PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2229 "IGDNG/MC2", NULL, &intel_i965_driver },
2230 { 0, 0, 0, NULL, NULL, NULL }
2231 };
2232
2233 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2234 const struct pci_device_id *ent)
2235 {
2236 struct agp_bridge_data *bridge;
2237 u8 cap_ptr = 0;
2238 struct resource *r;
2239 int i;
2240
2241 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2242
2243 bridge = agp_alloc_bridge();
2244 if (!bridge)
2245 return -ENOMEM;
2246
2247 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2248 /* In case that multiple models of gfx chip may
2249 stand on same host bridge type, this can be
2250 sure we detect the right IGD. */
2251 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2252 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2253 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2254 bridge->driver =
2255 intel_agp_chipsets[i].gmch_driver;
2256 break;
2257 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2258 continue;
2259 } else {
2260 bridge->driver = intel_agp_chipsets[i].driver;
2261 break;
2262 }
2263 }
2264 }
2265
2266 if (intel_agp_chipsets[i].name == NULL) {
2267 if (cap_ptr)
2268 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2269 pdev->vendor, pdev->device);
2270 agp_put_bridge(bridge);
2271 return -ENODEV;
2272 }
2273
2274 if (bridge->driver == NULL) {
2275 /* bridge has no AGP and no IGD detected */
2276 if (cap_ptr)
2277 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2278 intel_agp_chipsets[i].gmch_chip_id);
2279 agp_put_bridge(bridge);
2280 return -ENODEV;
2281 }
2282
2283 bridge->dev = pdev;
2284 bridge->capndx = cap_ptr;
2285 bridge->dev_private_data = &intel_private;
2286
2287 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
2288
2289 /*
2290 * The following fixes the case where the BIOS has "forgotten" to
2291 * provide an address range for the GART.
2292 * 20030610 - hamish@zot.org
2293 */
2294 r = &pdev->resource[0];
2295 if (!r->start && r->end) {
2296 if (pci_assign_resource(pdev, 0)) {
2297 dev_err(&pdev->dev, "can't assign resource 0\n");
2298 agp_put_bridge(bridge);
2299 return -ENODEV;
2300 }
2301 }
2302
2303 /*
2304 * If the device has not been properly setup, the following will catch
2305 * the problem and should stop the system from crashing.
2306 * 20030610 - hamish@zot.org
2307 */
2308 if (pci_enable_device(pdev)) {
2309 dev_err(&pdev->dev, "can't enable PCI device\n");
2310 agp_put_bridge(bridge);
2311 return -ENODEV;
2312 }
2313
2314 /* Fill in the mode register */
2315 if (cap_ptr) {
2316 pci_read_config_dword(pdev,
2317 bridge->capndx+PCI_AGP_STATUS,
2318 &bridge->mode);
2319 }
2320
2321 pci_set_drvdata(pdev, bridge);
2322 return agp_add_bridge(bridge);
2323 }
2324
2325 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2326 {
2327 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2328
2329 agp_remove_bridge(bridge);
2330
2331 if (intel_private.pcidev)
2332 pci_dev_put(intel_private.pcidev);
2333
2334 agp_put_bridge(bridge);
2335 }
2336
2337 #ifdef CONFIG_PM
2338 static int agp_intel_resume(struct pci_dev *pdev)
2339 {
2340 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2341 int ret_val;
2342
2343 if (bridge->driver == &intel_generic_driver)
2344 intel_configure();
2345 else if (bridge->driver == &intel_850_driver)
2346 intel_850_configure();
2347 else if (bridge->driver == &intel_845_driver)
2348 intel_845_configure();
2349 else if (bridge->driver == &intel_830mp_driver)
2350 intel_830mp_configure();
2351 else if (bridge->driver == &intel_915_driver)
2352 intel_i915_configure();
2353 else if (bridge->driver == &intel_830_driver)
2354 intel_i830_configure();
2355 else if (bridge->driver == &intel_810_driver)
2356 intel_i810_configure();
2357 else if (bridge->driver == &intel_i965_driver)
2358 intel_i915_configure();
2359
2360 ret_val = agp_rebind_memory();
2361 if (ret_val != 0)
2362 return ret_val;
2363
2364 return 0;
2365 }
2366 #endif
2367
2368 static struct pci_device_id agp_intel_pci_table[] = {
2369 #define ID(x) \
2370 { \
2371 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2372 .class_mask = ~0, \
2373 .vendor = PCI_VENDOR_ID_INTEL, \
2374 .device = x, \
2375 .subvendor = PCI_ANY_ID, \
2376 .subdevice = PCI_ANY_ID, \
2377 }
2378 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2379 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2380 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2381 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2382 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2383 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2384 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2385 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2386 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2387 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2388 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2389 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2390 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2391 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2392 ID(PCI_DEVICE_ID_INTEL_82854_HB),
2393 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2394 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2395 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2396 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2397 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2398 ID(PCI_DEVICE_ID_INTEL_7505_0),
2399 ID(PCI_DEVICE_ID_INTEL_7205_0),
2400 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2401 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2402 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2403 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2404 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2405 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2406 ID(PCI_DEVICE_ID_INTEL_IGDGM_HB),
2407 ID(PCI_DEVICE_ID_INTEL_IGDG_HB),
2408 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2409 ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2410 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2411 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2412 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2413 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2414 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2415 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2416 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2417 ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2418 ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2419 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2420 ID(PCI_DEVICE_ID_INTEL_G45_HB),
2421 ID(PCI_DEVICE_ID_INTEL_G41_HB),
2422 ID(PCI_DEVICE_ID_INTEL_B43_HB),
2423 ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB),
2424 ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB),
2425 ID(PCI_DEVICE_ID_INTEL_IGDNG_MA_HB),
2426 ID(PCI_DEVICE_ID_INTEL_IGDNG_MC2_HB),
2427 { }
2428 };
2429
2430 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2431
2432 static struct pci_driver agp_intel_pci_driver = {
2433 .name = "agpgart-intel",
2434 .id_table = agp_intel_pci_table,
2435 .probe = agp_intel_probe,
2436 .remove = __devexit_p(agp_intel_remove),
2437 #ifdef CONFIG_PM
2438 .resume = agp_intel_resume,
2439 #endif
2440 };
2441
2442 static int __init agp_intel_init(void)
2443 {
2444 if (agp_off)
2445 return -EINVAL;
2446 return pci_register_driver(&agp_intel_pci_driver);
2447 }
2448
2449 static void __exit agp_intel_cleanup(void)
2450 {
2451 pci_unregister_driver(&agp_intel_pci_driver);
2452 }
2453
2454 module_init(agp_intel_init);
2455 module_exit(agp_intel_cleanup);
2456
2457 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2458 MODULE_LICENSE("GPL and additional rights");
2459
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