1
2 /*
3 * This file contains defines for the
4 * Micro Memory MM5415
5 * family PCI Memory Module with Battery Backup.
6 *
7 * Copyright Micro Memory INC 2001. All rights reserved.
8 * Release under the terms of the GNU GENERAL PUBLIC LICENSE version 2.
9 * See the file COPYING.
10 */
11
12 #ifndef _DRIVERS_BLOCK_MM_H
13 #define _DRIVERS_BLOCK_MM_H
14
15
16 #define IRQ_TIMEOUT (1 * HZ)
17
18 /* CSR register definition */
19 #define MEMCTRLSTATUS_MAGIC 0x00
20 #define MM_MAGIC_VALUE (unsigned char)0x59
21
22 #define MEMCTRLSTATUS_BATTERY 0x04
23 #define BATTERY_1_DISABLED 0x01
24 #define BATTERY_1_FAILURE 0x02
25 #define BATTERY_2_DISABLED 0x04
26 #define BATTERY_2_FAILURE 0x08
27
28 #define MEMCTRLSTATUS_MEMORY 0x07
29 #define MEM_128_MB 0xfe
30 #define MEM_256_MB 0xfc
31 #define MEM_512_MB 0xf8
32 #define MEM_1_GB 0xf0
33 #define MEM_2_GB 0xe0
34
35 #define MEMCTRLCMD_LEDCTRL 0x08
36 #define LED_REMOVE 2
37 #define LED_FAULT 4
38 #define LED_POWER 6
39 #define LED_FLIP 255
40 #define LED_OFF 0x00
41 #define LED_ON 0x01
42 #define LED_FLASH_3_5 0x02
43 #define LED_FLASH_7_0 0x03
44 #define LED_POWER_ON 0x00
45 #define LED_POWER_OFF 0x01
46 #define USER_BIT1 0x01
47 #define USER_BIT2 0x02
48
49 #define MEMORY_INITIALIZED USER_BIT1
50
51 #define MEMCTRLCMD_ERRCTRL 0x0C
52 #define EDC_NONE_DEFAULT 0x00
53 #define EDC_NONE 0x01
54 #define EDC_STORE_READ 0x02
55 #define EDC_STORE_CORRECT 0x03
56
57 #define MEMCTRLCMD_ERRCNT 0x0D
58 #define MEMCTRLCMD_ERRSTATUS 0x0E
59
60 #define ERROR_DATA_LOG 0x20
61 #define ERROR_ADDR_LOG 0x28
62 #define ERROR_COUNT 0x3D
63 #define ERROR_SYNDROME 0x3E
64 #define ERROR_CHECK 0x3F
65
66 #define DMA_PCI_ADDR 0x40
67 #define DMA_LOCAL_ADDR 0x48
68 #define DMA_TRANSFER_SIZE 0x50
69 #define DMA_DESCRIPTOR_ADDR 0x58
70 #define DMA_SEMAPHORE_ADDR 0x60
71 #define DMA_STATUS_CTRL 0x68
72 #define DMASCR_GO 0x00001
73 #define DMASCR_TRANSFER_READ 0x00002
74 #define DMASCR_CHAIN_EN 0x00004
75 #define DMASCR_SEM_EN 0x00010
76 #define DMASCR_DMA_COMP_EN 0x00020
77 #define DMASCR_CHAIN_COMP_EN 0x00040
78 #define DMASCR_ERR_INT_EN 0x00080
79 #define DMASCR_PARITY_INT_EN 0x00100
80 #define DMASCR_ANY_ERR 0x00800
81 #define DMASCR_MBE_ERR 0x01000
82 #define DMASCR_PARITY_ERR_REP 0x02000
83 #define DMASCR_PARITY_ERR_DET 0x04000
84 #define DMASCR_SYSTEM_ERR_SIG 0x08000
85 #define DMASCR_TARGET_ABT 0x10000
86 #define DMASCR_MASTER_ABT 0x20000
87 #define DMASCR_DMA_COMPLETE 0x40000
88 #define DMASCR_CHAIN_COMPLETE 0x80000
89
90 /*
91 3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE
92 READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA
93 TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE
94 TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS
95 (31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6,
96 AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING
97 DMA READ OPERATIONS.
98 */
99 #define DMASCR_READ 0x60000000
100 #define DMASCR_READLINE 0xE0000000
101 #define DMASCR_READMULTI 0xC0000000
102
103
104 #define DMASCR_ERROR_MASK (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR | DMASCR_ANY_ERR)
105 #define DMASCR_HARD_ERROR (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR)
106
107 #define WINDOWMAP_WINNUM 0x7B
108
109 #define DMA_READ_FROM_HOST 0
110 #define DMA_WRITE_TO_HOST 1
111
112 struct mm_dma_desc {
113 __le64 pci_addr;
114 __le64 local_addr;
115 __le32 transfer_size;
116 u32 zero1;
117 __le64 next_desc_addr;
118 __le64 sem_addr;
119 __le32 control_bits;
120 u32 zero2;
121
122 dma_addr_t data_dma_handle;
123
124 /* Copy of the bits */
125 __le64 sem_control_bits;
126 } __attribute__((aligned(8)));
127
128 /* bits for card->flags */
129 #define UM_FLAG_DMA_IN_REGS 1
130 #define UM_FLAG_NO_BYTE_STATUS 2
131 #define UM_FLAG_NO_BATTREG 4
132 #define UM_FLAG_NO_BATT 8
133 #endif
134
|
This page was automatically generated by the
LXR engine.
|