1 /*
2 * Disk Array driver for Compaq SMART2 Controllers
3 * Copyright 1998 Compaq Computer Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
20 *
21 */
22 #ifndef ARRAYCMD_H
23 #define ARRAYCMD_H
24
25 #include <asm/types.h>
26 #if 0
27 #include <linux/blkdev.h>
28 #endif
29
30 /* for the Smart Array 42XX cards */
31 #define S42XX_REQUEST_PORT_OFFSET 0x40
32 #define S42XX_REPLY_INTR_MASK_OFFSET 0x34
33 #define S42XX_REPLY_PORT_OFFSET 0x44
34 #define S42XX_INTR_STATUS 0x30
35
36 #define S42XX_INTR_OFF 0x08
37 #define S42XX_INTR_PENDING 0x08
38
39 #define COMMAND_FIFO 0x04
40 #define COMMAND_COMPLETE_FIFO 0x08
41 #define INTR_MASK 0x0C
42 #define INTR_STATUS 0x10
43 #define INTR_PENDING 0x14
44
45 #define FIFO_NOT_EMPTY 0x01
46 #define FIFO_NOT_FULL 0x02
47
48 #define BIG_PROBLEM 0x40
49 #define LOG_NOT_CONF 2
50
51 #pragma pack(1)
52 typedef struct {
53 __u32 size;
54 __u32 addr;
55 } sg_t;
56
57 #define RCODE_NONFATAL 0x02
58 #define RCODE_FATAL 0x04
59 #define RCODE_INVREQ 0x10
60 typedef struct {
61 __u16 next;
62 __u8 cmd;
63 __u8 rcode;
64 __u32 blk;
65 __u16 blk_cnt;
66 __u8 sg_cnt;
67 __u8 reserved;
68 } rhdr_t;
69
70 #define SG_MAX 32
71 typedef struct {
72 rhdr_t hdr;
73 sg_t sg[SG_MAX];
74 __u32 bp;
75 } rblk_t;
76
77 typedef struct {
78 __u8 unit;
79 __u8 prio;
80 __u16 size;
81 } chdr_t;
82
83 #define CMD_RWREQ 0x00
84 #define CMD_IOCTL_PEND 0x01
85 #define CMD_IOCTL_DONE 0x02
86
87 typedef struct cmdlist {
88 chdr_t hdr;
89 rblk_t req;
90 __u32 size;
91 int retry_cnt;
92 __u32 busaddr;
93 int ctlr;
94 struct cmdlist *prev;
95 struct cmdlist *next;
96 struct request *rq;
97 int type;
98 } cmdlist_t;
99
100 #define ID_CTLR 0x11
101 typedef struct {
102 __u8 nr_drvs;
103 __u32 cfg_sig;
104 __u8 firm_rev[4];
105 __u8 rom_rev[4];
106 __u8 hw_rev;
107 __u32 bb_rev;
108 __u32 drv_present_map;
109 __u32 ext_drv_map;
110 __u32 board_id;
111 __u8 cfg_error;
112 __u32 non_disk_bits;
113 __u8 bad_ram_addr;
114 __u8 cpu_rev;
115 __u8 pdpi_rev;
116 __u8 epic_rev;
117 __u8 wcxc_rev;
118 __u8 marketing_rev;
119 __u8 ctlr_flags;
120 __u8 host_flags;
121 __u8 expand_dis;
122 __u8 scsi_chips;
123 __u32 max_req_blocks;
124 __u32 ctlr_clock;
125 __u8 drvs_per_bus;
126 __u16 big_drv_present_map[8];
127 __u16 big_ext_drv_map[8];
128 __u16 big_non_disk_map[8];
129 __u16 task_flags;
130 __u8 icl_bus;
131 __u8 red_modes;
132 __u8 cur_red_mode;
133 __u8 red_ctlr_stat;
134 __u8 red_fail_reason;
135 __u8 reserved[403];
136 } id_ctlr_t;
137
138 typedef struct {
139 __u16 cyl;
140 __u8 heads;
141 __u8 xsig;
142 __u8 psectors;
143 __u16 wpre;
144 __u8 maxecc;
145 __u8 drv_ctrl;
146 __u16 pcyls;
147 __u8 pheads;
148 __u16 landz;
149 __u8 sect_per_track;
150 __u8 cksum;
151 } drv_param_t;
152
153 #define ID_LOG_DRV 0x10
154 typedef struct {
155 __u16 blk_size;
156 __u32 nr_blks;
157 drv_param_t drv;
158 __u8 fault_tol;
159 __u8 reserved;
160 __u8 bios_disable;
161 } id_log_drv_t;
162
163 #define ID_LOG_DRV_EXT 0x18
164 typedef struct {
165 __u32 log_drv_id;
166 __u8 log_drv_label[64];
167 __u8 reserved[418];
168 } id_log_drv_ext_t;
169
170 #define SENSE_LOG_DRV_STAT 0x12
171 typedef struct {
172 __u8 status;
173 __u32 fail_map;
174 __u16 read_err[32];
175 __u16 write_err[32];
176 __u8 drv_err_data[256];
177 __u8 drq_timeout[32];
178 __u32 blks_to_recover;
179 __u8 drv_recovering;
180 __u16 remap_cnt[32];
181 __u32 replace_drv_map;
182 __u32 act_spare_map;
183 __u8 spare_stat;
184 __u8 spare_repl_map[32];
185 __u32 repl_ok_map;
186 __u8 media_exch;
187 __u8 cache_fail;
188 __u8 expn_fail;
189 __u8 unit_flags;
190 __u16 big_fail_map[8];
191 __u16 big_remap_map[128];
192 __u16 big_repl_map[8];
193 __u16 big_act_spare_map[8];
194 __u8 big_spar_repl_map[128];
195 __u16 big_repl_ok_map[8];
196 __u8 big_drv_rebuild;
197 __u8 reserved[36];
198 } sense_log_drv_stat_t;
199
200 #define START_RECOVER 0x13
201
202 #define ID_PHYS_DRV 0x15
203 typedef struct {
204 __u8 scsi_bus;
205 __u8 scsi_id;
206 __u16 blk_size;
207 __u32 nr_blks;
208 __u32 rsvd_blks;
209 __u8 drv_model[40];
210 __u8 drv_sn[40];
211 __u8 drv_fw[8];
212 __u8 scsi_iq_bits;
213 __u8 compaq_drv_stmp;
214 __u8 last_fail;
215 __u8 phys_drv_flags;
216 __u8 phys_drv_flags1;
217 __u8 scsi_lun;
218 __u8 phys_drv_flags2;
219 __u8 reserved;
220 __u32 spi_speed_rules;
221 __u8 phys_connector[2];
222 __u8 phys_box_on_bus;
223 __u8 phys_bay_in_box;
224 } id_phys_drv_t;
225
226 #define BLINK_DRV_LEDS 0x16
227 typedef struct {
228 __u32 blink_duration;
229 __u32 reserved;
230 __u8 blink[256];
231 __u8 reserved1[248];
232 } blink_drv_leds_t;
233
234 #define SENSE_BLINK_LEDS 0x17
235 typedef struct {
236 __u32 blink_duration;
237 __u32 btime_elap;
238 __u8 blink[256];
239 __u8 reserved1[248];
240 } sense_blink_leds_t;
241
242 #define IDA_READ 0x20
243 #define IDA_WRITE 0x30
244 #define IDA_WRITE_MEDIA 0x31
245 #define RESET_TO_DIAG 0x40
246 #define DIAG_PASS_THRU 0x41
247
248 #define SENSE_CONFIG 0x50
249 #define SET_CONFIG 0x51
250 typedef struct {
251 __u32 cfg_sig;
252 __u16 compat_port;
253 __u8 data_dist_mode;
254 __u8 surf_an_ctrl;
255 __u16 ctlr_phys_drv;
256 __u16 log_unit_phys_drv;
257 __u16 fault_tol_mode;
258 __u8 phys_drv_param[16];
259 drv_param_t drv;
260 __u32 drv_asgn_map;
261 __u16 dist_factor;
262 __u32 spare_asgn_map;
263 __u8 reserved[6];
264 __u16 os;
265 __u8 ctlr_order;
266 __u8 extra_info;
267 __u32 data_offs;
268 __u8 parity_backedout_write_drvs;
269 __u8 parity_dist_mode;
270 __u8 parity_shift_fact;
271 __u8 bios_disable_flag;
272 __u32 blks_on_vol;
273 __u32 blks_per_drv;
274 __u8 scratch[16];
275 __u16 big_drv_map[8];
276 __u16 big_spare_map[8];
277 __u8 ss_source_vol;
278 __u8 mix_drv_cap_range;
279 struct {
280 __u16 big_drv_map[8];
281 __u32 blks_per_drv;
282 __u16 fault_tol_mode;
283 __u16 dist_factor;
284 } MDC_range[4];
285 __u8 reserved1[248];
286 } config_t;
287
288 #define BYPASS_VOL_STATE 0x52
289 #define SS_CREATE_VOL 0x53
290 #define CHANGE_CONFIG 0x54
291 #define SENSE_ORIG_CONF 0x55
292 #define REORDER_LOG_DRV 0x56
293 typedef struct {
294 __u8 old_units[32];
295 } reorder_log_drv_t;
296
297 #define LABEL_LOG_DRV 0x57
298 typedef struct {
299 __u8 log_drv_label[64];
300 } label_log_drv_t;
301
302 #define SS_TO_VOL 0x58
303
304 #define SET_SURF_DELAY 0x60
305 typedef struct {
306 __u16 delay;
307 __u8 reserved[510];
308 } surf_delay_t;
309
310 #define SET_OVERHEAT_DELAY 0x61
311 typedef struct {
312 __u16 delay;
313 } overhead_delay_t;
314
315 #define SET_MP_DELAY
316 typedef struct {
317 __u16 delay;
318 __u8 reserved[510];
319 } mp_delay_t;
320
321 #define PASSTHRU_A 0x91
322 typedef struct {
323 __u8 target;
324 __u8 bus;
325 __u8 lun;
326 __u32 timeout;
327 __u32 flags;
328 __u8 status;
329 __u8 error;
330 __u8 cdb_len;
331 __u8 sense_error;
332 __u8 sense_key;
333 __u32 sense_info;
334 __u8 sense_code;
335 __u8 sense_qual;
336 __u32 residual;
337 __u8 reserved[4];
338 __u8 cdb[12];
339 } scsi_param_t;
340
341 #define RESUME_BACKGROUND_ACTIVITY 0x99
342 #define SENSE_CONTROLLER_PERFORMANCE 0xa8
343 #define FLUSH_CACHE 0xc2
344 #define COLLECT_BUFFER 0xd2
345 #define READ_FLASH_ROM 0xf6
346 #define WRITE_FLASH_ROM 0xf7
347 #pragma pack()
348
349 #endif /* ARRAYCMD_H */
350
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