1 /*
2 * Disk Array driver for Compaq SMART2 Controllers
3 * Copyright 1998 Compaq Computer Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
20 *
21 */
22 #include <linux/config.h> /* CONFIG_PROC_FS */
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/pci.h>
26 #include <linux/bio.h>
27 #include <linux/interrupt.h>
28 #include <linux/kernel.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include <linux/major.h>
32 #include <linux/fs.h>
33 #include <linux/blkpg.h>
34 #include <linux/timer.h>
35 #include <linux/proc_fs.h>
36 #include <linux/devfs_fs_kernel.h>
37 #include <linux/init.h>
38 #include <linux/hdreg.h>
39 #include <linux/spinlock.h>
40 #include <linux/blkdev.h>
41 #include <linux/genhd.h>
42 #include <asm/uaccess.h>
43 #include <asm/io.h>
44
45
46 #define SMART2_DRIVER_VERSION(maj,min,submin) ((maj<<16)|(min<<8)|(submin))
47
48 #define DRIVER_NAME "Compaq SMART2 Driver (v 2.6.0)"
49 #define DRIVER_VERSION SMART2_DRIVER_VERSION(2,6,0)
50
51 /* Embedded module documentation macros - see modules.h */
52 /* Original author Chris Frantz - Compaq Computer Corporation */
53 MODULE_AUTHOR("Compaq Computer Corporation");
54 MODULE_DESCRIPTION("Driver for Compaq Smart2 Array Controllers version 2.6.0");
55 MODULE_LICENSE("GPL");
56
57 #include "cpqarray.h"
58 #include "ida_cmd.h"
59 #include "smart1,2.h"
60 #include "ida_ioctl.h"
61
62 #define READ_AHEAD 128
63 #define NR_CMDS 128 /* This could probably go as high as ~400 */
64
65 #define MAX_CTLR 8
66 #define CTLR_SHIFT 8
67
68 #define CPQARRAY_DMA_MASK 0xFFFFFFFF /* 32 bit DMA */
69
70 static int nr_ctlr;
71 static ctlr_info_t *hba[MAX_CTLR];
72
73 static int eisa[8];
74
75 #define NR_PRODUCTS (sizeof(products)/sizeof(struct board_type))
76
77 /* board_id = Subsystem Device ID & Vendor ID
78 * product = Marketing Name for the board
79 * access = Address of the struct of function pointers
80 */
81 static struct board_type products[] = {
82 { 0x0040110E, "IDA", &smart1_access },
83 { 0x0140110E, "IDA-2", &smart1_access },
84 { 0x1040110E, "IAES", &smart1_access },
85 { 0x2040110E, "SMART", &smart1_access },
86 { 0x3040110E, "SMART-2/E", &smart2e_access },
87 { 0x40300E11, "SMART-2/P", &smart2_access },
88 { 0x40310E11, "SMART-2SL", &smart2_access },
89 { 0x40320E11, "Smart Array 3200", &smart2_access },
90 { 0x40330E11, "Smart Array 3100ES", &smart2_access },
91 { 0x40340E11, "Smart Array 221", &smart2_access },
92 { 0x40400E11, "Integrated Array", &smart4_access },
93 { 0x40480E11, "Compaq Raid LC2", &smart4_access },
94 { 0x40500E11, "Smart Array 4200", &smart4_access },
95 { 0x40510E11, "Smart Array 4250ES", &smart4_access },
96 { 0x40580E11, "Smart Array 431", &smart4_access },
97 };
98
99 /* define the PCI info for the PCI cards this driver can control */
100 const struct pci_device_id cpqarray_pci_device_id[] =
101 {
102 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
103 0x0E11, 0x4058, 0, 0, 0}, /* SA431 */
104 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
105 0x0E11, 0x4051, 0, 0, 0}, /* SA4250ES */
106 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
107 0x0E11, 0x4050, 0, 0, 0}, /* SA4200 */
108 { PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C1510,
109 0x0E11, 0x4048, 0, 0, 0}, /* LC2 */
110 { PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C1510,
111 0x0E11, 0x4040, 0, 0, 0}, /* Integrated Array */
112 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
113 0x0E11, 0x4034, 0, 0, 0}, /* SA 221 */
114 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
115 0x0E11, 0x4033, 0, 0, 0}, /* SA 3100ES*/
116 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
117 0x0E11, 0x4032, 0, 0, 0}, /* SA 3200*/
118 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
119 0x0E11, 0x4031, 0, 0, 0}, /* SA 2SL*/
120 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
121 0x0E11, 0x4030, 0, 0, 0}, /* SA 2P */
122 { 0 }
123 };
124
125 MODULE_DEVICE_TABLE(pci, cpqarray_pci_device_id);
126
127 static struct gendisk *ida_gendisk[MAX_CTLR][NWD];
128
129 /* Debug... */
130 #define DBG(s) do { s } while(0)
131 /* Debug (general info)... */
132 #define DBGINFO(s) do { } while(0)
133 /* Debug Paranoid... */
134 #define DBGP(s) do { } while(0)
135 /* Debug Extra Paranoid... */
136 #define DBGPX(s) do { } while(0)
137
138 int cpqarray_init_step2(void);
139 static int cpqarray_pci_init(ctlr_info_t *c, struct pci_dev *pdev);
140 static void __iomem *remap_pci_mem(ulong base, ulong size);
141 static int cpqarray_eisa_detect(void);
142 static int pollcomplete(int ctlr);
143 static void getgeometry(int ctlr);
144 static void start_fwbk(int ctlr);
145
146 static cmdlist_t * cmd_alloc(ctlr_info_t *h, int get_from_pool);
147 static void cmd_free(ctlr_info_t *h, cmdlist_t *c, int got_from_pool);
148
149 static void free_hba(int i);
150 static int alloc_cpqarray_hba(void);
151
152 static int sendcmd(
153 __u8 cmd,
154 int ctlr,
155 void *buff,
156 size_t size,
157 unsigned int blk,
158 unsigned int blkcnt,
159 unsigned int log_unit );
160
161 static int ida_open(struct inode *inode, struct file *filep);
162 static int ida_release(struct inode *inode, struct file *filep);
163 static int ida_ioctl(struct inode *inode, struct file *filep, unsigned int cmd, unsigned long arg);
164 static int ida_ctlr_ioctl(ctlr_info_t *h, int dsk, ida_ioctl_t *io);
165
166 static void do_ida_request(request_queue_t *q);
167 static void start_io(ctlr_info_t *h);
168
169 static inline void addQ(cmdlist_t **Qptr, cmdlist_t *c);
170 static inline cmdlist_t *removeQ(cmdlist_t **Qptr, cmdlist_t *c);
171 static inline void complete_buffers(struct bio *bio, int ok);
172 static inline void complete_command(cmdlist_t *cmd, int timeout);
173
174 static irqreturn_t do_ida_intr(int irq, void *dev_id, struct pt_regs * regs);
175 static void ida_timer(unsigned long tdata);
176 static int ida_revalidate(struct gendisk *disk);
177 static int revalidate_allvol(ctlr_info_t *host);
178 static int cpqarray_register_ctlr(int ctlr, struct pci_dev *pdev);
179
180 #ifdef CONFIG_PROC_FS
181 static void ida_procinit(int i);
182 static int ida_proc_get_info(char *buffer, char **start, off_t offset, int length, int *eof, void *data);
183 #else
184 static void ida_procinit(int i) {}
185 #endif
186
187 static inline drv_info_t *get_drv(struct gendisk *disk)
188 {
189 return disk->private_data;
190 }
191
192 static inline ctlr_info_t *get_host(struct gendisk *disk)
193 {
194 return disk->queue->queuedata;
195 }
196
197
198 static struct block_device_operations ida_fops = {
199 .owner = THIS_MODULE,
200 .open = ida_open,
201 .release = ida_release,
202 .ioctl = ida_ioctl,
203 .revalidate_disk= ida_revalidate,
204 };
205
206
207 #ifdef CONFIG_PROC_FS
208
209 static struct proc_dir_entry *proc_array;
210
211 /*
212 * Get us a file in /proc/array that says something about each controller.
213 * Create /proc/array if it doesn't exist yet.
214 */
215 static void __init ida_procinit(int i)
216 {
217 if (proc_array == NULL) {
218 proc_array = proc_mkdir("cpqarray", proc_root_driver);
219 if (!proc_array) return;
220 }
221
222 create_proc_read_entry(hba[i]->devname, 0, proc_array,
223 ida_proc_get_info, hba[i]);
224 }
225
226 /*
227 * Report information about this controller.
228 */
229 static int ida_proc_get_info(char *buffer, char **start, off_t offset, int length, int *eof, void *data)
230 {
231 off_t pos = 0;
232 off_t len = 0;
233 int size, i, ctlr;
234 ctlr_info_t *h = (ctlr_info_t*)data;
235 drv_info_t *drv;
236 #ifdef CPQ_PROC_PRINT_QUEUES
237 cmdlist_t *c;
238 unsigned long flags;
239 #endif
240
241 ctlr = h->ctlr;
242 size = sprintf(buffer, "%s: Compaq %s Controller\n"
243 " Board ID: 0x%08lx\n"
244 " Firmware Revision: %c%c%c%c\n"
245 " Controller Sig: 0x%08lx\n"
246 " Memory Address: 0x%08lx\n"
247 " I/O Port: 0x%04x\n"
248 " IRQ: %d\n"
249 " Logical drives: %d\n"
250 " Physical drives: %d\n\n"
251 " Current Q depth: %d\n"
252 " Max Q depth since init: %d\n\n",
253 h->devname,
254 h->product_name,
255 (unsigned long)h->board_id,
256 h->firm_rev[0], h->firm_rev[1], h->firm_rev[2], h->firm_rev[3],
257 (unsigned long)h->ctlr_sig, (unsigned long)h->vaddr,
258 (unsigned int) h->io_mem_addr, (unsigned int)h->intr,
259 h->log_drives, h->phys_drives,
260 h->Qdepth, h->maxQsinceinit);
261
262 pos += size; len += size;
263
264 size = sprintf(buffer+len, "Logical Drive Info:\n");
265 pos += size; len += size;
266
267 for(i=0; i<h->log_drives; i++) {
268 drv = &h->drv[i];
269 size = sprintf(buffer+len, "ida/c%dd%d: blksz=%d nr_blks=%d\n",
270 ctlr, i, drv->blk_size, drv->nr_blks);
271 pos += size; len += size;
272 }
273
274 #ifdef CPQ_PROC_PRINT_QUEUES
275 spin_lock_irqsave(IDA_LOCK(h->ctlr), flags);
276 size = sprintf(buffer+len, "\nCurrent Queues:\n");
277 pos += size; len += size;
278
279 c = h->reqQ;
280 size = sprintf(buffer+len, "reqQ = %p", c); pos += size; len += size;
281 if (c) c=c->next;
282 while(c && c != h->reqQ) {
283 size = sprintf(buffer+len, "->%p", c);
284 pos += size; len += size;
285 c=c->next;
286 }
287
288 c = h->cmpQ;
289 size = sprintf(buffer+len, "\ncmpQ = %p", c); pos += size; len += size;
290 if (c) c=c->next;
291 while(c && c != h->cmpQ) {
292 size = sprintf(buffer+len, "->%p", c);
293 pos += size; len += size;
294 c=c->next;
295 }
296
297 size = sprintf(buffer+len, "\n"); pos += size; len += size;
298 spin_unlock_irqrestore(IDA_LOCK(h->ctlr), flags);
299 #endif
300 size = sprintf(buffer+len, "nr_allocs = %d\nnr_frees = %d\n",
301 h->nr_allocs, h->nr_frees);
302 pos += size; len += size;
303
304 *eof = 1;
305 *start = buffer+offset;
306 len -= offset;
307 if (len>length)
308 len = length;
309 return len;
310 }
311 #endif /* CONFIG_PROC_FS */
312
313 module_param_array(eisa, int, NULL, 0);
314
315 /* This is a bit of a hack,
316 * necessary to support both eisa and pci
317 */
318 int __init cpqarray_init(void)
319 {
320 return (cpqarray_init_step2());
321 }
322
323 static void release_io_mem(ctlr_info_t *c)
324 {
325 /* if IO mem was not protected do nothing */
326 if( c->io_mem_addr == 0)
327 return;
328 release_region(c->io_mem_addr, c->io_mem_length);
329 c->io_mem_addr = 0;
330 c->io_mem_length = 0;
331 }
332
333 static void __devexit cpqarray_remove_one(int i)
334 {
335 int j;
336 char buff[4];
337
338 /* sendcmd will turn off interrupt, and send the flush...
339 * To write all data in the battery backed cache to disks
340 * no data returned, but don't want to send NULL to sendcmd */
341 if( sendcmd(FLUSH_CACHE, i, buff, 4, 0, 0, 0))
342 {
343 printk(KERN_WARNING "Unable to flush cache on controller %d\n",
344 i);
345 }
346 free_irq(hba[i]->intr, hba[i]);
347 iounmap(hba[i]->vaddr);
348 unregister_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname);
349 del_timer(&hba[i]->timer);
350 remove_proc_entry(hba[i]->devname, proc_array);
351 pci_free_consistent(hba[i]->pci_dev,
352 NR_CMDS * sizeof(cmdlist_t), (hba[i]->cmd_pool),
353 hba[i]->cmd_pool_dhandle);
354 kfree(hba[i]->cmd_pool_bits);
355 for(j = 0; j < NWD; j++) {
356 if (ida_gendisk[i][j]->flags & GENHD_FL_UP)
357 del_gendisk(ida_gendisk[i][j]);
358 devfs_remove("ida/c%dd%d",i,j);
359 put_disk(ida_gendisk[i][j]);
360 }
361 blk_cleanup_queue(hba[i]->queue);
362 release_io_mem(hba[i]);
363 free_hba(i);
364 }
365
366 static void __devexit cpqarray_remove_one_pci (struct pci_dev *pdev)
367 {
368 int i;
369 ctlr_info_t *tmp_ptr;
370
371 if (pci_get_drvdata(pdev) == NULL) {
372 printk( KERN_ERR "cpqarray: Unable to remove device \n");
373 return;
374 }
375
376 tmp_ptr = pci_get_drvdata(pdev);
377 i = tmp_ptr->ctlr;
378 if (hba[i] == NULL) {
379 printk(KERN_ERR "cpqarray: controller %d appears to have"
380 "already been removed \n", i);
381 return;
382 }
383 pci_set_drvdata(pdev, NULL);
384
385 cpqarray_remove_one(i);
386 }
387
388 /* removing an instance that was not removed automatically..
389 * must be an eisa card.
390 */
391 static void __devexit cpqarray_remove_one_eisa (int i)
392 {
393 if (hba[i] == NULL) {
394 printk(KERN_ERR "cpqarray: controller %d appears to have"
395 "already been removed \n", i);
396 return;
397 }
398 cpqarray_remove_one(i);
399 }
400
401 /* pdev is NULL for eisa */
402 static int cpqarray_register_ctlr( int i, struct pci_dev *pdev)
403 {
404 request_queue_t *q;
405 int j;
406
407 /*
408 * register block devices
409 * Find disks and fill in structs
410 * Get an interrupt, set the Q depth and get into /proc
411 */
412
413 /* If this successful it should insure that we are the only */
414 /* instance of the driver */
415 if (register_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname)) {
416 goto Enomem4;
417 }
418 hba[i]->access.set_intr_mask(hba[i], 0);
419 if (request_irq(hba[i]->intr, do_ida_intr,
420 SA_INTERRUPT|SA_SHIRQ|SA_SAMPLE_RANDOM,
421 hba[i]->devname, hba[i]))
422 {
423 printk(KERN_ERR "cpqarray: Unable to get irq %d for %s\n",
424 hba[i]->intr, hba[i]->devname);
425 goto Enomem3;
426 }
427
428 for (j=0; j<NWD; j++) {
429 ida_gendisk[i][j] = alloc_disk(1 << NWD_SHIFT);
430 if (!ida_gendisk[i][j])
431 goto Enomem2;
432 }
433
434 hba[i]->cmd_pool = (cmdlist_t *)pci_alloc_consistent(
435 hba[i]->pci_dev, NR_CMDS * sizeof(cmdlist_t),
436 &(hba[i]->cmd_pool_dhandle));
437 hba[i]->cmd_pool_bits = kmalloc(
438 ((NR_CMDS+BITS_PER_LONG-1)/BITS_PER_LONG)*sizeof(unsigned long),
439 GFP_KERNEL);
440
441 if (!hba[i]->cmd_pool_bits || !hba[i]->cmd_pool)
442 goto Enomem1;
443
444 memset(hba[i]->cmd_pool, 0, NR_CMDS * sizeof(cmdlist_t));
445 memset(hba[i]->cmd_pool_bits, 0, ((NR_CMDS+BITS_PER_LONG-1)/BITS_PER_LONG)*sizeof(unsigned long));
446 printk(KERN_INFO "cpqarray: Finding drives on %s",
447 hba[i]->devname);
448
449 spin_lock_init(&hba[i]->lock);
450 q = blk_init_queue(do_ida_request, &hba[i]->lock);
451 if (!q)
452 goto Enomem1;
453
454 hba[i]->queue = q;
455 q->queuedata = hba[i];
456
457 getgeometry(i);
458 start_fwbk(i);
459
460 ida_procinit(i);
461
462 if (pdev)
463 blk_queue_bounce_limit(q, hba[i]->pci_dev->dma_mask);
464
465 /* This is a hardware imposed limit. */
466 blk_queue_max_hw_segments(q, SG_MAX);
467
468 /* This is a driver limit and could be eliminated. */
469 blk_queue_max_phys_segments(q, SG_MAX);
470
471 init_timer(&hba[i]->timer);
472 hba[i]->timer.expires = jiffies + IDA_TIMER;
473 hba[i]->timer.data = (unsigned long)hba[i];
474 hba[i]->timer.function = ida_timer;
475 add_timer(&hba[i]->timer);
476
477 /* Enable IRQ now that spinlock and rate limit timer are set up */
478 hba[i]->access.set_intr_mask(hba[i], FIFO_NOT_EMPTY);
479
480 for(j=0; j<NWD; j++) {
481 struct gendisk *disk = ida_gendisk[i][j];
482 drv_info_t *drv = &hba[i]->drv[j];
483 sprintf(disk->disk_name, "ida/c%dd%d", i, j);
484 disk->major = COMPAQ_SMART2_MAJOR + i;
485 disk->first_minor = j<<NWD_SHIFT;
486 disk->fops = &ida_fops;
487 if (j && !drv->nr_blks)
488 continue;
489 blk_queue_hardsect_size(hba[i]->queue, drv->blk_size);
490 set_capacity(disk, drv->nr_blks);
491 disk->queue = hba[i]->queue;
492 disk->private_data = drv;
493 add_disk(disk);
494 }
495
496 /* done ! */
497 return(i);
498
499 Enomem1:
500 nr_ctlr = i;
501 kfree(hba[i]->cmd_pool_bits);
502 if (hba[i]->cmd_pool)
503 pci_free_consistent(hba[i]->pci_dev, NR_CMDS*sizeof(cmdlist_t),
504 hba[i]->cmd_pool, hba[i]->cmd_pool_dhandle);
505 Enomem2:
506 while (j--) {
507 put_disk(ida_gendisk[i][j]);
508 ida_gendisk[i][j] = NULL;
509 }
510 free_irq(hba[i]->intr, hba[i]);
511 Enomem3:
512 unregister_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname);
513 Enomem4:
514 if (pdev)
515 pci_set_drvdata(pdev, NULL);
516 release_io_mem(hba[i]);
517 free_hba(i);
518
519 printk( KERN_ERR "cpqarray: out of memory");
520
521 return -1;
522 }
523
524 static int __init cpqarray_init_one( struct pci_dev *pdev,
525 const struct pci_device_id *ent)
526 {
527 int i;
528
529 printk(KERN_DEBUG "cpqarray: Device 0x%x has been found at"
530 " bus %d dev %d func %d\n",
531 pdev->device, pdev->bus->number, PCI_SLOT(pdev->devfn),
532 PCI_FUNC(pdev->devfn));
533 i = alloc_cpqarray_hba();
534 if( i < 0 )
535 return (-1);
536 memset(hba[i], 0, sizeof(ctlr_info_t));
537 sprintf(hba[i]->devname, "ida%d", i);
538 hba[i]->ctlr = i;
539 /* Initialize the pdev driver private data */
540 pci_set_drvdata(pdev, hba[i]);
541
542 if (cpqarray_pci_init(hba[i], pdev) != 0) {
543 pci_set_drvdata(pdev, NULL);
544 release_io_mem(hba[i]);
545 free_hba(i);
546 return -1;
547 }
548
549 return (cpqarray_register_ctlr(i, pdev));
550 }
551
552 static struct pci_driver cpqarray_pci_driver = {
553 .name = "cpqarray",
554 .probe = cpqarray_init_one,
555 .remove = __devexit_p(cpqarray_remove_one_pci),
556 .id_table = cpqarray_pci_device_id,
557 };
558
559 /*
560 * This is it. Find all the controllers and register them.
561 * returns the number of block devices registered.
562 */
563 int __init cpqarray_init_step2(void)
564 {
565 int num_cntlrs_reg = 0;
566 int i;
567 int rc = 0;
568
569 /* detect controllers */
570 printk(DRIVER_NAME "\n");
571
572 rc = pci_register_driver(&cpqarray_pci_driver);
573 if (rc)
574 return rc;
575 cpqarray_eisa_detect();
576
577 for (i=0; i < MAX_CTLR; i++) {
578 if (hba[i] != NULL)
579 num_cntlrs_reg++;
580 }
581
582 return(num_cntlrs_reg);
583 }
584
585 /* Function to find the first free pointer into our hba[] array */
586 /* Returns -1 if no free entries are left. */
587 static int alloc_cpqarray_hba(void)
588 {
589 int i;
590
591 for(i=0; i< MAX_CTLR; i++) {
592 if (hba[i] == NULL) {
593 hba[i] = kmalloc(sizeof(ctlr_info_t), GFP_KERNEL);
594 if(hba[i]==NULL) {
595 printk(KERN_ERR "cpqarray: out of memory.\n");
596 return (-1);
597 }
598 return (i);
599 }
600 }
601 printk(KERN_WARNING "cpqarray: This driver supports a maximum"
602 " of 8 controllers.\n");
603 return(-1);
604 }
605
606 static void free_hba(int i)
607 {
608 kfree(hba[i]);
609 hba[i]=NULL;
610 }
611
612 /*
613 * Find the IO address of the controller, its IRQ and so forth. Fill
614 * in some basic stuff into the ctlr_info_t structure.
615 */
616 static int cpqarray_pci_init(ctlr_info_t *c, struct pci_dev *pdev)
617 {
618 ushort vendor_id, device_id, command;
619 unchar cache_line_size, latency_timer;
620 unchar irq, revision;
621 unsigned long addr[6];
622 __u32 board_id;
623
624 int i;
625
626 c->pci_dev = pdev;
627 if (pci_enable_device(pdev)) {
628 printk(KERN_ERR "cpqarray: Unable to Enable PCI device\n");
629 return -1;
630 }
631 vendor_id = pdev->vendor;
632 device_id = pdev->device;
633 irq = pdev->irq;
634
635 for(i=0; i<6; i++)
636 addr[i] = pci_resource_start(pdev, i);
637
638 if (pci_set_dma_mask(pdev, CPQARRAY_DMA_MASK) != 0)
639 {
640 printk(KERN_ERR "cpqarray: Unable to set DMA mask\n");
641 return -1;
642 }
643
644 pci_read_config_word(pdev, PCI_COMMAND, &command);
645 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
646 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line_size);
647 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency_timer);
648
649 pci_read_config_dword(pdev, 0x2c, &board_id);
650
651 /* check to see if controller has been disabled */
652 if(!(command & 0x02)) {
653 printk(KERN_WARNING
654 "cpqarray: controller appears to be disabled\n");
655 return(-1);
656 }
657
658 DBGINFO(
659 printk("vendor_id = %x\n", vendor_id);
660 printk("device_id = %x\n", device_id);
661 printk("command = %x\n", command);
662 for(i=0; i<6; i++)
663 printk("addr[%d] = %lx\n", i, addr[i]);
664 printk("revision = %x\n", revision);
665 printk("irq = %x\n", irq);
666 printk("cache_line_size = %x\n", cache_line_size);
667 printk("latency_timer = %x\n", latency_timer);
668 printk("board_id = %x\n", board_id);
669 );
670
671 c->intr = irq;
672
673 for(i=0; i<6; i++) {
674 if (pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE_IO)
675 { /* IO space */
676 c->io_mem_addr = addr[i];
677 c->io_mem_length = pci_resource_end(pdev, i)
678 - pci_resource_start(pdev, i) + 1;
679 if(!request_region( c->io_mem_addr, c->io_mem_length,
680 "cpqarray"))
681 {
682 printk( KERN_WARNING "cpqarray I/O memory range already in use addr %lx length = %ld\n", c->io_mem_addr, c->io_mem_length);
683 c->io_mem_addr = 0;
684 c->io_mem_length = 0;
685 }
686 break;
687 }
688 }
689
690 c->paddr = 0;
691 for(i=0; i<6; i++)
692 if (!(pci_resource_flags(pdev, i) &
693 PCI_BASE_ADDRESS_SPACE_IO)) {
694 c->paddr = pci_resource_start (pdev, i);
695 break;
696 }
697 if (!c->paddr)
698 return -1;
699 c->vaddr = remap_pci_mem(c->paddr, 128);
700 if (!c->vaddr)
701 return -1;
702 c->board_id = board_id;
703
704 for(i=0; i<NR_PRODUCTS; i++) {
705 if (board_id == products[i].board_id) {
706 c->product_name = products[i].product_name;
707 c->access = *(products[i].access);
708 break;
709 }
710 }
711 if (i == NR_PRODUCTS) {
712 printk(KERN_WARNING "cpqarray: Sorry, I don't know how"
713 " to access the SMART Array controller %08lx\n",
714 (unsigned long)board_id);
715 return -1;
716 }
717
718 return 0;
719 }
720
721 /*
722 * Map (physical) PCI mem into (virtual) kernel space
723 */
724 static void __iomem *remap_pci_mem(ulong base, ulong size)
725 {
726 ulong page_base = ((ulong) base) & PAGE_MASK;
727 ulong page_offs = ((ulong) base) - page_base;
728 void __iomem *page_remapped = ioremap(page_base, page_offs+size);
729
730 return (page_remapped ? (page_remapped + page_offs) : NULL);
731 }
732
733 #ifndef MODULE
734 /*
735 * Config string is a comma separated set of i/o addresses of EISA cards.
736 */
737 static int cpqarray_setup(char *str)
738 {
739 int i, ints[9];
740
741 (void)get_options(str, ARRAY_SIZE(ints), ints);
742
743 for(i=0; i<ints[0] && i<8; i++)
744 eisa[i] = ints[i+1];
745 return 1;
746 }
747
748 __setup("smart2=", cpqarray_setup);
749
750 #endif
751
752 /*
753 * Find an EISA controller's signature. Set up an hba if we find it.
754 */
755 static int cpqarray_eisa_detect(void)
756 {
757 int i=0, j;
758 __u32 board_id;
759 int intr;
760 int ctlr;
761 int num_ctlr = 0;
762
763 while(i<8 && eisa[i]) {
764 ctlr = alloc_cpqarray_hba();
765 if(ctlr == -1)
766 break;
767 board_id = inl(eisa[i]+0xC80);
768 for(j=0; j < NR_PRODUCTS; j++)
769 if (board_id == products[j].board_id)
770 break;
771
772 if (j == NR_PRODUCTS) {
773 printk(KERN_WARNING "cpqarray: Sorry, I don't know how"
774 " to access the SMART Array controller %08lx\n", (unsigned long)board_id);
775 continue;
776 }
777
778 memset(hba[ctlr], 0, sizeof(ctlr_info_t));
779 hba[ctlr]->io_mem_addr = eisa[i];
780 hba[ctlr]->io_mem_length = 0x7FF;
781 if(!request_region(hba[ctlr]->io_mem_addr,
782 hba[ctlr]->io_mem_length,
783 "cpqarray"))
784 {
785 printk(KERN_WARNING "cpqarray: I/O range already in "
786 "use addr = %lx length = %ld\n",
787 hba[ctlr]->io_mem_addr,
788 hba[ctlr]->io_mem_length);
789 free_hba(ctlr);
790 continue;
791 }
792
793 /*
794 * Read the config register to find our interrupt
795 */
796 intr = inb(eisa[i]+0xCC0) >> 4;
797 if (intr & 1) intr = 11;
798 else if (intr & 2) intr = 10;
799 else if (intr & 4) intr = 14;
800 else if (intr & 8) intr = 15;
801
802 hba[ctlr]->intr = intr;
803 sprintf(hba[ctlr]->devname, "ida%d", nr_ctlr);
804 hba[ctlr]->product_name = products[j].product_name;
805 hba[ctlr]->access = *(products[j].access);
806 hba[ctlr]->ctlr = ctlr;
807 hba[ctlr]->board_id = board_id;
808 hba[ctlr]->pci_dev = NULL; /* not PCI */
809
810 DBGINFO(
811 printk("i = %d, j = %d\n", i, j);
812 printk("irq = %x\n", intr);
813 printk("product name = %s\n", products[j].product_name);
814 printk("board_id = %x\n", board_id);
815 );
816
817 num_ctlr++;
818 i++;
819
820 if (cpqarray_register_ctlr(ctlr, NULL) == -1)
821 printk(KERN_WARNING
822 "cpqarray: Can't register EISA controller %d\n",
823 ctlr);
824
825 }
826
827 return num_ctlr;
828 }
829
830 /*
831 * Open. Make sure the device is really there.
832 */
833 static int ida_open(struct inode *inode, struct file *filep)
834 {
835 drv_info_t *drv = get_drv(inode->i_bdev->bd_disk);
836 ctlr_info_t *host = get_host(inode->i_bdev->bd_disk);
837
838 DBGINFO(printk("ida_open %s\n", inode->i_bdev->bd_disk->disk_name));
839 /*
840 * Root is allowed to open raw volume zero even if it's not configured
841 * so array config can still work. I don't think I really like this,
842 * but I'm already using way to many device nodes to claim another one
843 * for "raw controller".
844 */
845 if (!drv->nr_blks) {
846 if (!capable(CAP_SYS_RAWIO))
847 return -ENXIO;
848 if (!capable(CAP_SYS_ADMIN) && drv != host->drv)
849 return -ENXIO;
850 }
851 host->usage_count++;
852 return 0;
853 }
854
855 /*
856 * Close. Sync first.
857 */
858 static int ida_release(struct inode *inode, struct file *filep)
859 {
860 ctlr_info_t *host = get_host(inode->i_bdev->bd_disk);
861 host->usage_count--;
862 return 0;
863 }
864
865 /*
866 * Enqueuing and dequeuing functions for cmdlists.
867 */
868 static inline void addQ(cmdlist_t **Qptr, cmdlist_t *c)
869 {
870 if (*Qptr == NULL) {
871 *Qptr = c;
872 c->next = c->prev = c;
873 } else {
874 c->prev = (*Qptr)->prev;
875 c->next = (*Qptr);
876 (*Qptr)->prev->next = c;
877 (*Qptr)->prev = c;
878 }
879 }
880
881 static inline cmdlist_t *removeQ(cmdlist_t **Qptr, cmdlist_t *c)
882 {
883 if (c && c->next != c) {
884 if (*Qptr == c) *Qptr = c->next;
885 c->prev->next = c->next;
886 c->next->prev = c->prev;
887 } else {
888 *Qptr = NULL;
889 }
890 return c;
891 }
892
893 /*
894 * Get a request and submit it to the controller.
895 * This routine needs to grab all the requests it possibly can from the
896 * req Q and submit them. Interrupts are off (and need to be off) when you
897 * are in here (either via the dummy do_ida_request functions or by being
898 * called from the interrupt handler
899 */
900 static void do_ida_request(request_queue_t *q)
901 {
902 ctlr_info_t *h = q->queuedata;
903 cmdlist_t *c;
904 struct request *creq;
905 struct scatterlist tmp_sg[SG_MAX];
906 int i, dir, seg;
907
908 if (blk_queue_plugged(q))
909 goto startio;
910
911 queue_next:
912 creq = elv_next_request(q);
913 if (!creq)
914 goto startio;
915
916 if (creq->nr_phys_segments > SG_MAX)
917 BUG();
918
919 if ((c = cmd_alloc(h,1)) == NULL)
920 goto startio;
921
922 blkdev_dequeue_request(creq);
923
924 c->ctlr = h->ctlr;
925 c->hdr.unit = (drv_info_t *)(creq->rq_disk->private_data) - h->drv;
926 c->hdr.size = sizeof(rblk_t) >> 2;
927 c->size += sizeof(rblk_t);
928
929 c->req.hdr.blk = creq->sector;
930 c->rq = creq;
931 DBGPX(
932 printk("sector=%d, nr_sectors=%d\n", creq->sector, creq->nr_sectors);
933 );
934 seg = blk_rq_map_sg(q, creq, tmp_sg);
935
936 /* Now do all the DMA Mappings */
937 if (rq_data_dir(creq) == READ)
938 dir = PCI_DMA_FROMDEVICE;
939 else
940 dir = PCI_DMA_TODEVICE;
941 for( i=0; i < seg; i++)
942 {
943 c->req.sg[i].size = tmp_sg[i].length;
944 c->req.sg[i].addr = (__u32) pci_map_page(h->pci_dev,
945 tmp_sg[i].page,
946 tmp_sg[i].offset,
947 tmp_sg[i].length, dir);
948 }
949 DBGPX( printk("Submitting %d sectors in %d segments\n", creq->nr_sectors, seg); );
950 c->req.hdr.sg_cnt = seg;
951 c->req.hdr.blk_cnt = creq->nr_sectors;
952 c->req.hdr.cmd = (rq_data_dir(creq) == READ) ? IDA_READ : IDA_WRITE;
953 c->type = CMD_RWREQ;
954
955 /* Put the request on the tail of the request queue */
956 addQ(&h->reqQ, c);
957 h->Qdepth++;
958 if (h->Qdepth > h->maxQsinceinit)
959 h->maxQsinceinit = h->Qdepth;
960
961 goto queue_next;
962
963 startio:
964 start_io(h);
965 }
966
967 /*
968 * start_io submits everything on a controller's request queue
969 * and moves it to the completion queue.
970 *
971 * Interrupts had better be off if you're in here
972 */
973 static void start_io(ctlr_info_t *h)
974 {
975 cmdlist_t *c;
976
977 while((c = h->reqQ) != NULL) {
978 /* Can't do anything if we're busy */
979 if (h->access.fifo_full(h) == 0)
980 return;
981
982 /* Get the first entry from the request Q */
983 removeQ(&h->reqQ, c);
984 h->Qdepth--;
985
986 /* Tell the controller to do our bidding */
987 h->access.submit_command(h, c);
988
989 /* Get onto the completion Q */
990 addQ(&h->cmpQ, c);
991 }
992 }
993
994 static inline void complete_buffers(struct bio *bio, int ok)
995 {
996 struct bio *xbh;
997 while(bio) {
998 int nr_sectors = bio_sectors(bio);
999
1000 xbh = bio->bi_next;
1001 bio->bi_next = NULL;
1002
1003 blk_finished_io(nr_sectors);
1004 bio_endio(bio, nr_sectors << 9, ok ? 0 : -EIO);
1005
1006 bio = xbh;
1007 }
1008 }
1009 /*
1010 * Mark all buffers that cmd was responsible for
1011 */
1012 static inline void complete_command(cmdlist_t *cmd, int timeout)
1013 {
1014 int ok=1;
1015 int i, ddir;
1016
1017 if (cmd->req.hdr.rcode & RCODE_NONFATAL &&
1018 (hba[cmd->ctlr]->misc_tflags & MISC_NONFATAL_WARN) == 0) {
1019 printk(KERN_NOTICE "Non Fatal error on ida/c%dd%d\n",
1020 cmd->ctlr, cmd->hdr.unit);
1021 hba[cmd->ctlr]->misc_tflags |= MISC_NONFATAL_WARN;
1022 }
1023 if (cmd->req.hdr.rcode & RCODE_FATAL) {
1024 printk(KERN_WARNING "Fatal error on ida/c%dd%d\n",
1025 cmd->ctlr, cmd->hdr.unit);
1026 ok = 0;
1027 }
1028 if (cmd->req.hdr.rcode & RCODE_INVREQ) {
1029 printk(KERN_WARNING "Invalid request on ida/c%dd%d = (cmd=%x sect=%d cnt=%d sg=%d ret=%x)\n",
1030 cmd->ctlr, cmd->hdr.unit, cmd->req.hdr.cmd,
1031 cmd->req.hdr.blk, cmd->req.hdr.blk_cnt,
1032 cmd->req.hdr.sg_cnt, cmd->req.hdr.rcode);
1033 ok = 0;
1034 }
1035 if (timeout) ok = 0;
1036 /* unmap the DMA mapping for all the scatter gather elements */
1037 if (cmd->req.hdr.cmd == IDA_READ)
1038 ddir = PCI_DMA_FROMDEVICE;
1039 else
1040 ddir = PCI_DMA_TODEVICE;
1041 for(i=0; i<cmd->req.hdr.sg_cnt; i++)
1042 pci_unmap_page(hba[cmd->ctlr]->pci_dev, cmd->req.sg[i].addr,
1043 cmd->req.sg[i].size, ddir);
1044
1045 complete_buffers(cmd->rq->bio, ok);
1046
1047 DBGPX(printk("Done with %p\n", cmd->rq););
1048 end_that_request_last(cmd->rq);
1049 }
1050
1051 /*
1052 * The controller will interrupt us upon completion of commands.
1053 * Find the command on the completion queue, remove it, tell the OS and
1054 * try to queue up more IO
1055 */
1056 static irqreturn_t do_ida_intr(int irq, void *dev_id, struct pt_regs *regs)
1057 {
1058 ctlr_info_t *h = dev_id;
1059 cmdlist_t *c;
1060 unsigned long istat;
1061 unsigned long flags;
1062 __u32 a,a1;
1063
1064 istat = h->access.intr_pending(h);
1065 /* Is this interrupt for us? */
1066 if (istat == 0)
1067 return IRQ_NONE;
1068
1069 /*
1070 * If there are completed commands in the completion queue,
1071 * we had better do something about it.
1072 */
1073 spin_lock_irqsave(IDA_LOCK(h->ctlr), flags);
1074 if (istat & FIFO_NOT_EMPTY) {
1075 while((a = h->access.command_completed(h))) {
1076 a1 = a; a &= ~3;
1077 if ((c = h->cmpQ) == NULL)
1078 {
1079 printk(KERN_WARNING "cpqarray: Completion of %08lx ignored\n", (unsigned long)a1);
1080 continue;
1081 }
1082 while(c->busaddr != a) {
1083 c = c->next;
1084 if (c == h->cmpQ)
1085 break;
1086 }
1087 /*
1088 * If we've found the command, take it off the
1089 * completion Q and free it
1090 */
1091 if (c->busaddr == a) {
1092 removeQ(&h->cmpQ, c);
1093 /* Check for invalid command.
1094 * Controller returns command error,
1095 * But rcode = 0.
1096 */
1097
1098 if((a1 & 0x03) && (c->req.hdr.rcode == 0))
1099 {
1100 c->req.hdr.rcode = RCODE_INVREQ;
1101 }
1102 if (c->type == CMD_RWREQ) {
1103 complete_command(c, 0);
1104 cmd_free(h, c, 1);
1105 } else if (c->type == CMD_IOCTL_PEND) {
1106 c->type = CMD_IOCTL_DONE;
1107 }
1108 continue;
1109 }
1110 }
1111 }
1112
1113 /*
1114 * See if we can queue up some more IO
1115 */
1116 do_ida_request(h->queue);
1117 spin_unlock_irqrestore(IDA_LOCK(h->ctlr), flags);
1118 return IRQ_HANDLED;
1119 }
1120
1121 /*
1122 * This timer was for timing out requests that haven't happened after
1123 * IDA_TIMEOUT. That wasn't such a good idea. This timer is used to
1124 * reset a flags structure so we don't flood the user with
1125 * "Non-Fatal error" messages.
1126 */
1127 static void ida_timer(unsigned long tdata)
1128 {
1129 ctlr_info_t *h = (ctlr_info_t*)tdata;
1130
1131 h->timer.expires = jiffies + IDA_TIMER;
1132 add_timer(&h->timer);
1133 h->misc_tflags = 0;
1134 }
1135
1136 /*
1137 * ida_ioctl does some miscellaneous stuff like reporting drive geometry,
1138 * setting readahead and submitting commands from userspace to the controller.
1139 */
1140 static int ida_ioctl(struct inode *inode, struct file *filep, unsigned int cmd, unsigned long arg)
1141 {
1142 drv_info_t *drv = get_drv(inode->i_bdev->bd_disk);
1143 ctlr_info_t *host = get_host(inode->i_bdev->bd_disk);
1144 int error;
1145 int diskinfo[4];
1146 struct hd_geometry __user *geo = (struct hd_geometry __user *)arg;
1147 ida_ioctl_t __user *io = (ida_ioctl_t __user *)arg;
1148 ida_ioctl_t *my_io;
1149
1150 switch(cmd) {
1151 case HDIO_GETGEO:
1152 if (drv->cylinders) {
1153 diskinfo[0] = drv->heads;
1154 diskinfo[1] = drv->sectors;
1155 diskinfo[2] = drv->cylinders;
1156 } else {
1157 diskinfo[0] = 0xff;
1158 diskinfo[1] = 0x3f;
1159 diskinfo[2] = drv->nr_blks / (0xff*0x3f);
1160 }
1161 put_user(diskinfo[0], &geo->heads);
1162 put_user(diskinfo[1], &geo->sectors);
1163 put_user(diskinfo[2], &geo->cylinders);
1164 put_user(get_start_sect(inode->i_bdev), &geo->start);
1165 return 0;
1166 case IDAGETDRVINFO:
1167 if (copy_to_user(&io->c.drv, drv, sizeof(drv_info_t)))
1168 return -EFAULT;
1169 return 0;
1170 case IDAPASSTHRU:
1171 if (!capable(CAP_SYS_RAWIO))
1172 return -EPERM;
1173 my_io = kmalloc(sizeof(ida_ioctl_t), GFP_KERNEL);
1174 if (!my_io)
1175 return -ENOMEM;
1176 error = -EFAULT;
1177 if (copy_from_user(my_io, io, sizeof(*my_io)))
1178 goto out_passthru;
1179 error = ida_ctlr_ioctl(host, drv - host->drv, my_io);
1180 if (error)
1181 goto out_passthru;
1182 error = -EFAULT;
1183 if (copy_to_user(io, my_io, sizeof(*my_io)))
1184 goto out_passthru;
1185 error = 0;
1186 out_passthru:
1187 kfree(my_io);
1188 return error;
1189 case IDAGETCTLRSIG:
1190 if (!arg) return -EINVAL;
1191 put_user(host->ctlr_sig, (int __user *)arg);
1192 return 0;
1193 case IDAREVALIDATEVOLS:
1194 if (iminor(inode) != 0)
1195 return -ENXIO;
1196 return revalidate_allvol(host);
1197 case IDADRIVERVERSION:
1198 if (!arg) return -EINVAL;
1199 put_user(DRIVER_VERSION, (unsigned long __user *)arg);
1200 return 0;
1201 case IDAGETPCIINFO:
1202 {
1203
1204 ida_pci_info_struct pciinfo;
1205
1206 if (!arg) return -EINVAL;
1207 pciinfo.bus = host->pci_dev->bus->number;
1208 pciinfo.dev_fn = host->pci_dev->devfn;
1209 pciinfo.board_id = host->board_id;
1210 if(copy_to_user((void __user *) arg, &pciinfo,
1211 sizeof( ida_pci_info_struct)))
1212 return -EFAULT;
1213 return(0);
1214 }
1215
1216 default:
1217 return -EINVAL;
1218 }
1219
1220 }
1221 /*
1222 * ida_ctlr_ioctl is for passing commands to the controller from userspace.
1223 * The command block (io) has already been copied to kernel space for us,
1224 * however, any elements in the sglist need to be copied to kernel space
1225 * or copied back to userspace.
1226 *
1227 * Only root may perform a controller passthru command, however I'm not doing
1228 * any serious sanity checking on the arguments. Doing an IDA_WRITE_MEDIA and
1229 * putting a 64M buffer in the sglist is probably a *bad* idea.
1230 */
1231 static int ida_ctlr_ioctl(ctlr_info_t *h, int dsk, ida_ioctl_t *io)
1232 {
1233 int ctlr = h->ctlr;
1234 cmdlist_t *c;
1235 void *p = NULL;
1236 unsigned long flags;
1237 int error;
1238
1239 if ((c = cmd_alloc(h, 0)) == NULL)
1240 return -ENOMEM;
1241 c->ctlr = ctlr;
1242 c->hdr.unit = (io->unit & UNITVALID) ? (io->unit & ~UNITVALID) : dsk;
1243 c->hdr.size = sizeof(rblk_t) >> 2;
1244 c->size += sizeof(rblk_t);
1245
1246 c->req.hdr.cmd = io->cmd;
1247 c->req.hdr.blk = io->blk;
1248 c->req.hdr.blk_cnt = io->blk_cnt;
1249 c->type = CMD_IOCTL_PEND;
1250
1251 /* Pre submit processing */
1252 switch(io->cmd) {
1253 case PASSTHRU_A:
1254 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1255 if (!p)
1256 {
1257 error = -ENOMEM;
1258 cmd_free(h, c, 0);
1259 return(error);
1260 }
1261 if (copy_from_user(p, io->sg[0].addr, io->sg[0].size)) {
1262 kfree(p);
1263 cmd_free(h, c, 0);
1264 return -EFAULT;
1265 }
1266 c->req.hdr.blk = pci_map_single(h->pci_dev, &(io->c),
1267 sizeof(ida_ioctl_t),
1268 PCI_DMA_BIDIRECTIONAL);
1269 c->req.sg[0].size = io->sg[0].size;
1270 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1271 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1272 c->req.hdr.sg_cnt = 1;
1273 break;
1274 case IDA_READ:
1275 case READ_FLASH_ROM:
1276 case SENSE_CONTROLLER_PERFORMANCE:
1277 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1278 if (!p)
1279 {
1280 error = -ENOMEM;
1281 cmd_free(h, c, 0);
1282 return(error);
1283 }
1284
1285 c->req.sg[0].size = io->sg[0].size;
1286 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1287 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1288 c->req.hdr.sg_cnt = 1;
1289 break;
1290 case IDA_WRITE:
1291 case IDA_WRITE_MEDIA:
1292 case DIAG_PASS_THRU:
1293 case COLLECT_BUFFER:
1294 case WRITE_FLASH_ROM:
1295 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1296 if (!p)
1297 {
1298 error = -ENOMEM;
1299 cmd_free(h, c, 0);
1300 return(error);
1301 }
1302 if (copy_from_user(p, io->sg[0].addr, io->sg[0].size)) {
1303 kfree(p);
1304 cmd_free(h, c, 0);
1305 return -EFAULT;
1306 }
1307 c->req.sg[0].size = io->sg[0].size;
1308 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1309 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1310 c->req.hdr.sg_cnt = 1;
1311 break;
1312 default:
1313 c->req.sg[0].size = sizeof(io->c);
1314 c->req.sg[0].addr = pci_map_single(h->pci_dev,&io->c,
1315 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1316 c->req.hdr.sg_cnt = 1;
1317 }
1318
1319 /* Put the request on the tail of the request queue */
1320 spin_lock_irqsave(IDA_LOCK(ctlr), flags);
1321 addQ(&h->reqQ, c);
1322 h->Qdepth++;
1323 start_io(h);
1324 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1325
1326 /* Wait for completion */
1327 while(c->type != CMD_IOCTL_DONE)
1328 schedule();
1329
1330 /* Unmap the DMA */
1331 pci_unmap_single(h->pci_dev, c->req.sg[0].addr, c->req.sg[0].size,
1332 PCI_DMA_BIDIRECTIONAL);
1333 /* Post submit processing */
1334 switch(io->cmd) {
1335 case PASSTHRU_A:
1336 pci_unmap_single(h->pci_dev, c->req.hdr.blk,
1337 sizeof(ida_ioctl_t),
1338 PCI_DMA_BIDIRECTIONAL);
1339 case IDA_READ:
1340 case DIAG_PASS_THRU:
1341 case SENSE_CONTROLLER_PERFORMANCE:
1342 case READ_FLASH_ROM:
1343 if (copy_to_user(io->sg[0].addr, p, io->sg[0].size)) {
1344 kfree(p);
1345 return -EFAULT;
1346 }
1347 /* fall through and free p */
1348 case IDA_WRITE:
1349 case IDA_WRITE_MEDIA:
1350 case COLLECT_BUFFER:
1351 case WRITE_FLASH_ROM:
1352 kfree(p);
1353 break;
1354 default:;
1355 /* Nothing to do */
1356 }
1357
1358 io->rcode = c->req.hdr.rcode;
1359 cmd_free(h, c, 0);
1360 return(0);
1361 }
1362
1363 /*
1364 * Commands are pre-allocated in a large block. Here we use a simple bitmap
1365 * scheme to suballocte them to the driver. Operations that are not time
1366 * critical (and can wait for kmalloc and possibly sleep) can pass in NULL
1367 * as the first argument to get a new command.
1368 */
1369 static cmdlist_t * cmd_alloc(ctlr_info_t *h, int get_from_pool)
1370 {
1371 cmdlist_t * c;
1372 int i;
1373 dma_addr_t cmd_dhandle;
1374
1375 if (!get_from_pool) {
1376 c = (cmdlist_t*)pci_alloc_consistent(h->pci_dev,
1377 sizeof(cmdlist_t), &cmd_dhandle);
1378 if(c==NULL)
1379 return NULL;
1380 } else {
1381 do {
1382 i = find_first_zero_bit(h->cmd_pool_bits, NR_CMDS);
1383 if (i == NR_CMDS)
1384 return NULL;
1385 } while(test_and_set_bit(i&(BITS_PER_LONG-1), h->cmd_pool_bits+(i/BITS_PER_LONG)) != 0);
1386 c = h->cmd_pool + i;
1387 cmd_dhandle = h->cmd_pool_dhandle + i*sizeof(cmdlist_t);
1388 h->nr_allocs++;
1389 }
1390
1391 memset(c, 0, sizeof(cmdlist_t));
1392 c->busaddr = cmd_dhandle;
1393 return c;
1394 }
1395
1396 static void cmd_free(ctlr_info_t *h, cmdlist_t *c, int got_from_pool)
1397 {
1398 int i;
1399
1400 if (!got_from_pool) {
1401 pci_free_consistent(h->pci_dev, sizeof(cmdlist_t), c,
1402 c->busaddr);
1403 } else {
1404 i = c - h->cmd_pool;
1405 clear_bit(i&(BITS_PER_LONG-1), h->cmd_pool_bits+(i/BITS_PER_LONG));
1406 h->nr_frees++;
1407 }
1408 }
1409
1410 /***********************************************************************
1411 name: sendcmd
1412 Send a command to an IDA using the memory mapped FIFO interface
1413 and wait for it to complete.
1414 This routine should only be called at init time.
1415 ***********************************************************************/
1416 static int sendcmd(
1417 __u8 cmd,
1418 int ctlr,
1419 void *buff,
1420 size_t size,
1421 unsigned int blk,
1422 unsigned int blkcnt,
1423 unsigned int log_unit )
1424 {
1425 cmdlist_t *c;
1426 int complete;
1427 unsigned long temp;
1428 unsigned long i;
1429 ctlr_info_t *info_p = hba[ctlr];
1430
1431 c = cmd_alloc(info_p, 1);
1432 if(!c)
1433 return IO_ERROR;
1434 c->ctlr = ctlr;
1435 c->hdr.unit = log_unit;
1436 c->hdr.prio = 0;
1437 c->hdr.size = sizeof(rblk_t) >> 2;
1438 c->size += sizeof(rblk_t);
1439
1440 /* The request information. */
1441 c->req.hdr.next = 0;
1442 c->req.hdr.rcode = 0;
1443 c->req.bp = 0;
1444 c->req.hdr.sg_cnt = 1;
1445 c->req.hdr.reserved = 0;
1446
1447 if (size == 0)
1448 c->req.sg[0].size = 512;
1449 else
1450 c->req.sg[0].size = size;
1451
1452 c->req.hdr.blk = blk;
1453 c->req.hdr.blk_cnt = blkcnt;
1454 c->req.hdr.cmd = (unsigned char) cmd;
1455 c->req.sg[0].addr = (__u32) pci_map_single(info_p->pci_dev,
1456 buff, c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1457 /*
1458 * Disable interrupt
1459 */
1460 info_p->access.set_intr_mask(info_p, 0);
1461 /* Make sure there is room in the command FIFO */
1462 /* Actually it should be completely empty at this time. */
1463 for (i = 200000; i > 0; i--) {
1464 temp = info_p->access.fifo_full(info_p);
1465 if (temp != 0) {
1466 break;
1467 }
1468 udelay(10);
1469 DBG(
1470 printk(KERN_WARNING "cpqarray ida%d: idaSendPciCmd FIFO full,"
1471 " waiting!\n", ctlr);
1472 );
1473 }
1474 /*
1475 * Send the cmd
1476 */
1477 info_p->access.submit_command(info_p, c);
1478 complete = pollcomplete(ctlr);
1479
1480 pci_unmap_single(info_p->pci_dev, (dma_addr_t) c->req.sg[0].addr,
1481 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1482 if (complete != 1) {
1483 if (complete != c->busaddr) {
1484 printk( KERN_WARNING
1485 "cpqarray ida%d: idaSendPciCmd "
1486 "Invalid command list address returned! (%08lx)\n",
1487 ctlr, (unsigned long)complete);
1488 cmd_free(info_p, c, 1);
1489 return (IO_ERROR);
1490 }
1491 } else {
1492 printk( KERN_WARNING
1493 "cpqarray ida%d: idaSendPciCmd Timeout out, "
1494 "No command list address returned!\n",
1495 ctlr);
1496 cmd_free(info_p, c, 1);
1497 return (IO_ERROR);
1498 }
1499
1500 if (c->req.hdr.rcode & 0x00FE) {
1501 if (!(c->req.hdr.rcode & BIG_PROBLEM)) {
1502 printk( KERN_WARNING
1503 "cpqarray ida%d: idaSendPciCmd, error: "
1504 "Controller failed at init time "
1505 "cmd: 0x%x, return code = 0x%x\n",
1506 ctlr, c->req.hdr.cmd, c->req.hdr.rcode);
1507
1508 cmd_free(info_p, c, 1);
1509 return (IO_ERROR);
1510 }
1511 }
1512 cmd_free(info_p, c, 1);
1513 return (IO_OK);
1514 }
1515
1516 /*
1517 * revalidate_allvol is for online array config utilities. After a
1518 * utility reconfigures the drives in the array, it can use this function
1519 * (through an ioctl) to make the driver zap any previous disk structs for
1520 * that controller and get new ones.
1521 *
1522 * Right now I'm using the getgeometry() function to do this, but this
1523 * function should probably be finer grained and allow you to revalidate one
1524 * particualar logical volume (instead of all of them on a particular
1525 * controller).
1526 */
1527 static int revalidate_allvol(ctlr_info_t *host)
1528 {
1529 int ctlr = host->ctlr;
1530 int i;
1531 unsigned long flags;
1532
1533 spin_lock_irqsave(IDA_LOCK(ctlr), flags);
1534 if (host->usage_count > 1) {
1535 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1536 printk(KERN_WARNING "cpqarray: Device busy for volume"
1537 " revalidation (usage=%d)\n", host->usage_count);
1538 return -EBUSY;
1539 }
1540 host->usage_count++;
1541 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1542
1543 /*
1544 * Set the partition and block size structures for all volumes
1545 * on this controller to zero. We will reread all of this data
1546 */
1547 set_capacity(ida_gendisk[ctlr][0], 0);
1548 for (i = 1; i < NWD; i++) {
1549 struct gendisk *disk = ida_gendisk[ctlr][i];
1550 if (disk->flags & GENHD_FL_UP)
1551 del_gendisk(disk);
1552 }
1553 memset(host->drv, 0, sizeof(drv_info_t)*NWD);
1554
1555 /*
1556 * Tell the array controller not to give us any interrupts while
1557 * we check the new geometry. Then turn interrupts back on when
1558 * we're done.
1559 */
1560 host->access.set_intr_mask(host, 0);
1561 getgeometry(ctlr);
1562 host->access.set_intr_mask(host, FIFO_NOT_EMPTY);
1563
1564 for(i=0; i<NWD; i++) {
1565 struct gendisk *disk = ida_gendisk[ctlr][i];
1566 drv_info_t *drv = &host->drv[i];
1567 if (i && !drv->nr_blks)
1568 continue;
1569 blk_queue_hardsect_size(host->queue, drv->blk_size);
1570 set_capacity(disk, drv->nr_blks);
1571 disk->queue = host->queue;
1572 disk->private_data = drv;
1573 if (i)
1574 add_disk(disk);
1575 }
1576
1577 host->usage_count--;
1578 return 0;
1579 }
1580
1581 static int ida_revalidate(struct gendisk *disk)
1582 {
1583 drv_info_t *drv = disk->private_data;
1584 set_capacity(disk, drv->nr_blks);
1585 return 0;
1586 }
1587
1588 /********************************************************************
1589 name: pollcomplete
1590 Wait polling for a command to complete.
1591 The memory mapped FIFO is polled for the completion.
1592 Used only at init time, interrupts disabled.
1593 ********************************************************************/
1594 static int pollcomplete(int ctlr)
1595 {
1596 int done;
1597 int i;
1598
1599 /* Wait (up to 2 seconds) for a command to complete */
1600
1601 for (i = 200000; i > 0; i--) {
1602 done = hba[ctlr]->access.command_completed(hba[ctlr]);
1603 if (done == 0) {
1604 udelay(10); /* a short fixed delay */
1605 } else
1606 return (done);
1607 }
1608 /* Invalid address to tell caller we ran out of time */
1609 return 1;
1610 }
1611 /*****************************************************************
1612 start_fwbk
1613 Starts controller firmwares background processing.
1614 Currently only the Integrated Raid controller needs this done.
1615 If the PCI mem address registers are written to after this,
1616 data corruption may occur
1617 *****************************************************************/
1618 static void start_fwbk(int ctlr)
1619 {
1620 id_ctlr_t *id_ctlr_buf;
1621 int ret_code;
1622
1623 if( (hba[ctlr]->board_id != 0x40400E11)
1624 && (hba[ctlr]->board_id != 0x40480E11) )
1625
1626 /* Not a Integrated Raid, so there is nothing for us to do */
1627 return;
1628 printk(KERN_DEBUG "cpqarray: Starting firmware's background"
1629 " processing\n");
1630 /* Command does not return anything, but idasend command needs a
1631 buffer */
1632 id_ctlr_buf = (id_ctlr_t *)kmalloc(sizeof(id_ctlr_t), GFP_KERNEL);
1633 if(id_ctlr_buf==NULL)
1634 {
1635 printk(KERN_WARNING "cpqarray: Out of memory. "
1636 "Unable to start background processing.\n");
1637 return;
1638 }
1639 ret_code = sendcmd(RESUME_BACKGROUND_ACTIVITY, ctlr,
1640 id_ctlr_buf, 0, 0, 0, 0);
1641 if(ret_code != IO_OK)
1642 printk(KERN_WARNING "cpqarray: Unable to start"
1643 " background processing\n");
1644
1645 kfree(id_ctlr_buf);
1646 }
1647 /*****************************************************************
1648 getgeometry
1649 Get ida logical volume geometry from the controller
1650 This is a large bit of code which once existed in two flavors,
1651 It is used only at init time.
1652 *****************************************************************/
1653 static void getgeometry(int ctlr)
1654 {
1655 id_log_drv_t *id_ldrive;
1656 id_ctlr_t *id_ctlr_buf;
1657 sense_log_drv_stat_t *id_lstatus_buf;
1658 config_t *sense_config_buf;
1659 unsigned int log_unit, log_index;
1660 int ret_code, size;
1661 drv_info_t *drv;
1662 ctlr_info_t *info_p = hba[ctlr];
1663 int i;
1664
1665 info_p->log_drv_map = 0;
1666
1667 id_ldrive = (id_log_drv_t *)kmalloc(sizeof(id_log_drv_t), GFP_KERNEL);
1668 if(id_ldrive == NULL)
1669 {
1670 printk( KERN_ERR "cpqarray: out of memory.\n");
1671 return;
1672 }
1673
1674 id_ctlr_buf = (id_ctlr_t *)kmalloc(sizeof(id_ctlr_t), GFP_KERNEL);
1675 if(id_ctlr_buf == NULL)
1676 {
1677 kfree(id_ldrive);
1678 printk( KERN_ERR "cpqarray: out of memory.\n");
1679 return;
1680 }
1681
1682 id_lstatus_buf = (sense_log_drv_stat_t *)kmalloc(sizeof(sense_log_drv_stat_t), GFP_KERNEL);
1683 if(id_lstatus_buf == NULL)
1684 {
1685 kfree(id_ctlr_buf);
1686 kfree(id_ldrive);
1687 printk( KERN_ERR "cpqarray: out of memory.\n");
1688 return;
1689 }
1690
1691 sense_config_buf = (config_t *)kmalloc(sizeof(config_t), GFP_KERNEL);
1692 if(sense_config_buf == NULL)
1693 {
1694 kfree(id_lstatus_buf);
1695 kfree(id_ctlr_buf);
1696 kfree(id_ldrive);
1697 printk( KERN_ERR "cpqarray: out of memory.\n");
1698 return;
1699 }
1700
1701 memset(id_ldrive, 0, sizeof(id_log_drv_t));
1702 memset(id_ctlr_buf, 0, sizeof(id_ctlr_t));
1703 memset(id_lstatus_buf, 0, sizeof(sense_log_drv_stat_t));
1704 memset(sense_config_buf, 0, sizeof(config_t));
1705
1706 info_p->phys_drives = 0;
1707 info_p->log_drv_map = 0;
1708 info_p->drv_assign_map = 0;
1709 info_p->drv_spare_map = 0;
1710 info_p->mp_failed_drv_map = 0; /* only initialized here */
1711 /* Get controllers info for this logical drive */
1712 ret_code = sendcmd(ID_CTLR, ctlr, id_ctlr_buf, 0, 0, 0, 0);
1713 if (ret_code == IO_ERROR) {
1714 /*
1715 * If can't get controller info, set the logical drive map to 0,
1716 * so the idastubopen will fail on all logical drives
1717 * on the controller.
1718 */
1719 /* Free all the buffers and return */
1720 printk(KERN_ERR "cpqarray: error sending ID controller\n");
1721 kfree(sense_config_buf);
1722 kfree(id_lstatus_buf);
1723 kfree(id_ctlr_buf);
1724 kfree(id_ldrive);
1725 return;
1726 }
1727
1728 info_p->log_drives = id_ctlr_buf->nr_drvs;
1729 for(i=0;i<4;i++)
1730 info_p->firm_rev[i] = id_ctlr_buf->firm_rev[i];
1731 info_p->ctlr_sig = id_ctlr_buf->cfg_sig;
1732
1733 printk(" (%s)\n", info_p->product_name);
1734 /*
1735 * Initialize logical drive map to zero
1736 */
1737 log_index = 0;
1738 /*
1739 * Get drive geometry for all logical drives
1740 */
1741 if (id_ctlr_buf->nr_drvs > 16)
1742 printk(KERN_WARNING "cpqarray ida%d: This driver supports "
1743 "16 logical drives per controller.\n. "
1744 " Additional drives will not be "
1745 "detected\n", ctlr);
1746
1747 for (log_unit = 0;
1748 (log_index < id_ctlr_buf->nr_drvs)
1749 && (log_unit < NWD);
1750 log_unit++) {
1751 struct gendisk *disk = ida_gendisk[ctlr][log_unit];
1752
1753 size = sizeof(sense_log_drv_stat_t);
1754
1755 /*
1756 Send "Identify logical drive status" cmd
1757 */
1758 ret_code = sendcmd(SENSE_LOG_DRV_STAT,
1759 ctlr, id_lstatus_buf, size, 0, 0, log_unit);
1760 if (ret_code == IO_ERROR) {
1761 /*
1762 If can't get logical drive status, set
1763 the logical drive map to 0, so the
1764 idastubopen will fail for all logical drives
1765 on the controller.
1766 */
1767 info_p->log_drv_map = 0;
1768 printk( KERN_WARNING
1769 "cpqarray ida%d: idaGetGeometry - Controller"
1770 " failed to report status of logical drive %d\n"
1771 "Access to this controller has been disabled\n",
1772 ctlr, log_unit);
1773 /* Free all the buffers and return */
1774 kfree(sense_config_buf);
1775 kfree(id_lstatus_buf);
1776 kfree(id_ctlr_buf);
1777 kfree(id_ldrive);
1778 return;
1779 }
1780 /*
1781 Make sure the logical drive is configured
1782 */
1783 if (id_lstatus_buf->status != LOG_NOT_CONF) {
1784 ret_code = sendcmd(ID_LOG_DRV, ctlr, id_ldrive,
1785 sizeof(id_log_drv_t), 0, 0, log_unit);
1786 /*
1787 If error, the bit for this
1788 logical drive won't be set and
1789 idastubopen will return error.
1790 */
1791 if (ret_code != IO_ERROR) {
1792 drv = &info_p->drv[log_unit];
1793 drv->blk_size = id_ldrive->blk_size;
1794 drv->nr_blks = id_ldrive->nr_blks;
1795 drv->cylinders = id_ldrive->drv.cyl;
1796 drv->heads = id_ldrive->drv.heads;
1797 drv->sectors = id_ldrive->drv.sect_per_track;
1798 info_p->log_drv_map |= (1 << log_unit);
1799
1800 printk(KERN_INFO "cpqarray ida/c%dd%d: blksz=%d nr_blks=%d\n",
1801 ctlr, log_unit, drv->blk_size, drv->nr_blks);
1802 ret_code = sendcmd(SENSE_CONFIG,
1803 ctlr, sense_config_buf,
1804 sizeof(config_t), 0, 0, log_unit);
1805 if (ret_code == IO_ERROR) {
1806 info_p->log_drv_map = 0;
1807 /* Free all the buffers and return */
1808 printk(KERN_ERR "cpqarray: error sending sense config\n");
1809 kfree(sense_config_buf);
1810 kfree(id_lstatus_buf);
1811 kfree(id_ctlr_buf);
1812 kfree(id_ldrive);
1813 return;
1814
1815 }
1816
1817 sprintf(disk->devfs_name, "ida/c%dd%d", ctlr, log_unit);
1818
1819 info_p->phys_drives =
1820 sense_config_buf->ctlr_phys_drv;
1821 info_p->drv_assign_map
1822 |= sense_config_buf->drv_asgn_map;
1823 info_p->drv_assign_map
1824 |= sense_config_buf->spare_asgn_map;
1825 info_p->drv_spare_map
1826 |= sense_config_buf->spare_asgn_map;
1827 } /* end of if no error on id_ldrive */
1828 log_index = log_index + 1;
1829 } /* end of if logical drive configured */
1830 } /* end of for log_unit */
1831 kfree(sense_config_buf);
1832 kfree(id_ldrive);
1833 kfree(id_lstatus_buf);
1834 kfree(id_ctlr_buf);
1835 return;
1836
1837 }
1838
1839 static void __exit cpqarray_exit(void)
1840 {
1841 int i;
1842
1843 pci_unregister_driver(&cpqarray_pci_driver);
1844
1845 /* Double check that all controller entries have been removed */
1846 for(i=0; i<MAX_CTLR; i++) {
1847 if (hba[i] != NULL) {
1848 printk(KERN_WARNING "cpqarray: Removing EISA "
1849 "controller %d\n", i);
1850 cpqarray_remove_one_eisa(i);
1851 }
1852 }
1853
1854 devfs_remove("ida");
1855 remove_proc_entry("cpqarray", proc_root_driver);
1856 }
1857
1858 module_init(cpqarray_init)
1859 module_exit(cpqarray_exit)
1860
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