1 #ifndef CCISS_H
2 #define CCISS_H
3
4 #include <linux/genhd.h>
5
6 #include "cciss_cmd.h"
7
8
9 #define NWD_SHIFT 4
10 #define MAX_PART (1 << NWD_SHIFT)
11
12 #define IO_OK 0
13 #define IO_ERROR 1
14 #define IO_NEEDS_RETRY 3
15
16 #define VENDOR_LEN 8
17 #define MODEL_LEN 16
18 #define REV_LEN 4
19
20 struct ctlr_info;
21 typedef struct ctlr_info ctlr_info_t;
22
23 struct access_method {
24 void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
25 void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
26 unsigned long (*fifo_full)(ctlr_info_t *h);
27 unsigned long (*intr_pending)(ctlr_info_t *h);
28 unsigned long (*command_completed)(ctlr_info_t *h);
29 };
30 typedef struct _drive_info_struct
31 {
32 __u32 LunID;
33 int usage_count;
34 struct request_queue *queue;
35 sector_t nr_blocks;
36 int block_size;
37 int heads;
38 int sectors;
39 int cylinders;
40 int raid_level; /* set to -1 to indicate that
41 * the drive is not in use/configured
42 */
43 int busy_configuring; /* This is set when a drive is being removed
44 * to prevent it from being opened or it's
45 * queue from being started.
46 */
47 struct device dev;
48 __u8 serial_no[16]; /* from inquiry page 0x83,
49 * not necc. null terminated.
50 */
51 char vendor[VENDOR_LEN + 1]; /* SCSI vendor string */
52 char model[MODEL_LEN + 1]; /* SCSI model string */
53 char rev[REV_LEN + 1]; /* SCSI revision string */
54 } drive_info_struct;
55
56 struct ctlr_info
57 {
58 int ctlr;
59 char devname[8];
60 char *product_name;
61 char firm_ver[4]; // Firmware version
62 struct pci_dev *pdev;
63 __u32 board_id;
64 void __iomem *vaddr;
65 unsigned long paddr;
66 int nr_cmds; /* Number of commands allowed on this controller */
67 CfgTable_struct __iomem *cfgtable;
68 int interrupts_enabled;
69 int major;
70 int max_commands;
71 int commands_outstanding;
72 int max_outstanding; /* Debug */
73 int num_luns;
74 int highest_lun;
75 int usage_count; /* number of opens all all minor devices */
76 # define DOORBELL_INT 0
77 # define PERF_MODE_INT 1
78 # define SIMPLE_MODE_INT 2
79 # define MEMQ_MODE_INT 3
80 unsigned int intr[4];
81 unsigned int msix_vector;
82 unsigned int msi_vector;
83 int cciss_max_sectors;
84 BYTE cciss_read;
85 BYTE cciss_write;
86 BYTE cciss_read_capacity;
87
88 // information about each logical volume
89 drive_info_struct drv[CISS_MAX_LUN];
90
91 struct access_method access;
92
93 /* queue and queue Info */
94 struct hlist_head reqQ;
95 struct hlist_head cmpQ;
96 unsigned int Qdepth;
97 unsigned int maxQsinceinit;
98 unsigned int maxSG;
99 spinlock_t lock;
100
101 //* pointers to command and error info pool */
102 CommandList_struct *cmd_pool;
103 dma_addr_t cmd_pool_dhandle;
104 ErrorInfo_struct *errinfo_pool;
105 dma_addr_t errinfo_pool_dhandle;
106 unsigned long *cmd_pool_bits;
107 int nr_allocs;
108 int nr_frees;
109 int busy_configuring;
110 int busy_initializing;
111
112 /* This element holds the zero based queue number of the last
113 * queue to be started. It is used for fairness.
114 */
115 int next_to_run;
116
117 // Disk structures we need to pass back
118 struct gendisk *gendisk[CISS_MAX_LUN];
119 #ifdef CONFIG_CISS_SCSI_TAPE
120 void *scsi_ctlr; /* ptr to structure containing scsi related stuff */
121 /* list of block side commands the scsi error handling sucked up */
122 /* and saved for later processing */
123 #endif
124 unsigned char alive;
125 struct completion *rescan_wait;
126 struct task_struct *cciss_scan_thread;
127 struct device dev;
128 };
129
130 /* Defining the diffent access_menthods */
131 /*
132 * Memory mapped FIFO interface (SMART 53xx cards)
133 */
134 #define SA5_DOORBELL 0x20
135 #define SA5_REQUEST_PORT_OFFSET 0x40
136 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
137 #define SA5_REPLY_PORT_OFFSET 0x44
138 #define SA5_INTR_STATUS 0x30
139 #define SA5_SCRATCHPAD_OFFSET 0xB0
140
141 #define SA5_CTCFG_OFFSET 0xB4
142 #define SA5_CTMEM_OFFSET 0xB8
143
144 #define SA5_INTR_OFF 0x08
145 #define SA5B_INTR_OFF 0x04
146 #define SA5_INTR_PENDING 0x08
147 #define SA5B_INTR_PENDING 0x04
148 #define FIFO_EMPTY 0xffffffff
149 #define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
150
151 #define CISS_ERROR_BIT 0x02
152
153 #define CCISS_INTR_ON 1
154 #define CCISS_INTR_OFF 0
155 /*
156 Send the command to the hardware
157 */
158 static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)
159 {
160 #ifdef CCISS_DEBUG
161 printk("Sending %x - down to controller\n", c->busaddr );
162 #endif /* CCISS_DEBUG */
163 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
164 h->commands_outstanding++;
165 if ( h->commands_outstanding > h->max_outstanding)
166 h->max_outstanding = h->commands_outstanding;
167 }
168
169 /*
170 * This card is the opposite of the other cards.
171 * 0 turns interrupts on...
172 * 0x08 turns them off...
173 */
174 static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
175 {
176 if (val)
177 { /* Turn interrupts on */
178 h->interrupts_enabled = 1;
179 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
180 } else /* Turn them off */
181 {
182 h->interrupts_enabled = 0;
183 writel( SA5_INTR_OFF,
184 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
185 }
186 }
187 /*
188 * This card is the opposite of the other cards.
189 * 0 turns interrupts on...
190 * 0x04 turns them off...
191 */
192 static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
193 {
194 if (val)
195 { /* Turn interrupts on */
196 h->interrupts_enabled = 1;
197 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
198 } else /* Turn them off */
199 {
200 h->interrupts_enabled = 0;
201 writel( SA5B_INTR_OFF,
202 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
203 }
204 }
205 /*
206 * Returns true if fifo is full.
207 *
208 */
209 static unsigned long SA5_fifo_full(ctlr_info_t *h)
210 {
211 if( h->commands_outstanding >= h->max_commands)
212 return(1);
213 else
214 return(0);
215
216 }
217 /*
218 * returns value read from hardware.
219 * returns FIFO_EMPTY if there is nothing to read
220 */
221 static unsigned long SA5_completed(ctlr_info_t *h)
222 {
223 unsigned long register_value
224 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
225 if(register_value != FIFO_EMPTY)
226 {
227 h->commands_outstanding--;
228 #ifdef CCISS_DEBUG
229 printk("cciss: Read %lx back from board\n", register_value);
230 #endif /* CCISS_DEBUG */
231 }
232 #ifdef CCISS_DEBUG
233 else
234 {
235 printk("cciss: FIFO Empty read\n");
236 }
237 #endif
238 return ( register_value);
239
240 }
241 /*
242 * Returns true if an interrupt is pending..
243 */
244 static unsigned long SA5_intr_pending(ctlr_info_t *h)
245 {
246 unsigned long register_value =
247 readl(h->vaddr + SA5_INTR_STATUS);
248 #ifdef CCISS_DEBUG
249 printk("cciss: intr_pending %lx\n", register_value);
250 #endif /* CCISS_DEBUG */
251 if( register_value & SA5_INTR_PENDING)
252 return 1;
253 return 0 ;
254 }
255
256 /*
257 * Returns true if an interrupt is pending..
258 */
259 static unsigned long SA5B_intr_pending(ctlr_info_t *h)
260 {
261 unsigned long register_value =
262 readl(h->vaddr + SA5_INTR_STATUS);
263 #ifdef CCISS_DEBUG
264 printk("cciss: intr_pending %lx\n", register_value);
265 #endif /* CCISS_DEBUG */
266 if( register_value & SA5B_INTR_PENDING)
267 return 1;
268 return 0 ;
269 }
270
271
272 static struct access_method SA5_access = {
273 SA5_submit_command,
274 SA5_intr_mask,
275 SA5_fifo_full,
276 SA5_intr_pending,
277 SA5_completed,
278 };
279
280 static struct access_method SA5B_access = {
281 SA5_submit_command,
282 SA5B_intr_mask,
283 SA5_fifo_full,
284 SA5B_intr_pending,
285 SA5_completed,
286 };
287
288 struct board_type {
289 __u32 board_id;
290 char *product_name;
291 struct access_method *access;
292 int nr_cmds; /* Max cmds this kind of ctlr can handle. */
293 };
294
295 #define CCISS_LOCK(i) (&hba[i]->lock)
296
297 #endif /* CCISS_H */
298
299
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