1 /*
2 * pdc_adma.c - Pacific Digital Corporation ADMA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Mark Lord
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 *
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
29 *
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
45
46 #define DRV_NAME "pdc_adma"
47 #define DRV_VERSION "1.0"
48
49 /* macro to calculate base address for ATA regs */
50 #define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
51
52 /* macro to calculate base address for ADMA regs */
53 #define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
54
55 /* macro to obtain addresses from ata_port */
56 #define ADMA_PORT_REGS(ap) \
57 ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
58
59 enum {
60 ADMA_MMIO_BAR = 4,
61
62 ADMA_PORTS = 2,
63 ADMA_CPB_BYTES = 40,
64 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
65 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
66
67 ADMA_DMA_BOUNDARY = 0xffffffff,
68
69 /* global register offsets */
70 ADMA_MODE_LOCK = 0x00c7,
71
72 /* per-channel register offsets */
73 ADMA_CONTROL = 0x0000, /* ADMA control */
74 ADMA_STATUS = 0x0002, /* ADMA status */
75 ADMA_CPB_COUNT = 0x0004, /* CPB count */
76 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
77 ADMA_CPB_NEXT = 0x000c, /* next CPB address */
78 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
79 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
80 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
81
82 /* ADMA_CONTROL register bits */
83 aNIEN = (1 << 8), /* irq mask: 1==masked */
84 aGO = (1 << 7), /* packet trigger ("Go!") */
85 aRSTADM = (1 << 5), /* ADMA logic reset */
86 aPIOMD4 = 0x0003, /* PIO mode 4 */
87
88 /* ADMA_STATUS register bits */
89 aPSD = (1 << 6),
90 aUIRQ = (1 << 4),
91 aPERR = (1 << 0),
92
93 /* CPB bits */
94 cDONE = (1 << 0),
95 cATERR = (1 << 3),
96
97 cVLD = (1 << 0),
98 cDAT = (1 << 2),
99 cIEN = (1 << 3),
100
101 /* PRD bits */
102 pORD = (1 << 4),
103 pDIRO = (1 << 5),
104 pEND = (1 << 7),
105
106 /* ATA register flags */
107 rIGN = (1 << 5),
108 rEND = (1 << 7),
109
110 /* ATA register addresses */
111 ADMA_REGS_CONTROL = 0x0e,
112 ADMA_REGS_SECTOR_COUNT = 0x12,
113 ADMA_REGS_LBA_LOW = 0x13,
114 ADMA_REGS_LBA_MID = 0x14,
115 ADMA_REGS_LBA_HIGH = 0x15,
116 ADMA_REGS_DEVICE = 0x16,
117 ADMA_REGS_COMMAND = 0x17,
118
119 /* PCI device IDs */
120 board_1841_idx = 0, /* ADMA 2-port controller */
121 };
122
123 typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
124
125 struct adma_port_priv {
126 u8 *pkt;
127 dma_addr_t pkt_dma;
128 adma_state_t state;
129 };
130
131 static int adma_ata_init_one(struct pci_dev *pdev,
132 const struct pci_device_id *ent);
133 static int adma_port_start(struct ata_port *ap);
134 static void adma_host_stop(struct ata_host *host);
135 static void adma_port_stop(struct ata_port *ap);
136 static void adma_qc_prep(struct ata_queued_cmd *qc);
137 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
138 static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
139 static void adma_bmdma_stop(struct ata_queued_cmd *qc);
140 static u8 adma_bmdma_status(struct ata_port *ap);
141 static void adma_irq_clear(struct ata_port *ap);
142 static void adma_freeze(struct ata_port *ap);
143 static void adma_thaw(struct ata_port *ap);
144 static void adma_error_handler(struct ata_port *ap);
145
146 static struct scsi_host_template adma_ata_sht = {
147 .module = THIS_MODULE,
148 .name = DRV_NAME,
149 .ioctl = ata_scsi_ioctl,
150 .queuecommand = ata_scsi_queuecmd,
151 .slave_configure = ata_scsi_slave_config,
152 .slave_destroy = ata_scsi_slave_destroy,
153 .bios_param = ata_std_bios_param,
154 .proc_name = DRV_NAME,
155 .can_queue = ATA_DEF_QUEUE,
156 .this_id = ATA_SHT_THIS_ID,
157 .sg_tablesize = LIBATA_MAX_PRD,
158 .dma_boundary = ADMA_DMA_BOUNDARY,
159 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
160 .use_clustering = ENABLE_CLUSTERING,
161 .emulated = ATA_SHT_EMULATED,
162 };
163
164 static const struct ata_port_operations adma_ata_ops = {
165 .tf_load = ata_tf_load,
166 .tf_read = ata_tf_read,
167 .exec_command = ata_exec_command,
168 .check_status = ata_check_status,
169 .dev_select = ata_std_dev_select,
170 .check_atapi_dma = adma_check_atapi_dma,
171 .data_xfer = ata_data_xfer,
172 .qc_prep = adma_qc_prep,
173 .qc_issue = adma_qc_issue,
174 .freeze = adma_freeze,
175 .thaw = adma_thaw,
176 .error_handler = adma_error_handler,
177 .irq_clear = adma_irq_clear,
178 .irq_on = ata_irq_on,
179 .port_start = adma_port_start,
180 .port_stop = adma_port_stop,
181 .host_stop = adma_host_stop,
182 .bmdma_stop = adma_bmdma_stop,
183 .bmdma_status = adma_bmdma_status,
184 };
185
186 static struct ata_port_info adma_port_info[] = {
187 /* board_1841_idx */
188 {
189 .flags = ATA_FLAG_SLAVE_POSS |
190 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO |
191 ATA_FLAG_PIO_POLLING,
192 .pio_mask = 0x10, /* pio4 */
193 .udma_mask = ATA_UDMA4,
194 .port_ops = &adma_ata_ops,
195 },
196 };
197
198 static const struct pci_device_id adma_ata_pci_tbl[] = {
199 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
200
201 { } /* terminate list */
202 };
203
204 static struct pci_driver adma_ata_pci_driver = {
205 .name = DRV_NAME,
206 .id_table = adma_ata_pci_tbl,
207 .probe = adma_ata_init_one,
208 .remove = ata_pci_remove_one,
209 };
210
211 static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
212 {
213 return 1; /* ATAPI DMA not yet supported */
214 }
215
216 static void adma_bmdma_stop(struct ata_queued_cmd *qc)
217 {
218 /* nothing */
219 }
220
221 static u8 adma_bmdma_status(struct ata_port *ap)
222 {
223 return 0;
224 }
225
226 static void adma_irq_clear(struct ata_port *ap)
227 {
228 /* nothing */
229 }
230
231 static void adma_reset_engine(struct ata_port *ap)
232 {
233 void __iomem *chan = ADMA_PORT_REGS(ap);
234
235 /* reset ADMA to idle state */
236 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
237 udelay(2);
238 writew(aPIOMD4, chan + ADMA_CONTROL);
239 udelay(2);
240 }
241
242 static void adma_reinit_engine(struct ata_port *ap)
243 {
244 struct adma_port_priv *pp = ap->private_data;
245 void __iomem *chan = ADMA_PORT_REGS(ap);
246
247 /* mask/clear ATA interrupts */
248 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
249 ata_check_status(ap);
250
251 /* reset the ADMA engine */
252 adma_reset_engine(ap);
253
254 /* set in-FIFO threshold to 0x100 */
255 writew(0x100, chan + ADMA_FIFO_IN);
256
257 /* set CPB pointer */
258 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
259
260 /* set out-FIFO threshold to 0x100 */
261 writew(0x100, chan + ADMA_FIFO_OUT);
262
263 /* set CPB count */
264 writew(1, chan + ADMA_CPB_COUNT);
265
266 /* read/discard ADMA status */
267 readb(chan + ADMA_STATUS);
268 }
269
270 static inline void adma_enter_reg_mode(struct ata_port *ap)
271 {
272 void __iomem *chan = ADMA_PORT_REGS(ap);
273
274 writew(aPIOMD4, chan + ADMA_CONTROL);
275 readb(chan + ADMA_STATUS); /* flush */
276 }
277
278 static void adma_freeze(struct ata_port *ap)
279 {
280 void __iomem *chan = ADMA_PORT_REGS(ap);
281
282 /* mask/clear ATA interrupts */
283 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
284 ata_check_status(ap);
285
286 /* reset ADMA to idle state */
287 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
288 udelay(2);
289 writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
290 udelay(2);
291 }
292
293 static void adma_thaw(struct ata_port *ap)
294 {
295 adma_reinit_engine(ap);
296 }
297
298 static int adma_prereset(struct ata_link *link, unsigned long deadline)
299 {
300 struct ata_port *ap = link->ap;
301 struct adma_port_priv *pp = ap->private_data;
302
303 if (pp->state != adma_state_idle) /* healthy paranoia */
304 pp->state = adma_state_mmio;
305 adma_reinit_engine(ap);
306
307 return ata_std_prereset(link, deadline);
308 }
309
310 static void adma_error_handler(struct ata_port *ap)
311 {
312 ata_do_eh(ap, adma_prereset, ata_std_softreset, NULL,
313 ata_std_postreset);
314 }
315
316 static int adma_fill_sg(struct ata_queued_cmd *qc)
317 {
318 struct scatterlist *sg;
319 struct ata_port *ap = qc->ap;
320 struct adma_port_priv *pp = ap->private_data;
321 u8 *buf = pp->pkt, *last_buf = NULL;
322 int i = (2 + buf[3]) * 8;
323 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
324 unsigned int si;
325
326 for_each_sg(qc->sg, sg, qc->n_elem, si) {
327 u32 addr;
328 u32 len;
329
330 addr = (u32)sg_dma_address(sg);
331 *(__le32 *)(buf + i) = cpu_to_le32(addr);
332 i += 4;
333
334 len = sg_dma_len(sg) >> 3;
335 *(__le32 *)(buf + i) = cpu_to_le32(len);
336 i += 4;
337
338 last_buf = &buf[i];
339 buf[i++] = pFLAGS;
340 buf[i++] = qc->dev->dma_mode & 0xf;
341 buf[i++] = 0; /* pPKLW */
342 buf[i++] = 0; /* reserved */
343
344 *(__le32 *)(buf + i) =
345 (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
346 i += 4;
347
348 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
349 (unsigned long)addr, len);
350 }
351
352 if (likely(last_buf))
353 *last_buf |= pEND;
354
355 return i;
356 }
357
358 static void adma_qc_prep(struct ata_queued_cmd *qc)
359 {
360 struct adma_port_priv *pp = qc->ap->private_data;
361 u8 *buf = pp->pkt;
362 u32 pkt_dma = (u32)pp->pkt_dma;
363 int i = 0;
364
365 VPRINTK("ENTER\n");
366
367 adma_enter_reg_mode(qc->ap);
368 if (qc->tf.protocol != ATA_PROT_DMA) {
369 ata_qc_prep(qc);
370 return;
371 }
372
373 buf[i++] = 0; /* Response flags */
374 buf[i++] = 0; /* reserved */
375 buf[i++] = cVLD | cDAT | cIEN;
376 i++; /* cLEN, gets filled in below */
377
378 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
379 i += 4; /* cNCPB */
380 i += 4; /* cPRD, gets filled in below */
381
382 buf[i++] = 0; /* reserved */
383 buf[i++] = 0; /* reserved */
384 buf[i++] = 0; /* reserved */
385 buf[i++] = 0; /* reserved */
386
387 /* ATA registers; must be a multiple of 4 */
388 buf[i++] = qc->tf.device;
389 buf[i++] = ADMA_REGS_DEVICE;
390 if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
391 buf[i++] = qc->tf.hob_nsect;
392 buf[i++] = ADMA_REGS_SECTOR_COUNT;
393 buf[i++] = qc->tf.hob_lbal;
394 buf[i++] = ADMA_REGS_LBA_LOW;
395 buf[i++] = qc->tf.hob_lbam;
396 buf[i++] = ADMA_REGS_LBA_MID;
397 buf[i++] = qc->tf.hob_lbah;
398 buf[i++] = ADMA_REGS_LBA_HIGH;
399 }
400 buf[i++] = qc->tf.nsect;
401 buf[i++] = ADMA_REGS_SECTOR_COUNT;
402 buf[i++] = qc->tf.lbal;
403 buf[i++] = ADMA_REGS_LBA_LOW;
404 buf[i++] = qc->tf.lbam;
405 buf[i++] = ADMA_REGS_LBA_MID;
406 buf[i++] = qc->tf.lbah;
407 buf[i++] = ADMA_REGS_LBA_HIGH;
408 buf[i++] = 0;
409 buf[i++] = ADMA_REGS_CONTROL;
410 buf[i++] = rIGN;
411 buf[i++] = 0;
412 buf[i++] = qc->tf.command;
413 buf[i++] = ADMA_REGS_COMMAND | rEND;
414
415 buf[3] = (i >> 3) - 2; /* cLEN */
416 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
417
418 i = adma_fill_sg(qc);
419 wmb(); /* flush PRDs and pkt to memory */
420 #if 0
421 /* dump out CPB + PRDs for debug */
422 {
423 int j, len = 0;
424 static char obuf[2048];
425 for (j = 0; j < i; ++j) {
426 len += sprintf(obuf+len, "%02x ", buf[j]);
427 if ((j & 7) == 7) {
428 printk("%s\n", obuf);
429 len = 0;
430 }
431 }
432 if (len)
433 printk("%s\n", obuf);
434 }
435 #endif
436 }
437
438 static inline void adma_packet_start(struct ata_queued_cmd *qc)
439 {
440 struct ata_port *ap = qc->ap;
441 void __iomem *chan = ADMA_PORT_REGS(ap);
442
443 VPRINTK("ENTER, ap %p\n", ap);
444
445 /* fire up the ADMA engine */
446 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
447 }
448
449 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
450 {
451 struct adma_port_priv *pp = qc->ap->private_data;
452
453 switch (qc->tf.protocol) {
454 case ATA_PROT_DMA:
455 pp->state = adma_state_pkt;
456 adma_packet_start(qc);
457 return 0;
458
459 case ATAPI_PROT_DMA:
460 BUG();
461 break;
462
463 default:
464 break;
465 }
466
467 pp->state = adma_state_mmio;
468 return ata_qc_issue_prot(qc);
469 }
470
471 static inline unsigned int adma_intr_pkt(struct ata_host *host)
472 {
473 unsigned int handled = 0, port_no;
474
475 for (port_no = 0; port_no < host->n_ports; ++port_no) {
476 struct ata_port *ap = host->ports[port_no];
477 struct adma_port_priv *pp;
478 struct ata_queued_cmd *qc;
479 void __iomem *chan = ADMA_PORT_REGS(ap);
480 u8 status = readb(chan + ADMA_STATUS);
481
482 if (status == 0)
483 continue;
484 handled = 1;
485 adma_enter_reg_mode(ap);
486 if (ap->flags & ATA_FLAG_DISABLED)
487 continue;
488 pp = ap->private_data;
489 if (!pp || pp->state != adma_state_pkt)
490 continue;
491 qc = ata_qc_from_tag(ap, ap->link.active_tag);
492 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
493 if (status & aPERR)
494 qc->err_mask |= AC_ERR_HOST_BUS;
495 else if ((status & (aPSD | aUIRQ)))
496 qc->err_mask |= AC_ERR_OTHER;
497
498 if (pp->pkt[0] & cATERR)
499 qc->err_mask |= AC_ERR_DEV;
500 else if (pp->pkt[0] != cDONE)
501 qc->err_mask |= AC_ERR_OTHER;
502
503 if (!qc->err_mask)
504 ata_qc_complete(qc);
505 else {
506 struct ata_eh_info *ehi = &ap->link.eh_info;
507 ata_ehi_clear_desc(ehi);
508 ata_ehi_push_desc(ehi,
509 "ADMA-status 0x%02X", status);
510 ata_ehi_push_desc(ehi,
511 "pkt[0] 0x%02X", pp->pkt[0]);
512
513 if (qc->err_mask == AC_ERR_DEV)
514 ata_port_abort(ap);
515 else
516 ata_port_freeze(ap);
517 }
518 }
519 }
520 return handled;
521 }
522
523 static inline unsigned int adma_intr_mmio(struct ata_host *host)
524 {
525 unsigned int handled = 0, port_no;
526
527 for (port_no = 0; port_no < host->n_ports; ++port_no) {
528 struct ata_port *ap;
529 ap = host->ports[port_no];
530 if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) {
531 struct ata_queued_cmd *qc;
532 struct adma_port_priv *pp = ap->private_data;
533 if (!pp || pp->state != adma_state_mmio)
534 continue;
535 qc = ata_qc_from_tag(ap, ap->link.active_tag);
536 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
537
538 /* check main status, clearing INTRQ */
539 u8 status = ata_check_status(ap);
540 if ((status & ATA_BUSY))
541 continue;
542 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
543 ap->print_id, qc->tf.protocol, status);
544
545 /* complete taskfile transaction */
546 pp->state = adma_state_idle;
547 qc->err_mask |= ac_err_mask(status);
548 if (!qc->err_mask)
549 ata_qc_complete(qc);
550 else {
551 struct ata_eh_info *ehi =
552 &ap->link.eh_info;
553 ata_ehi_clear_desc(ehi);
554 ata_ehi_push_desc(ehi,
555 "status 0x%02X", status);
556
557 if (qc->err_mask == AC_ERR_DEV)
558 ata_port_abort(ap);
559 else
560 ata_port_freeze(ap);
561 }
562 handled = 1;
563 }
564 }
565 }
566 return handled;
567 }
568
569 static irqreturn_t adma_intr(int irq, void *dev_instance)
570 {
571 struct ata_host *host = dev_instance;
572 unsigned int handled = 0;
573
574 VPRINTK("ENTER\n");
575
576 spin_lock(&host->lock);
577 handled = adma_intr_pkt(host) | adma_intr_mmio(host);
578 spin_unlock(&host->lock);
579
580 VPRINTK("EXIT\n");
581
582 return IRQ_RETVAL(handled);
583 }
584
585 static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
586 {
587 port->cmd_addr =
588 port->data_addr = base + 0x000;
589 port->error_addr =
590 port->feature_addr = base + 0x004;
591 port->nsect_addr = base + 0x008;
592 port->lbal_addr = base + 0x00c;
593 port->lbam_addr = base + 0x010;
594 port->lbah_addr = base + 0x014;
595 port->device_addr = base + 0x018;
596 port->status_addr =
597 port->command_addr = base + 0x01c;
598 port->altstatus_addr =
599 port->ctl_addr = base + 0x038;
600 }
601
602 static int adma_port_start(struct ata_port *ap)
603 {
604 struct device *dev = ap->host->dev;
605 struct adma_port_priv *pp;
606 int rc;
607
608 rc = ata_port_start(ap);
609 if (rc)
610 return rc;
611 adma_enter_reg_mode(ap);
612 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
613 if (!pp)
614 return -ENOMEM;
615 pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
616 GFP_KERNEL);
617 if (!pp->pkt)
618 return -ENOMEM;
619 /* paranoia? */
620 if ((pp->pkt_dma & 7) != 0) {
621 printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
622 (u32)pp->pkt_dma);
623 return -ENOMEM;
624 }
625 memset(pp->pkt, 0, ADMA_PKT_BYTES);
626 ap->private_data = pp;
627 adma_reinit_engine(ap);
628 return 0;
629 }
630
631 static void adma_port_stop(struct ata_port *ap)
632 {
633 adma_reset_engine(ap);
634 }
635
636 static void adma_host_stop(struct ata_host *host)
637 {
638 unsigned int port_no;
639
640 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
641 adma_reset_engine(host->ports[port_no]);
642 }
643
644 static void adma_host_init(struct ata_host *host, unsigned int chip_id)
645 {
646 unsigned int port_no;
647
648 /* enable/lock aGO operation */
649 writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
650
651 /* reset the ADMA logic */
652 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
653 adma_reset_engine(host->ports[port_no]);
654 }
655
656 static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
657 {
658 int rc;
659
660 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
661 if (rc) {
662 dev_printk(KERN_ERR, &pdev->dev,
663 "32-bit DMA enable failed\n");
664 return rc;
665 }
666 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
667 if (rc) {
668 dev_printk(KERN_ERR, &pdev->dev,
669 "32-bit consistent DMA enable failed\n");
670 return rc;
671 }
672 return 0;
673 }
674
675 static int adma_ata_init_one(struct pci_dev *pdev,
676 const struct pci_device_id *ent)
677 {
678 static int printed_version;
679 unsigned int board_idx = (unsigned int) ent->driver_data;
680 const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
681 struct ata_host *host;
682 void __iomem *mmio_base;
683 int rc, port_no;
684
685 if (!printed_version++)
686 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
687
688 /* alloc host */
689 host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
690 if (!host)
691 return -ENOMEM;
692
693 /* acquire resources and fill host */
694 rc = pcim_enable_device(pdev);
695 if (rc)
696 return rc;
697
698 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
699 return -ENODEV;
700
701 rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
702 if (rc)
703 return rc;
704 host->iomap = pcim_iomap_table(pdev);
705 mmio_base = host->iomap[ADMA_MMIO_BAR];
706
707 rc = adma_set_dma_masks(pdev, mmio_base);
708 if (rc)
709 return rc;
710
711 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
712 struct ata_port *ap = host->ports[port_no];
713 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
714 unsigned int offset = port_base - mmio_base;
715
716 adma_ata_setup_port(&ap->ioaddr, port_base);
717
718 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
719 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
720 }
721
722 /* initialize adapter */
723 adma_host_init(host, board_idx);
724
725 pci_set_master(pdev);
726 return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
727 &adma_ata_sht);
728 }
729
730 static int __init adma_ata_init(void)
731 {
732 return pci_register_driver(&adma_ata_pci_driver);
733 }
734
735 static void __exit adma_ata_exit(void)
736 {
737 pci_unregister_driver(&adma_ata_pci_driver);
738 }
739
740 MODULE_AUTHOR("Mark Lord");
741 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
742 MODULE_LICENSE("GPL");
743 MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
744 MODULE_VERSION(DRV_VERSION);
745
746 module_init(adma_ata_init);
747 module_exit(adma_ata_exit);
748
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