1 /*
2 * Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
12 *
13 *
14 * TODO
15 * Work out best PLL policy
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <scsi/scsi_host.h>
25 #include <linux/libata.h>
26
27 #define DRV_NAME "pata_hpt3x2n"
28 #define DRV_VERSION "0.3.8"
29
30 enum {
31 HPT_PCI_FAST = (1 << 31),
32 PCI66 = (1 << 1),
33 USE_DPLL = (1 << 0)
34 };
35
36 struct hpt_clock {
37 u8 xfer_speed;
38 u32 timing;
39 };
40
41 struct hpt_chip {
42 const char *name;
43 struct hpt_clock *clocks[3];
44 };
45
46 /* key for bus clock timings
47 * bit
48 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
49 * DMA. cycles = value + 1
50 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
51 * DMA. cycles = value + 1
52 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
53 * register access.
54 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
55 * register access.
56 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
57 * during task file register access.
58 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
59 * xfer.
60 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
61 * register access.
62 * 28 UDMA enable
63 * 29 DMA enable
64 * 30 PIO_MST enable. if set, the chip is in bus master mode during
65 * PIO.
66 * 31 FIFO enable.
67 */
68
69 /* 66MHz DPLL clocks */
70
71 static struct hpt_clock hpt3x2n_clocks[] = {
72 { XFER_UDMA_7, 0x1c869c62 },
73 { XFER_UDMA_6, 0x1c869c62 },
74 { XFER_UDMA_5, 0x1c8a9c62 },
75 { XFER_UDMA_4, 0x1c8a9c62 },
76 { XFER_UDMA_3, 0x1c8e9c62 },
77 { XFER_UDMA_2, 0x1c929c62 },
78 { XFER_UDMA_1, 0x1c9a9c62 },
79 { XFER_UDMA_0, 0x1c829c62 },
80
81 { XFER_MW_DMA_2, 0x2c829c62 },
82 { XFER_MW_DMA_1, 0x2c829c66 },
83 { XFER_MW_DMA_0, 0x2c829d2c },
84
85 { XFER_PIO_4, 0x0c829c62 },
86 { XFER_PIO_3, 0x0c829c84 },
87 { XFER_PIO_2, 0x0c829ca6 },
88 { XFER_PIO_1, 0x0d029d26 },
89 { XFER_PIO_0, 0x0d029d5e },
90 { 0, 0x0d029d5e }
91 };
92
93 /**
94 * hpt3x2n_find_mode - reset the hpt3x2n bus
95 * @ap: ATA port
96 * @speed: transfer mode
97 *
98 * Return the 32bit register programming information for this channel
99 * that matches the speed provided. For the moment the clocks table
100 * is hard coded but easy to change. This will be needed if we use
101 * different DPLLs
102 */
103
104 static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
105 {
106 struct hpt_clock *clocks = hpt3x2n_clocks;
107
108 while(clocks->xfer_speed) {
109 if (clocks->xfer_speed == speed)
110 return clocks->timing;
111 clocks++;
112 }
113 BUG();
114 return 0xffffffffU; /* silence compiler warning */
115 }
116
117 /**
118 * hpt3x2n_cable_detect - Detect the cable type
119 * @ap: ATA port to detect on
120 *
121 * Return the cable type attached to this port
122 */
123
124 static int hpt3x2n_cable_detect(struct ata_port *ap)
125 {
126 u8 scr2, ata66;
127 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
128
129 pci_read_config_byte(pdev, 0x5B, &scr2);
130 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
131 /* Cable register now active */
132 pci_read_config_byte(pdev, 0x5A, &ata66);
133 /* Restore state */
134 pci_write_config_byte(pdev, 0x5B, scr2);
135
136 if (ata66 & (1 << ap->port_no))
137 return ATA_CBL_PATA40;
138 else
139 return ATA_CBL_PATA80;
140 }
141
142 /**
143 * hpt3x2n_pre_reset - reset the hpt3x2n bus
144 * @link: ATA link to reset
145 * @deadline: deadline jiffies for the operation
146 *
147 * Perform the initial reset handling for the 3x2n series controllers.
148 * Reset the hardware and state machine,
149 */
150
151 static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
152 {
153 struct ata_port *ap = link->ap;
154 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
155 /* Reset the state machine */
156 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
157 udelay(100);
158
159 return ata_sff_prereset(link, deadline);
160 }
161
162 /**
163 * hpt3x2n_set_piomode - PIO setup
164 * @ap: ATA interface
165 * @adev: device on the interface
166 *
167 * Perform PIO mode setup.
168 */
169
170 static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
171 {
172 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
173 u32 addr1, addr2;
174 u32 reg;
175 u32 mode;
176 u8 fast;
177
178 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
179 addr2 = 0x51 + 4 * ap->port_no;
180
181 /* Fast interrupt prediction disable, hold off interrupt disable */
182 pci_read_config_byte(pdev, addr2, &fast);
183 fast &= ~0x07;
184 pci_write_config_byte(pdev, addr2, fast);
185
186 pci_read_config_dword(pdev, addr1, ®);
187 mode = hpt3x2n_find_mode(ap, adev->pio_mode);
188 mode &= 0xCFC3FFFF; /* Leave DMA bits alone */
189 reg &= ~0xCFC3FFFF; /* Strip timing bits */
190 pci_write_config_dword(pdev, addr1, reg | mode);
191 }
192
193 /**
194 * hpt3x2n_set_dmamode - DMA timing setup
195 * @ap: ATA interface
196 * @adev: Device being configured
197 *
198 * Set up the channel for MWDMA or UDMA modes. Much the same as with
199 * PIO, load the mode number and then set MWDMA or UDMA flag.
200 */
201
202 static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
203 {
204 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
205 u32 addr1, addr2;
206 u32 reg, mode, mask;
207 u8 fast;
208
209 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
210 addr2 = 0x51 + 4 * ap->port_no;
211
212 /* Fast interrupt prediction disable, hold off interrupt disable */
213 pci_read_config_byte(pdev, addr2, &fast);
214 fast &= ~0x07;
215 pci_write_config_byte(pdev, addr2, fast);
216
217 mask = adev->dma_mode < XFER_UDMA_0 ? 0x31C001FF : 0x303C0000;
218
219 pci_read_config_dword(pdev, addr1, ®);
220 mode = hpt3x2n_find_mode(ap, adev->dma_mode);
221 mode &= mask;
222 reg &= ~mask;
223 pci_write_config_dword(pdev, addr1, reg | mode);
224 }
225
226 /**
227 * hpt3x2n_bmdma_end - DMA engine stop
228 * @qc: ATA command
229 *
230 * Clean up after the HPT3x2n and later DMA engine
231 */
232
233 static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
234 {
235 struct ata_port *ap = qc->ap;
236 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
237 int mscreg = 0x50 + 2 * ap->port_no;
238 u8 bwsr_stat, msc_stat;
239
240 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
241 pci_read_config_byte(pdev, mscreg, &msc_stat);
242 if (bwsr_stat & (1 << ap->port_no))
243 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
244 ata_bmdma_stop(qc);
245 }
246
247 /**
248 * hpt3x2n_set_clock - clock control
249 * @ap: ATA port
250 * @source: 0x21 or 0x23 for PLL or PCI sourced clock
251 *
252 * Switch the ATA bus clock between the PLL and PCI clock sources
253 * while correctly isolating the bus and resetting internal logic
254 *
255 * We must use the DPLL for
256 * - writing
257 * - second channel UDMA7 (SATA ports) or higher
258 * - 66MHz PCI
259 *
260 * or we will underclock the device and get reduced performance.
261 */
262
263 static void hpt3x2n_set_clock(struct ata_port *ap, int source)
264 {
265 void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8;
266
267 /* Tristate the bus */
268 iowrite8(0x80, bmdma+0x73);
269 iowrite8(0x80, bmdma+0x77);
270
271 /* Switch clock and reset channels */
272 iowrite8(source, bmdma+0x7B);
273 iowrite8(0xC0, bmdma+0x79);
274
275 /* Reset state machines, avoid enabling the disabled channels */
276 iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70);
277 iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74);
278
279 /* Complete reset */
280 iowrite8(0x00, bmdma+0x79);
281
282 /* Reconnect channels to bus */
283 iowrite8(0x00, bmdma+0x73);
284 iowrite8(0x00, bmdma+0x77);
285 }
286
287 static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
288 {
289 long flags = (long)ap->host->private_data;
290
291 /* See if we should use the DPLL */
292 if (writing)
293 return USE_DPLL; /* Needed for write */
294 if (flags & PCI66)
295 return USE_DPLL; /* Needed at 66Mhz */
296 return 0;
297 }
298
299 static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc)
300 {
301 struct ata_port *ap = qc->ap;
302 struct ata_port *alt = ap->host->ports[ap->port_no ^ 1];
303 int rc, flags = (long)ap->host->private_data;
304 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
305
306 /* First apply the usual rules */
307 rc = ata_std_qc_defer(qc);
308 if (rc != 0)
309 return rc;
310
311 if ((flags & USE_DPLL) != dpll && alt->qc_active)
312 return ATA_DEFER_PORT;
313 return 0;
314 }
315
316 static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
317 {
318 struct ata_port *ap = qc->ap;
319 int flags = (long)ap->host->private_data;
320 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
321
322 if ((flags & USE_DPLL) != dpll) {
323 flags &= ~USE_DPLL;
324 flags |= dpll;
325 ap->host->private_data = (void *)(long)flags;
326
327 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);
328 }
329 return ata_sff_qc_issue(qc);
330 }
331
332 static struct scsi_host_template hpt3x2n_sht = {
333 ATA_BMDMA_SHT(DRV_NAME),
334 };
335
336 /*
337 * Configuration for HPT3x2n.
338 */
339
340 static struct ata_port_operations hpt3x2n_port_ops = {
341 .inherits = &ata_bmdma_port_ops,
342
343 .bmdma_stop = hpt3x2n_bmdma_stop,
344
345 .qc_defer = hpt3x2n_qc_defer,
346 .qc_issue = hpt3x2n_qc_issue,
347
348 .cable_detect = hpt3x2n_cable_detect,
349 .set_piomode = hpt3x2n_set_piomode,
350 .set_dmamode = hpt3x2n_set_dmamode,
351 .prereset = hpt3x2n_pre_reset,
352 };
353
354 /**
355 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
356 * @dev: PCI device
357 *
358 * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
359 * succeeds
360 */
361
362 static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
363 {
364 u8 reg5b;
365 u32 reg5c;
366 int tries;
367
368 for(tries = 0; tries < 0x5000; tries++) {
369 udelay(50);
370 pci_read_config_byte(dev, 0x5b, ®5b);
371 if (reg5b & 0x80) {
372 /* See if it stays set */
373 for(tries = 0; tries < 0x1000; tries ++) {
374 pci_read_config_byte(dev, 0x5b, ®5b);
375 /* Failed ? */
376 if ((reg5b & 0x80) == 0)
377 return 0;
378 }
379 /* Turn off tuning, we have the DPLL set */
380 pci_read_config_dword(dev, 0x5c, ®5c);
381 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
382 return 1;
383 }
384 }
385 /* Never went stable */
386 return 0;
387 }
388
389 static int hpt3x2n_pci_clock(struct pci_dev *pdev)
390 {
391 unsigned long freq;
392 u32 fcnt;
393 unsigned long iobase = pci_resource_start(pdev, 4);
394
395 fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */
396 if ((fcnt >> 12) != 0xABCDE) {
397 printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n");
398 return 33; /* Not BIOS set */
399 }
400 fcnt &= 0x1FF;
401
402 freq = (fcnt * 77) / 192;
403
404 /* Clamp to bands */
405 if (freq < 40)
406 return 33;
407 if (freq < 45)
408 return 40;
409 if (freq < 55)
410 return 50;
411 return 66;
412 }
413
414 /**
415 * hpt3x2n_init_one - Initialise an HPT37X/302
416 * @dev: PCI device
417 * @id: Entry in match table
418 *
419 * Initialise an HPT3x2n device. There are some interesting complications
420 * here. Firstly the chip may report 366 and be one of several variants.
421 * Secondly all the timings depend on the clock for the chip which we must
422 * detect and look up
423 *
424 * This is the known chip mappings. It may be missing a couple of later
425 * releases.
426 *
427 * Chip version PCI Rev Notes
428 * HPT372 4 (HPT366) 5 Other driver
429 * HPT372N 4 (HPT366) 6 UDMA133
430 * HPT372 5 (HPT372) 1 Other driver
431 * HPT372N 5 (HPT372) 2 UDMA133
432 * HPT302 6 (HPT302) * Other driver
433 * HPT302N 6 (HPT302) > 1 UDMA133
434 * HPT371 7 (HPT371) * Other driver
435 * HPT371N 7 (HPT371) > 1 UDMA133
436 * HPT374 8 (HPT374) * Other driver
437 * HPT372N 9 (HPT372N) * UDMA133
438 *
439 * (1) UDMA133 support depends on the bus clock
440 *
441 * To pin down HPT371N
442 */
443
444 static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
445 {
446 /* HPT372N and friends - UDMA133 */
447 static const struct ata_port_info info = {
448 .flags = ATA_FLAG_SLAVE_POSS,
449 .pio_mask = ATA_PIO4,
450 .mwdma_mask = ATA_MWDMA2,
451 .udma_mask = ATA_UDMA6,
452 .port_ops = &hpt3x2n_port_ops
453 };
454 const struct ata_port_info *ppi[] = { &info, NULL };
455
456 u8 irqmask;
457 u32 class_rev;
458
459 unsigned int pci_mhz;
460 unsigned int f_low, f_high;
461 int adjust;
462 unsigned long iobase = pci_resource_start(dev, 4);
463 void *hpriv = (void *)USE_DPLL;
464 int rc;
465
466 rc = pcim_enable_device(dev);
467 if (rc)
468 return rc;
469
470 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
471 class_rev &= 0xFF;
472
473 switch(dev->device) {
474 case PCI_DEVICE_ID_TTI_HPT366:
475 if (class_rev < 6)
476 return -ENODEV;
477 break;
478 case PCI_DEVICE_ID_TTI_HPT371:
479 if (class_rev < 2)
480 return -ENODEV;
481 /* 371N if rev > 1 */
482 break;
483 case PCI_DEVICE_ID_TTI_HPT372:
484 /* 372N if rev >= 2*/
485 if (class_rev < 2)
486 return -ENODEV;
487 break;
488 case PCI_DEVICE_ID_TTI_HPT302:
489 if (class_rev < 2)
490 return -ENODEV;
491 break;
492 case PCI_DEVICE_ID_TTI_HPT372N:
493 break;
494 default:
495 printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device);
496 return -ENODEV;
497 }
498
499 /* Ok so this is a chip we support */
500
501 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
502 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
503 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
504 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
505
506 pci_read_config_byte(dev, 0x5A, &irqmask);
507 irqmask &= ~0x10;
508 pci_write_config_byte(dev, 0x5a, irqmask);
509
510 /*
511 * HPT371 chips physically have only one channel, the secondary one,
512 * but the primary channel registers do exist! Go figure...
513 * So, we manually disable the non-existing channel here
514 * (if the BIOS hasn't done this already).
515 */
516 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
517 u8 mcr1;
518 pci_read_config_byte(dev, 0x50, &mcr1);
519 mcr1 &= ~0x04;
520 pci_write_config_byte(dev, 0x50, mcr1);
521 }
522
523 /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
524 50 for UDMA100. Right now we always use 66 */
525
526 pci_mhz = hpt3x2n_pci_clock(dev);
527
528 f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */
529 f_high = f_low + 2; /* Tolerance */
530
531 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
532 /* PLL clock */
533 pci_write_config_byte(dev, 0x5B, 0x21);
534
535 /* Unlike the 37x we don't try jiggling the frequency */
536 for(adjust = 0; adjust < 8; adjust++) {
537 if (hpt3xn_calibrate_dpll(dev))
538 break;
539 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
540 }
541 if (adjust == 8) {
542 printk(KERN_ERR "pata_hpt3x2n: DPLL did not stabilize!\n");
543 return -ENODEV;
544 }
545
546 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using 66MHz DPLL.\n",
547 pci_mhz);
548 /* Set our private data up. We only need a few flags so we use
549 it directly */
550 if (pci_mhz > 60) {
551 hpriv = (void *)(PCI66 | USE_DPLL);
552 /*
553 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
554 * the MISC. register to stretch the UltraDMA Tss timing.
555 * NOTE: This register is only writeable via I/O space.
556 */
557 if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
558 outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
559 }
560
561 /* Now kick off ATA set up */
562 return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv);
563 }
564
565 static const struct pci_device_id hpt3x2n[] = {
566 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
567 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
568 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
569 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
570 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
571
572 { },
573 };
574
575 static struct pci_driver hpt3x2n_pci_driver = {
576 .name = DRV_NAME,
577 .id_table = hpt3x2n,
578 .probe = hpt3x2n_init_one,
579 .remove = ata_pci_remove_one
580 };
581
582 static int __init hpt3x2n_init(void)
583 {
584 return pci_register_driver(&hpt3x2n_pci_driver);
585 }
586
587 static void __exit hpt3x2n_exit(void)
588 {
589 pci_unregister_driver(&hpt3x2n_pci_driver);
590 }
591
592 MODULE_AUTHOR("Alan Cox");
593 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x");
594 MODULE_LICENSE("GPL");
595 MODULE_DEVICE_TABLE(pci, hpt3x2n);
596 MODULE_VERSION(DRV_VERSION);
597
598 module_init(hpt3x2n_init);
599 module_exit(hpt3x2n_exit);
600
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