1 /*
2 * processor_idle - idle state submodule to the ACPI processor driver
3 *
4 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
5 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
6 * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de>
7 * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
8 * - Added processor hotplug support
9 * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
10 * - Added support for C3 on SMP
11 *
12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or (at
17 * your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22 * General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 *
28 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
29 */
30
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/init.h>
34 #include <linux/cpufreq.h>
35 #include <linux/proc_fs.h>
36 #include <linux/seq_file.h>
37 #include <linux/acpi.h>
38 #include <linux/dmi.h>
39 #include <linux/moduleparam.h>
40 #include <linux/sched.h> /* need_resched() */
41 #include <linux/pm_qos_params.h>
42 #include <linux/clockchips.h>
43 #include <linux/cpuidle.h>
44
45 /*
46 * Include the apic definitions for x86 to have the APIC timer related defines
47 * available also for UP (on SMP it gets magically included via linux/smp.h).
48 * asm/acpi.h is not an option, as it would require more include magic. Also
49 * creating an empty asm-ia64/apic.h would just trade pest vs. cholera.
50 */
51 #ifdef CONFIG_X86
52 #include <asm/apic.h>
53 #endif
54
55 #include <asm/io.h>
56 #include <asm/uaccess.h>
57
58 #include <acpi/acpi_bus.h>
59 #include <acpi/processor.h>
60
61 #define ACPI_PROCESSOR_COMPONENT 0x01000000
62 #define ACPI_PROCESSOR_CLASS "processor"
63 #define _COMPONENT ACPI_PROCESSOR_COMPONENT
64 ACPI_MODULE_NAME("processor_idle");
65 #define ACPI_PROCESSOR_FILE_POWER "power"
66 #define US_TO_PM_TIMER_TICKS(t) ((t * (PM_TIMER_FREQUENCY/1000)) / 1000)
67 #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY)
68 #ifndef CONFIG_CPU_IDLE
69 #define C2_OVERHEAD 4 /* 1us (3.579 ticks per us) */
70 #define C3_OVERHEAD 4 /* 1us (3.579 ticks per us) */
71 static void (*pm_idle_save) (void) __read_mostly;
72 #else
73 #define C2_OVERHEAD 1 /* 1us */
74 #define C3_OVERHEAD 1 /* 1us */
75 #endif
76 #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000))
77
78 static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER;
79 #ifdef CONFIG_CPU_IDLE
80 module_param(max_cstate, uint, 0000);
81 #else
82 module_param(max_cstate, uint, 0644);
83 #endif
84 static unsigned int nocst __read_mostly;
85 module_param(nocst, uint, 0000);
86
87 #ifndef CONFIG_CPU_IDLE
88 /*
89 * bm_history -- bit-mask with a bit per jiffy of bus-master activity
90 * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms
91 * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms
92 * 100 HZ: 0x0000000F: 4 jiffies = 40ms
93 * reduce history for more aggressive entry into C3
94 */
95 static unsigned int bm_history __read_mostly =
96 (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1));
97 module_param(bm_history, uint, 0644);
98
99 static int acpi_processor_set_power_policy(struct acpi_processor *pr);
100
101 #else /* CONFIG_CPU_IDLE */
102 static unsigned int latency_factor __read_mostly = 2;
103 module_param(latency_factor, uint, 0644);
104 #endif
105
106 /*
107 * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3.
108 * For now disable this. Probably a bug somewhere else.
109 *
110 * To skip this limit, boot/load with a large max_cstate limit.
111 */
112 static int set_max_cstate(const struct dmi_system_id *id)
113 {
114 if (max_cstate > ACPI_PROCESSOR_MAX_POWER)
115 return 0;
116
117 printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate."
118 " Override with \"processor.max_cstate=%d\"\n", id->ident,
119 (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1);
120
121 max_cstate = (long)id->driver_data;
122
123 return 0;
124 }
125
126 /* Actually this shouldn't be __cpuinitdata, would be better to fix the
127 callers to only run once -AK */
128 static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = {
129 { set_max_cstate, "IBM ThinkPad R40e", {
130 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
131 DMI_MATCH(DMI_BIOS_VERSION,"1SET70WW")}, (void *)1},
132 { set_max_cstate, "IBM ThinkPad R40e", {
133 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
134 DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW")}, (void *)1},
135 { set_max_cstate, "IBM ThinkPad R40e", {
136 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
137 DMI_MATCH(DMI_BIOS_VERSION,"1SET43WW") }, (void*)1},
138 { set_max_cstate, "IBM ThinkPad R40e", {
139 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
140 DMI_MATCH(DMI_BIOS_VERSION,"1SET45WW") }, (void*)1},
141 { set_max_cstate, "IBM ThinkPad R40e", {
142 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
143 DMI_MATCH(DMI_BIOS_VERSION,"1SET47WW") }, (void*)1},
144 { set_max_cstate, "IBM ThinkPad R40e", {
145 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
146 DMI_MATCH(DMI_BIOS_VERSION,"1SET50WW") }, (void*)1},
147 { set_max_cstate, "IBM ThinkPad R40e", {
148 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
149 DMI_MATCH(DMI_BIOS_VERSION,"1SET52WW") }, (void*)1},
150 { set_max_cstate, "IBM ThinkPad R40e", {
151 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
152 DMI_MATCH(DMI_BIOS_VERSION,"1SET55WW") }, (void*)1},
153 { set_max_cstate, "IBM ThinkPad R40e", {
154 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
155 DMI_MATCH(DMI_BIOS_VERSION,"1SET56WW") }, (void*)1},
156 { set_max_cstate, "IBM ThinkPad R40e", {
157 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
158 DMI_MATCH(DMI_BIOS_VERSION,"1SET59WW") }, (void*)1},
159 { set_max_cstate, "IBM ThinkPad R40e", {
160 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
161 DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1},
162 { set_max_cstate, "IBM ThinkPad R40e", {
163 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
164 DMI_MATCH(DMI_BIOS_VERSION,"1SET61WW") }, (void*)1},
165 { set_max_cstate, "IBM ThinkPad R40e", {
166 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
167 DMI_MATCH(DMI_BIOS_VERSION,"1SET62WW") }, (void*)1},
168 { set_max_cstate, "IBM ThinkPad R40e", {
169 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
170 DMI_MATCH(DMI_BIOS_VERSION,"1SET64WW") }, (void*)1},
171 { set_max_cstate, "IBM ThinkPad R40e", {
172 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
173 DMI_MATCH(DMI_BIOS_VERSION,"1SET65WW") }, (void*)1},
174 { set_max_cstate, "IBM ThinkPad R40e", {
175 DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
176 DMI_MATCH(DMI_BIOS_VERSION,"1SET68WW") }, (void*)1},
177 { set_max_cstate, "Medion 41700", {
178 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
179 DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J")}, (void *)1},
180 { set_max_cstate, "Clevo 5600D", {
181 DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
182 DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")},
183 (void *)2},
184 {},
185 };
186
187 static inline u32 ticks_elapsed(u32 t1, u32 t2)
188 {
189 if (t2 >= t1)
190 return (t2 - t1);
191 else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER))
192 return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF);
193 else
194 return ((0xFFFFFFFF - t1) + t2);
195 }
196
197 static inline u32 ticks_elapsed_in_us(u32 t1, u32 t2)
198 {
199 if (t2 >= t1)
200 return PM_TIMER_TICKS_TO_US(t2 - t1);
201 else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER))
202 return PM_TIMER_TICKS_TO_US(((0x00FFFFFF - t1) + t2) & 0x00FFFFFF);
203 else
204 return PM_TIMER_TICKS_TO_US((0xFFFFFFFF - t1) + t2);
205 }
206
207 /*
208 * Callers should disable interrupts before the call and enable
209 * interrupts after return.
210 */
211 static void acpi_safe_halt(void)
212 {
213 current_thread_info()->status &= ~TS_POLLING;
214 /*
215 * TS_POLLING-cleared state must be visible before we
216 * test NEED_RESCHED:
217 */
218 smp_mb();
219 if (!need_resched() || !need_resched_delayed()) {
220 safe_halt();
221 local_irq_disable();
222 }
223 current_thread_info()->status |= TS_POLLING;
224 }
225
226 #ifndef CONFIG_CPU_IDLE
227
228 static void
229 acpi_processor_power_activate(struct acpi_processor *pr,
230 struct acpi_processor_cx *new)
231 {
232 struct acpi_processor_cx *old;
233
234 if (!pr || !new)
235 return;
236
237 old = pr->power.state;
238
239 if (old)
240 old->promotion.count = 0;
241 new->demotion.count = 0;
242
243 /* Cleanup from old state. */
244 if (old) {
245 switch (old->type) {
246 case ACPI_STATE_C3:
247 /* Disable bus master reload */
248 if (new->type != ACPI_STATE_C3 && pr->flags.bm_check)
249 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
250 break;
251 }
252 }
253
254 /* Prepare to use new state. */
255 switch (new->type) {
256 case ACPI_STATE_C3:
257 /* Enable bus master reload */
258 if (old->type != ACPI_STATE_C3 && pr->flags.bm_check)
259 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1);
260 break;
261 }
262
263 pr->power.state = new;
264
265 return;
266 }
267
268 static atomic_t c3_cpu_count;
269
270 /* Common C-state entry for C2, C3, .. */
271 static void acpi_cstate_enter(struct acpi_processor_cx *cstate)
272 {
273 if (cstate->entry_method == ACPI_CSTATE_FFH) {
274 /* Call into architectural FFH based C-state */
275 acpi_processor_ffh_cstate_enter(cstate);
276 } else {
277 int unused;
278 /* IO port based C-state */
279 inb(cstate->address);
280 /* Dummy wait op - must do something useless after P_LVL2 read
281 because chipsets cannot guarantee that STPCLK# signal
282 gets asserted in time to freeze execution properly. */
283 unused = inl(acpi_gbl_FADT.xpm_timer_block.address);
284 }
285 }
286 #endif /* !CONFIG_CPU_IDLE */
287
288 #ifdef ARCH_APICTIMER_STOPS_ON_C3
289
290 /*
291 * Some BIOS implementations switch to C3 in the published C2 state.
292 * This seems to be a common problem on AMD boxen, but other vendors
293 * are affected too. We pick the most conservative approach: we assume
294 * that the local APIC stops in both C2 and C3.
295 */
296 static void acpi_timer_check_state(int state, struct acpi_processor *pr,
297 struct acpi_processor_cx *cx)
298 {
299 struct acpi_processor_power *pwr = &pr->power;
300 u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2;
301
302 /*
303 * Check, if one of the previous states already marked the lapic
304 * unstable
305 */
306 if (pwr->timer_broadcast_on_state < state)
307 return;
308
309 if (cx->type >= type)
310 pr->power.timer_broadcast_on_state = state;
311 }
312
313 static void acpi_propagate_timer_broadcast(struct acpi_processor *pr)
314 {
315 unsigned long reason;
316
317 reason = pr->power.timer_broadcast_on_state < INT_MAX ?
318 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
319
320 clockevents_notify(reason, &pr->id);
321 }
322
323 /* Power(C) State timer broadcast control */
324 static void acpi_state_timer_broadcast(struct acpi_processor *pr,
325 struct acpi_processor_cx *cx,
326 int broadcast)
327 {
328 int state = cx - pr->power.states;
329
330 if (state >= pr->power.timer_broadcast_on_state) {
331 unsigned long reason;
332
333 reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER :
334 CLOCK_EVT_NOTIFY_BROADCAST_EXIT;
335 clockevents_notify(reason, &pr->id);
336 }
337 }
338
339 #else
340
341 static void acpi_timer_check_state(int state, struct acpi_processor *pr,
342 struct acpi_processor_cx *cstate) { }
343 static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { }
344 static void acpi_state_timer_broadcast(struct acpi_processor *pr,
345 struct acpi_processor_cx *cx,
346 int broadcast)
347 {
348 }
349
350 #endif
351
352 /*
353 * Suspend / resume control
354 */
355 static int acpi_idle_suspend;
356
357 int acpi_processor_suspend(struct acpi_device * device, pm_message_t state)
358 {
359 acpi_idle_suspend = 1;
360 return 0;
361 }
362
363 int acpi_processor_resume(struct acpi_device * device)
364 {
365 acpi_idle_suspend = 0;
366 return 0;
367 }
368
369 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
370 static int tsc_halts_in_c(int state)
371 {
372 switch (boot_cpu_data.x86_vendor) {
373 case X86_VENDOR_AMD:
374 /*
375 * AMD Fam10h TSC will tick in all
376 * C/P/S0/S1 states when this bit is set.
377 */
378 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
379 return 0;
380 /*FALL THROUGH*/
381 case X86_VENDOR_INTEL:
382 /* Several cases known where TSC halts in C2 too */
383 default:
384 return state > ACPI_STATE_C1;
385 }
386 }
387 #endif
388
389 #ifndef CONFIG_CPU_IDLE
390 static void acpi_processor_idle(void)
391 {
392 struct acpi_processor *pr = NULL;
393 struct acpi_processor_cx *cx = NULL;
394 struct acpi_processor_cx *next_state = NULL;
395 int sleep_ticks = 0;
396 u32 t1, t2 = 0;
397
398 /*
399 * Interrupts must be disabled during bus mastering calculations and
400 * for C2/C3 transitions.
401 */
402 local_irq_disable();
403
404 pr = processors[smp_processor_id()];
405 if (!pr) {
406 local_irq_enable();
407 return;
408 }
409
410 /*
411 * Check whether we truly need to go idle, or should
412 * reschedule:
413 */
414 if (unlikely(need_resched())) {
415 local_irq_enable();
416 return;
417 }
418
419 cx = pr->power.state;
420 if (!cx || acpi_idle_suspend) {
421 if (pm_idle_save)
422 pm_idle_save();
423 else
424 acpi_safe_halt();
425
426 if (irqs_disabled())
427 local_irq_enable();
428
429 return;
430 }
431
432 /*
433 * Check BM Activity
434 * -----------------
435 * Check for bus mastering activity (if required), record, and check
436 * for demotion.
437 */
438 if (pr->flags.bm_check) {
439 u32 bm_status = 0;
440 unsigned long diff = jiffies - pr->power.bm_check_timestamp;
441
442 if (diff > 31)
443 diff = 31;
444
445 pr->power.bm_activity <<= diff;
446
447 acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
448 if (bm_status) {
449 pr->power.bm_activity |= 0x1;
450 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
451 }
452 /*
453 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
454 * the true state of bus mastering activity; forcing us to
455 * manually check the BMIDEA bit of each IDE channel.
456 */
457 else if (errata.piix4.bmisx) {
458 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01)
459 || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01))
460 pr->power.bm_activity |= 0x1;
461 }
462
463 pr->power.bm_check_timestamp = jiffies;
464
465 /*
466 * If bus mastering is or was active this jiffy, demote
467 * to avoid a faulty transition. Note that the processor
468 * won't enter a low-power state during this call (to this
469 * function) but should upon the next.
470 *
471 * TBD: A better policy might be to fallback to the demotion
472 * state (use it for this quantum only) istead of
473 * demoting -- and rely on duration as our sole demotion
474 * qualification. This may, however, introduce DMA
475 * issues (e.g. floppy DMA transfer overrun/underrun).
476 */
477 if ((pr->power.bm_activity & 0x1) &&
478 cx->demotion.threshold.bm) {
479 local_irq_enable();
480 next_state = cx->demotion.state;
481 goto end;
482 }
483 }
484
485 #ifdef CONFIG_HOTPLUG_CPU
486 /*
487 * Check for P_LVL2_UP flag before entering C2 and above on
488 * an SMP system. We do it here instead of doing it at _CST/P_LVL
489 * detection phase, to work cleanly with logical CPU hotplug.
490 */
491 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) &&
492 !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
493 cx = &pr->power.states[ACPI_STATE_C1];
494 #endif
495
496 /*
497 * Sleep:
498 * ------
499 * Invoke the current Cx state to put the processor to sleep.
500 */
501 if (cx->type == ACPI_STATE_C2 || cx->type == ACPI_STATE_C3) {
502 current_thread_info()->status &= ~TS_POLLING;
503 /*
504 * TS_POLLING-cleared state must be visible before we
505 * test NEED_RESCHED:
506 */
507 smp_mb();
508 if (need_resched()) {
509 current_thread_info()->status |= TS_POLLING;
510 local_irq_enable();
511 return;
512 }
513 }
514
515 switch (cx->type) {
516
517 case ACPI_STATE_C1:
518 /*
519 * Invoke C1.
520 * Use the appropriate idle routine, the one that would
521 * be used without acpi C-states.
522 */
523 if (pm_idle_save)
524 pm_idle_save();
525 else
526 acpi_safe_halt();
527
528 /*
529 * TBD: Can't get time duration while in C1, as resumes
530 * go to an ISR rather than here. Need to instrument
531 * base interrupt handler.
532 *
533 * Note: the TSC better not stop in C1, sched_clock() will
534 * skew otherwise.
535 */
536 sleep_ticks = 0xFFFFFFFF;
537 if (irqs_disabled())
538 local_irq_enable();
539
540 break;
541
542 case ACPI_STATE_C2:
543 /* Get start time (ticks) */
544 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
545 /* Tell the scheduler that we are going deep-idle: */
546 sched_clock_idle_sleep_event();
547 /* Invoke C2 */
548 acpi_state_timer_broadcast(pr, cx, 1);
549 acpi_cstate_enter(cx);
550 /* Get end time (ticks) */
551 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
552
553 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
554 /* TSC halts in C2, so notify users */
555 if (tsc_halts_in_c(ACPI_STATE_C2))
556 mark_tsc_unstable("possible TSC halt in C2");
557 #endif
558 /* Compute time (ticks) that we were actually asleep */
559 sleep_ticks = ticks_elapsed(t1, t2);
560
561 /* Tell the scheduler how much we idled: */
562 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
563
564 /* Re-enable interrupts */
565 local_irq_enable();
566 /* Do not account our idle-switching overhead: */
567 sleep_ticks -= cx->latency_ticks + C2_OVERHEAD;
568
569 current_thread_info()->status |= TS_POLLING;
570 acpi_state_timer_broadcast(pr, cx, 0);
571 break;
572
573 case ACPI_STATE_C3:
574 acpi_unlazy_tlb(smp_processor_id());
575 /*
576 * Must be done before busmaster disable as we might
577 * need to access HPET !
578 */
579 acpi_state_timer_broadcast(pr, cx, 1);
580 /*
581 * disable bus master
582 * bm_check implies we need ARB_DIS
583 * !bm_check implies we need cache flush
584 * bm_control implies whether we can do ARB_DIS
585 *
586 * That leaves a case where bm_check is set and bm_control is
587 * not set. In that case we cannot do much, we enter C3
588 * without doing anything.
589 */
590 if (pr->flags.bm_check && pr->flags.bm_control) {
591 if (atomic_inc_return(&c3_cpu_count) ==
592 num_online_cpus()) {
593 /*
594 * All CPUs are trying to go to C3
595 * Disable bus master arbitration
596 */
597 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
598 }
599 } else if (!pr->flags.bm_check) {
600 /* SMP with no shared cache... Invalidate cache */
601 ACPI_FLUSH_CPU_CACHE();
602 }
603
604 /* Get start time (ticks) */
605 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
606 /* Invoke C3 */
607 /* Tell the scheduler that we are going deep-idle: */
608 sched_clock_idle_sleep_event();
609 acpi_cstate_enter(cx);
610 /* Get end time (ticks) */
611 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
612 if (pr->flags.bm_check && pr->flags.bm_control) {
613 /* Enable bus master arbitration */
614 atomic_dec(&c3_cpu_count);
615 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
616 }
617
618 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
619 /* TSC halts in C3, so notify users */
620 if (tsc_halts_in_c(ACPI_STATE_C3))
621 mark_tsc_unstable("TSC halts in C3");
622 #endif
623 /* Compute time (ticks) that we were actually asleep */
624 sleep_ticks = ticks_elapsed(t1, t2);
625 /* Tell the scheduler how much we idled: */
626 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
627
628 /* Re-enable interrupts */
629 local_irq_enable();
630 /* Do not account our idle-switching overhead: */
631 sleep_ticks -= cx->latency_ticks + C3_OVERHEAD;
632
633 current_thread_info()->status |= TS_POLLING;
634 acpi_state_timer_broadcast(pr, cx, 0);
635 break;
636
637 default:
638 local_irq_enable();
639 return;
640 }
641 cx->usage++;
642 if ((cx->type != ACPI_STATE_C1) && (sleep_ticks > 0))
643 cx->time += sleep_ticks;
644
645 next_state = pr->power.state;
646
647 #ifdef CONFIG_HOTPLUG_CPU
648 /* Don't do promotion/demotion */
649 if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) &&
650 !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) {
651 next_state = cx;
652 goto end;
653 }
654 #endif
655
656 /*
657 * Promotion?
658 * ----------
659 * Track the number of longs (time asleep is greater than threshold)
660 * and promote when the count threshold is reached. Note that bus
661 * mastering activity may prevent promotions.
662 * Do not promote above max_cstate.
663 */
664 if (cx->promotion.state &&
665 ((cx->promotion.state - pr->power.states) <= max_cstate)) {
666 if (sleep_ticks > cx->promotion.threshold.ticks &&
667 cx->promotion.state->latency <=
668 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)) {
669 cx->promotion.count++;
670 cx->demotion.count = 0;
671 if (cx->promotion.count >=
672 cx->promotion.threshold.count) {
673 if (pr->flags.bm_check) {
674 if (!
675 (pr->power.bm_activity & cx->
676 promotion.threshold.bm)) {
677 next_state =
678 cx->promotion.state;
679 goto end;
680 }
681 } else {
682 next_state = cx->promotion.state;
683 goto end;
684 }
685 }
686 }
687 }
688
689 /*
690 * Demotion?
691 * ---------
692 * Track the number of shorts (time asleep is less than time threshold)
693 * and demote when the usage threshold is reached.
694 */
695 if (cx->demotion.state) {
696 if (sleep_ticks < cx->demotion.threshold.ticks) {
697 cx->demotion.count++;
698 cx->promotion.count = 0;
699 if (cx->demotion.count >= cx->demotion.threshold.count) {
700 next_state = cx->demotion.state;
701 goto end;
702 }
703 }
704 }
705
706 end:
707 /*
708 * Demote if current state exceeds max_cstate
709 * or if the latency of the current state is unacceptable
710 */
711 if ((pr->power.state - pr->power.states) > max_cstate ||
712 pr->power.state->latency >
713 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)) {
714 if (cx->demotion.state)
715 next_state = cx->demotion.state;
716 }
717
718 /*
719 * New Cx State?
720 * -------------
721 * If we're going to start using a new Cx state we must clean up
722 * from the previous and prepare to use the new.
723 */
724 if (next_state != pr->power.state)
725 acpi_processor_power_activate(pr, next_state);
726 }
727
728 static int acpi_processor_set_power_policy(struct acpi_processor *pr)
729 {
730 unsigned int i;
731 unsigned int state_is_set = 0;
732 struct acpi_processor_cx *lower = NULL;
733 struct acpi_processor_cx *higher = NULL;
734 struct acpi_processor_cx *cx;
735
736
737 if (!pr)
738 return -EINVAL;
739
740 /*
741 * This function sets the default Cx state policy (OS idle handler).
742 * Our scheme is to promote quickly to C2 but more conservatively
743 * to C3. We're favoring C2 for its characteristics of low latency
744 * (quick response), good power savings, and ability to allow bus
745 * mastering activity. Note that the Cx state policy is completely
746 * customizable and can be altered dynamically.
747 */
748
749 /* startup state */
750 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
751 cx = &pr->power.states[i];
752 if (!cx->valid)
753 continue;
754
755 if (!state_is_set)
756 pr->power.state = cx;
757 state_is_set++;
758 break;
759 }
760
761 if (!state_is_set)
762 return -ENODEV;
763
764 /* demotion */
765 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
766 cx = &pr->power.states[i];
767 if (!cx->valid)
768 continue;
769
770 if (lower) {
771 cx->demotion.state = lower;
772 cx->demotion.threshold.ticks = cx->latency_ticks;
773 cx->demotion.threshold.count = 1;
774 if (cx->type == ACPI_STATE_C3)
775 cx->demotion.threshold.bm = bm_history;
776 }
777
778 lower = cx;
779 }
780
781 /* promotion */
782 for (i = (ACPI_PROCESSOR_MAX_POWER - 1); i > 0; i--) {
783 cx = &pr->power.states[i];
784 if (!cx->valid)
785 continue;
786
787 if (higher) {
788 cx->promotion.state = higher;
789 cx->promotion.threshold.ticks = cx->latency_ticks;
790 if (cx->type >= ACPI_STATE_C2)
791 cx->promotion.threshold.count = 4;
792 else
793 cx->promotion.threshold.count = 10;
794 if (higher->type == ACPI_STATE_C3)
795 cx->promotion.threshold.bm = bm_history;
796 }
797
798 higher = cx;
799 }
800
801 return 0;
802 }
803 #endif /* !CONFIG_CPU_IDLE */
804
805 static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr)
806 {
807
808 if (!pr)
809 return -EINVAL;
810
811 if (!pr->pblk)
812 return -ENODEV;
813
814 /* if info is obtained from pblk/fadt, type equals state */
815 pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2;
816 pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3;
817
818 #ifndef CONFIG_HOTPLUG_CPU
819 /*
820 * Check for P_LVL2_UP flag before entering C2 and above on
821 * an SMP system.
822 */
823 if ((num_online_cpus() > 1) &&
824 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
825 return -ENODEV;
826 #endif
827
828 /* determine C2 and C3 address from pblk */
829 pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4;
830 pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5;
831
832 /* determine latencies from FADT */
833 pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency;
834 pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency;
835
836 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
837 "lvl2[0x%08x] lvl3[0x%08x]\n",
838 pr->power.states[ACPI_STATE_C2].address,
839 pr->power.states[ACPI_STATE_C3].address));
840
841 return 0;
842 }
843
844 static int acpi_processor_get_power_info_default(struct acpi_processor *pr)
845 {
846 if (!pr->power.states[ACPI_STATE_C1].valid) {
847 /* set the first C-State to C1 */
848 /* all processors need to support C1 */
849 pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1;
850 pr->power.states[ACPI_STATE_C1].valid = 1;
851 pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT;
852 }
853 /* the C0 state only exists as a filler in our array */
854 pr->power.states[ACPI_STATE_C0].valid = 1;
855 return 0;
856 }
857
858 static int acpi_processor_get_power_info_cst(struct acpi_processor *pr)
859 {
860 acpi_status status = 0;
861 acpi_integer count;
862 int current_count;
863 int i;
864 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
865 union acpi_object *cst;
866
867
868 if (nocst)
869 return -ENODEV;
870
871 current_count = 0;
872
873 status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer);
874 if (ACPI_FAILURE(status)) {
875 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n"));
876 return -ENODEV;
877 }
878
879 cst = buffer.pointer;
880
881 /* There must be at least 2 elements */
882 if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) {
883 printk(KERN_ERR PREFIX "not enough elements in _CST\n");
884 status = -EFAULT;
885 goto end;
886 }
887
888 count = cst->package.elements[0].integer.value;
889
890 /* Validate number of power states. */
891 if (count < 1 || count != cst->package.count - 1) {
892 printk(KERN_ERR PREFIX "count given by _CST is not valid\n");
893 status = -EFAULT;
894 goto end;
895 }
896
897 /* Tell driver that at least _CST is supported. */
898 pr->flags.has_cst = 1;
899
900 for (i = 1; i <= count; i++) {
901 union acpi_object *element;
902 union acpi_object *obj;
903 struct acpi_power_register *reg;
904 struct acpi_processor_cx cx;
905
906 memset(&cx, 0, sizeof(cx));
907
908 element = &(cst->package.elements[i]);
909 if (element->type != ACPI_TYPE_PACKAGE)
910 continue;
911
912 if (element->package.count != 4)
913 continue;
914
915 obj = &(element->package.elements[0]);
916
917 if (obj->type != ACPI_TYPE_BUFFER)
918 continue;
919
920 reg = (struct acpi_power_register *)obj->buffer.pointer;
921
922 if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO &&
923 (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE))
924 continue;
925
926 /* There should be an easy way to extract an integer... */
927 obj = &(element->package.elements[1]);
928 if (obj->type != ACPI_TYPE_INTEGER)
929 continue;
930
931 cx.type = obj->integer.value;
932 /*
933 * Some buggy BIOSes won't list C1 in _CST -
934 * Let acpi_processor_get_power_info_default() handle them later
935 */
936 if (i == 1 && cx.type != ACPI_STATE_C1)
937 current_count++;
938
939 cx.address = reg->address;
940 cx.index = current_count + 1;
941
942 cx.entry_method = ACPI_CSTATE_SYSTEMIO;
943 if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) {
944 if (acpi_processor_ffh_cstate_probe
945 (pr->id, &cx, reg) == 0) {
946 cx.entry_method = ACPI_CSTATE_FFH;
947 } else if (cx.type == ACPI_STATE_C1) {
948 /*
949 * C1 is a special case where FIXED_HARDWARE
950 * can be handled in non-MWAIT way as well.
951 * In that case, save this _CST entry info.
952 * Otherwise, ignore this info and continue.
953 */
954 cx.entry_method = ACPI_CSTATE_HALT;
955 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT");
956 } else {
957 continue;
958 }
959 } else {
960 snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x",
961 cx.address);
962 }
963
964 if (cx.type == ACPI_STATE_C1) {
965 cx.valid = 1;
966 }
967
968 obj = &(element->package.elements[2]);
969 if (obj->type != ACPI_TYPE_INTEGER)
970 continue;
971
972 cx.latency = obj->integer.value;
973
974 obj = &(element->package.elements[3]);
975 if (obj->type != ACPI_TYPE_INTEGER)
976 continue;
977
978 cx.power = obj->integer.value;
979
980 current_count++;
981 memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx));
982
983 /*
984 * We support total ACPI_PROCESSOR_MAX_POWER - 1
985 * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1)
986 */
987 if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) {
988 printk(KERN_WARNING
989 "Limiting number of power states to max (%d)\n",
990 ACPI_PROCESSOR_MAX_POWER);
991 printk(KERN_WARNING
992 "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n");
993 break;
994 }
995 }
996
997 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n",
998 current_count));
999
1000 /* Validate number of power states discovered */
1001 if (current_count < 2)
1002 status = -EFAULT;
1003
1004 end:
1005 kfree(buffer.pointer);
1006
1007 return status;
1008 }
1009
1010 static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx)
1011 {
1012
1013 if (!cx->address)
1014 return;
1015
1016 /*
1017 * C2 latency must be less than or equal to 100
1018 * microseconds.
1019 */
1020 else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) {
1021 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1022 "latency too large [%d]\n", cx->latency));
1023 return;
1024 }
1025
1026 /*
1027 * Otherwise we've met all of our C2 requirements.
1028 * Normalize the C2 latency to expidite policy
1029 */
1030 cx->valid = 1;
1031
1032 #ifndef CONFIG_CPU_IDLE
1033 cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency);
1034 #else
1035 cx->latency_ticks = cx->latency;
1036 #endif
1037
1038 return;
1039 }
1040
1041 static void acpi_processor_power_verify_c3(struct acpi_processor *pr,
1042 struct acpi_processor_cx *cx)
1043 {
1044 static int bm_check_flag;
1045
1046
1047 if (!cx->address)
1048 return;
1049
1050 /*
1051 * C3 latency must be less than or equal to 1000
1052 * microseconds.
1053 */
1054 else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) {
1055 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1056 "latency too large [%d]\n", cx->latency));
1057 return;
1058 }
1059
1060 /*
1061 * PIIX4 Erratum #18: We don't support C3 when Type-F (fast)
1062 * DMA transfers are used by any ISA device to avoid livelock.
1063 * Note that we could disable Type-F DMA (as recommended by
1064 * the erratum), but this is known to disrupt certain ISA
1065 * devices thus we take the conservative approach.
1066 */
1067 else if (errata.piix4.fdma) {
1068 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1069 "C3 not supported on PIIX4 with Type-F DMA\n"));
1070 return;
1071 }
1072
1073 /* All the logic here assumes flags.bm_check is same across all CPUs */
1074 if (!bm_check_flag) {
1075 /* Determine whether bm_check is needed based on CPU */
1076 acpi_processor_power_init_bm_check(&(pr->flags), pr->id);
1077 bm_check_flag = pr->flags.bm_check;
1078 } else {
1079 pr->flags.bm_check = bm_check_flag;
1080 }
1081
1082 if (pr->flags.bm_check) {
1083 if (!pr->flags.bm_control) {
1084 if (pr->flags.has_cst != 1) {
1085 /* bus mastering control is necessary */
1086 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1087 "C3 support requires BM control\n"));
1088 return;
1089 } else {
1090 /* Here we enter C3 without bus mastering */
1091 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1092 "C3 support without BM control\n"));
1093 }
1094 }
1095 } else {
1096 /*
1097 * WBINVD should be set in fadt, for C3 state to be
1098 * supported on when bm_check is not required.
1099 */
1100 if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) {
1101 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1102 "Cache invalidation should work properly"
1103 " for C3 to be enabled on SMP systems\n"));
1104 return;
1105 }
1106 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
1107 }
1108
1109 /*
1110 * Otherwise we've met all of our C3 requirements.
1111 * Normalize the C3 latency to expidite policy. Enable
1112 * checking of bus mastering status (bm_check) so we can
1113 * use this in our C3 policy
1114 */
1115 cx->valid = 1;
1116
1117 #ifndef CONFIG_CPU_IDLE
1118 cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency);
1119 #else
1120 cx->latency_ticks = cx->latency;
1121 #endif
1122
1123 return;
1124 }
1125
1126 static int acpi_processor_power_verify(struct acpi_processor *pr)
1127 {
1128 unsigned int i;
1129 unsigned int working = 0;
1130
1131 pr->power.timer_broadcast_on_state = INT_MAX;
1132
1133 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
1134 struct acpi_processor_cx *cx = &pr->power.states[i];
1135
1136 switch (cx->type) {
1137 case ACPI_STATE_C1:
1138 cx->valid = 1;
1139 break;
1140
1141 case ACPI_STATE_C2:
1142 acpi_processor_power_verify_c2(cx);
1143 if (cx->valid)
1144 acpi_timer_check_state(i, pr, cx);
1145 break;
1146
1147 case ACPI_STATE_C3:
1148 acpi_processor_power_verify_c3(pr, cx);
1149 if (cx->valid)
1150 acpi_timer_check_state(i, pr, cx);
1151 break;
1152 }
1153
1154 if (cx->valid)
1155 working++;
1156 }
1157
1158 acpi_propagate_timer_broadcast(pr);
1159
1160 return (working);
1161 }
1162
1163 static int acpi_processor_get_power_info(struct acpi_processor *pr)
1164 {
1165 unsigned int i;
1166 int result;
1167
1168
1169 /* NOTE: the idle thread may not be running while calling
1170 * this function */
1171
1172 /* Zero initialize all the C-states info. */
1173 memset(pr->power.states, 0, sizeof(pr->power.states));
1174
1175 result = acpi_processor_get_power_info_cst(pr);
1176 if (result == -ENODEV)
1177 result = acpi_processor_get_power_info_fadt(pr);
1178
1179 if (result)
1180 return result;
1181
1182 acpi_processor_get_power_info_default(pr);
1183
1184 pr->power.count = acpi_processor_power_verify(pr);
1185
1186 #ifndef CONFIG_CPU_IDLE
1187 /*
1188 * Set Default Policy
1189 * ------------------
1190 * Now that we know which states are supported, set the default
1191 * policy. Note that this policy can be changed dynamically
1192 * (e.g. encourage deeper sleeps to conserve battery life when
1193 * not on AC).
1194 */
1195 result = acpi_processor_set_power_policy(pr);
1196 if (result)
1197 return result;
1198 #endif
1199
1200 /*
1201 * if one state of type C2 or C3 is available, mark this
1202 * CPU as being "idle manageable"
1203 */
1204 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
1205 if (pr->power.states[i].valid) {
1206 pr->power.count = i;
1207 if (pr->power.states[i].type >= ACPI_STATE_C2)
1208 pr->flags.power = 1;
1209 }
1210 }
1211
1212 return 0;
1213 }
1214
1215 static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset)
1216 {
1217 struct acpi_processor *pr = seq->private;
1218 unsigned int i;
1219
1220
1221 if (!pr)
1222 goto end;
1223
1224 seq_printf(seq, "active state: C%zd\n"
1225 "max_cstate: C%d\n"
1226 "bus master activity: %08x\n"
1227 "maximum allowed latency: %d usec\n",
1228 pr->power.state ? pr->power.state - pr->power.states : 0,
1229 max_cstate, (unsigned)pr->power.bm_activity,
1230 pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY));
1231
1232 seq_puts(seq, "states:\n");
1233
1234 for (i = 1; i <= pr->power.count; i++) {
1235 seq_printf(seq, " %cC%d: ",
1236 (&pr->power.states[i] ==
1237 pr->power.state ? '*' : ' '), i);
1238
1239 if (!pr->power.states[i].valid) {
1240 seq_puts(seq, "<not supported>\n");
1241 continue;
1242 }
1243
1244 switch (pr->power.states[i].type) {
1245 case ACPI_STATE_C1:
1246 seq_printf(seq, "type[C1] ");
1247 break;
1248 case ACPI_STATE_C2:
1249 seq_printf(seq, "type[C2] ");
1250 break;
1251 case ACPI_STATE_C3:
1252 seq_printf(seq, "type[C3] ");
1253 break;
1254 default:
1255 seq_printf(seq, "type[--] ");
1256 break;
1257 }
1258
1259 if (pr->power.states[i].promotion.state)
1260 seq_printf(seq, "promotion[C%zd] ",
1261 (pr->power.states[i].promotion.state -
1262 pr->power.states));
1263 else
1264 seq_puts(seq, "promotion[--] ");
1265
1266 if (pr->power.states[i].demotion.state)
1267 seq_printf(seq, "demotion[C%zd] ",
1268 (pr->power.states[i].demotion.state -
1269 pr->power.states));
1270 else
1271 seq_puts(seq, "demotion[--] ");
1272
1273 seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n",
1274 pr->power.states[i].latency,
1275 pr->power.states[i].usage,
1276 (unsigned long long)pr->power.states[i].time);
1277 }
1278
1279 end:
1280 return 0;
1281 }
1282
1283 static int acpi_processor_power_open_fs(struct inode *inode, struct file *file)
1284 {
1285 return single_open(file, acpi_processor_power_seq_show,
1286 PDE(inode)->data);
1287 }
1288
1289 static const struct file_operations acpi_processor_power_fops = {
1290 .open = acpi_processor_power_open_fs,
1291 .read = seq_read,
1292 .llseek = seq_lseek,
1293 .release = single_release,
1294 };
1295
1296 #ifndef CONFIG_CPU_IDLE
1297
1298 int acpi_processor_cst_has_changed(struct acpi_processor *pr)
1299 {
1300 int result = 0;
1301
1302
1303 if (!pr)
1304 return -EINVAL;
1305
1306 if (nocst) {
1307 return -ENODEV;
1308 }
1309
1310 if (!pr->flags.power_setup_done)
1311 return -ENODEV;
1312
1313 /* Fall back to the default idle loop */
1314 pm_idle = pm_idle_save;
1315 synchronize_sched(); /* Relies on interrupts forcing exit from idle. */
1316
1317 pr->flags.power = 0;
1318 result = acpi_processor_get_power_info(pr);
1319 if ((pr->flags.power == 1) && (pr->flags.power_setup_done))
1320 pm_idle = acpi_processor_idle;
1321
1322 return result;
1323 }
1324
1325 #ifdef CONFIG_SMP
1326 static void smp_callback(void *v)
1327 {
1328 /* we already woke the CPU up, nothing more to do */
1329 }
1330
1331 /*
1332 * This function gets called when a part of the kernel has a new latency
1333 * requirement. This means we need to get all processors out of their C-state,
1334 * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that
1335 * wakes them all right up.
1336 */
1337 static int acpi_processor_latency_notify(struct notifier_block *b,
1338 unsigned long l, void *v)
1339 {
1340 smp_call_function(smp_callback, NULL, 0, 1);
1341 return NOTIFY_OK;
1342 }
1343
1344 static struct notifier_block acpi_processor_latency_notifier = {
1345 .notifier_call = acpi_processor_latency_notify,
1346 };
1347
1348 #endif
1349
1350 #else /* CONFIG_CPU_IDLE */
1351
1352 /**
1353 * acpi_idle_bm_check - checks if bus master activity was detected
1354 */
1355 static int acpi_idle_bm_check(void)
1356 {
1357 u32 bm_status = 0;
1358
1359 acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
1360 if (bm_status)
1361 acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
1362 /*
1363 * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
1364 * the true state of bus mastering activity; forcing us to
1365 * manually check the BMIDEA bit of each IDE channel.
1366 */
1367 else if (errata.piix4.bmisx) {
1368 if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01)
1369 || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01))
1370 bm_status = 1;
1371 }
1372 return bm_status;
1373 }
1374
1375 /**
1376 * acpi_idle_update_bm_rld - updates the BM_RLD bit depending on target state
1377 * @pr: the processor
1378 * @target: the new target state
1379 */
1380 static inline void acpi_idle_update_bm_rld(struct acpi_processor *pr,
1381 struct acpi_processor_cx *target)
1382 {
1383 if (pr->flags.bm_rld_set && target->type != ACPI_STATE_C3) {
1384 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
1385 pr->flags.bm_rld_set = 0;
1386 }
1387
1388 if (!pr->flags.bm_rld_set && target->type == ACPI_STATE_C3) {
1389 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1);
1390 pr->flags.bm_rld_set = 1;
1391 }
1392 }
1393
1394 /**
1395 * acpi_idle_do_entry - a helper function that does C2 and C3 type entry
1396 * @cx: cstate data
1397 *
1398 * Caller disables interrupt before call and enables interrupt after return.
1399 */
1400 static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx)
1401 {
1402 if (cx->entry_method == ACPI_CSTATE_FFH) {
1403 /* Call into architectural FFH based C-state */
1404 acpi_processor_ffh_cstate_enter(cx);
1405 } else if (cx->entry_method == ACPI_CSTATE_HALT) {
1406 acpi_safe_halt();
1407 } else {
1408 int unused;
1409 /* IO port based C-state */
1410 inb(cx->address);
1411 /* Dummy wait op - must do something useless after P_LVL2 read
1412 because chipsets cannot guarantee that STPCLK# signal
1413 gets asserted in time to freeze execution properly. */
1414 unused = inl(acpi_gbl_FADT.xpm_timer_block.address);
1415 }
1416 }
1417
1418 /**
1419 * acpi_idle_enter_c1 - enters an ACPI C1 state-type
1420 * @dev: the target CPU
1421 * @state: the state data
1422 *
1423 * This is equivalent to the HALT instruction.
1424 */
1425 static int acpi_idle_enter_c1(struct cpuidle_device *dev,
1426 struct cpuidle_state *state)
1427 {
1428 u32 t1, t2;
1429 struct acpi_processor *pr;
1430 struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
1431
1432 pr = processors[smp_processor_id()];
1433
1434 if (unlikely(!pr))
1435 return 0;
1436
1437 local_irq_disable();
1438
1439 /* Do not access any ACPI IO ports in suspend path */
1440 if (acpi_idle_suspend) {
1441 acpi_safe_halt();
1442 local_irq_enable();
1443 return 0;
1444 }
1445
1446 if (pr->flags.bm_check)
1447 acpi_idle_update_bm_rld(pr, cx);
1448
1449 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1450 acpi_idle_do_entry(cx);
1451 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1452
1453 local_irq_enable();
1454 cx->usage++;
1455
1456 return ticks_elapsed_in_us(t1, t2);
1457 }
1458
1459 /**
1460 * acpi_idle_enter_simple - enters an ACPI state without BM handling
1461 * @dev: the target CPU
1462 * @state: the state data
1463 */
1464 static int acpi_idle_enter_simple(struct cpuidle_device *dev,
1465 struct cpuidle_state *state)
1466 {
1467 struct acpi_processor *pr;
1468 struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
1469 u32 t1, t2;
1470 int sleep_ticks = 0;
1471
1472 pr = processors[smp_processor_id()];
1473
1474 if (unlikely(!pr))
1475 return 0;
1476
1477 if (acpi_idle_suspend)
1478 return(acpi_idle_enter_c1(dev, state));
1479
1480 local_irq_disable();
1481 current_thread_info()->status &= ~TS_POLLING;
1482 /*
1483 * TS_POLLING-cleared state must be visible before we test
1484 * NEED_RESCHED:
1485 */
1486 smp_mb();
1487
1488 if (unlikely(need_resched() || need_resched_delayed())) {
1489 current_thread_info()->status |= TS_POLLING;
1490 local_irq_enable();
1491 return 0;
1492 }
1493
1494 /*
1495 * Must be done before busmaster disable as we might need to
1496 * access HPET !
1497 */
1498 acpi_state_timer_broadcast(pr, cx, 1);
1499
1500 if (pr->flags.bm_check)
1501 acpi_idle_update_bm_rld(pr, cx);
1502
1503 if (cx->type == ACPI_STATE_C3)
1504 ACPI_FLUSH_CPU_CACHE();
1505
1506 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1507 /* Tell the scheduler that we are going deep-idle: */
1508 sched_clock_idle_sleep_event();
1509 acpi_idle_do_entry(cx);
1510 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1511
1512 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
1513 /* TSC could halt in idle, so notify users */
1514 if (tsc_halts_in_c(cx->type))
1515 mark_tsc_unstable("TSC halts in idle");;
1516 #endif
1517 sleep_ticks = ticks_elapsed(t1, t2);
1518
1519 /* Tell the scheduler how much we idled: */
1520 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
1521
1522 local_irq_enable();
1523 current_thread_info()->status |= TS_POLLING;
1524
1525 cx->usage++;
1526
1527 acpi_state_timer_broadcast(pr, cx, 0);
1528 cx->time += sleep_ticks;
1529 return ticks_elapsed_in_us(t1, t2);
1530 }
1531
1532 static int c3_cpu_count;
1533 static DEFINE_RAW_SPINLOCK(c3_lock);
1534
1535 /**
1536 * acpi_idle_enter_bm - enters C3 with proper BM handling
1537 * @dev: the target CPU
1538 * @state: the state data
1539 *
1540 * If BM is detected, the deepest non-C3 idle state is entered instead.
1541 */
1542 static int acpi_idle_enter_bm(struct cpuidle_device *dev,
1543 struct cpuidle_state *state)
1544 {
1545 struct acpi_processor *pr;
1546 struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
1547 u32 t1, t2;
1548 int sleep_ticks = 0;
1549
1550 pr = processors[smp_processor_id()];
1551
1552 if (unlikely(!pr))
1553 return 0;
1554
1555 if (acpi_idle_suspend)
1556 return(acpi_idle_enter_c1(dev, state));
1557
1558 if (acpi_idle_bm_check()) {
1559 if (dev->safe_state) {
1560 return dev->safe_state->enter(dev, dev->safe_state);
1561 } else {
1562 local_irq_disable();
1563 acpi_safe_halt();
1564 local_irq_enable();
1565 return 0;
1566 }
1567 }
1568
1569 local_irq_disable();
1570 current_thread_info()->status &= ~TS_POLLING;
1571 /*
1572 * TS_POLLING-cleared state must be visible before we test
1573 * NEED_RESCHED:
1574 */
1575 smp_mb();
1576
1577 if (unlikely(need_resched() || need_resched_delayed())) {
1578 current_thread_info()->status |= TS_POLLING;
1579 local_irq_enable();
1580 return 0;
1581 }
1582
1583 acpi_unlazy_tlb(smp_processor_id());
1584
1585 /* Tell the scheduler that we are going deep-idle: */
1586 sched_clock_idle_sleep_event();
1587 /*
1588 * Must be done before busmaster disable as we might need to
1589 * access HPET !
1590 */
1591 acpi_state_timer_broadcast(pr, cx, 1);
1592
1593 acpi_idle_update_bm_rld(pr, cx);
1594
1595 /*
1596 * disable bus master
1597 * bm_check implies we need ARB_DIS
1598 * !bm_check implies we need cache flush
1599 * bm_control implies whether we can do ARB_DIS
1600 *
1601 * That leaves a case where bm_check is set and bm_control is
1602 * not set. In that case we cannot do much, we enter C3
1603 * without doing anything.
1604 */
1605 if (pr->flags.bm_check && pr->flags.bm_control) {
1606 spin_lock(&c3_lock);
1607 c3_cpu_count++;
1608 /* Disable bus master arbitration when all CPUs are in C3 */
1609 if (c3_cpu_count == num_online_cpus())
1610 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
1611 spin_unlock(&c3_lock);
1612 } else if (!pr->flags.bm_check) {
1613 ACPI_FLUSH_CPU_CACHE();
1614 }
1615
1616 t1 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1617 acpi_idle_do_entry(cx);
1618 t2 = inl(acpi_gbl_FADT.xpm_timer_block.address);
1619
1620 /* Re-enable bus master arbitration */
1621 if (pr->flags.bm_check && pr->flags.bm_control) {
1622 spin_lock(&c3_lock);
1623 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
1624 c3_cpu_count--;
1625 spin_unlock(&c3_lock);
1626 }
1627
1628 #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86)
1629 /* TSC could halt in idle, so notify users */
1630 if (tsc_halts_in_c(ACPI_STATE_C3))
1631 mark_tsc_unstable("TSC halts in idle");
1632 #endif
1633 sleep_ticks = ticks_elapsed(t1, t2);
1634 /* Tell the scheduler how much we idled: */
1635 sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS);
1636
1637 local_irq_enable();
1638 current_thread_info()->status |= TS_POLLING;
1639
1640 cx->usage++;
1641
1642 acpi_state_timer_broadcast(pr, cx, 0);
1643 cx->time += sleep_ticks;
1644 return ticks_elapsed_in_us(t1, t2);
1645 }
1646
1647 struct cpuidle_driver acpi_idle_driver = {
1648 .name = "acpi_idle",
1649 .owner = THIS_MODULE,
1650 };
1651
1652 /**
1653 * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE
1654 * @pr: the ACPI processor
1655 */
1656 static int acpi_processor_setup_cpuidle(struct acpi_processor *pr)
1657 {
1658 int i, count = CPUIDLE_DRIVER_STATE_START;
1659 struct acpi_processor_cx *cx;
1660 struct cpuidle_state *state;
1661 struct cpuidle_device *dev = &pr->power.dev;
1662
1663 if (!pr->flags.power_setup_done)
1664 return -EINVAL;
1665
1666 if (pr->flags.power == 0) {
1667 return -EINVAL;
1668 }
1669
1670 for (i = 0; i < CPUIDLE_STATE_MAX; i++) {
1671 dev->states[i].name[0] = '\0';
1672 dev->states[i].desc[0] = '\0';
1673 }
1674
1675 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) {
1676 cx = &pr->power.states[i];
1677 state = &dev->states[count];
1678
1679 if (!cx->valid)
1680 continue;
1681
1682 #ifdef CONFIG_HOTPLUG_CPU
1683 if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) &&
1684 !pr->flags.has_cst &&
1685 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
1686 continue;
1687 #endif
1688 cpuidle_set_statedata(state, cx);
1689
1690 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i);
1691 strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
1692 state->exit_latency = cx->latency;
1693 state->target_residency = cx->latency * latency_factor;
1694 state->power_usage = cx->power;
1695
1696 state->flags = 0;
1697 switch (cx->type) {
1698 case ACPI_STATE_C1:
1699 state->flags |= CPUIDLE_FLAG_SHALLOW;
1700 if (cx->entry_method == ACPI_CSTATE_FFH)
1701 state->flags |= CPUIDLE_FLAG_TIME_VALID;
1702
1703 state->enter = acpi_idle_enter_c1;
1704 dev->safe_state = state;
1705 break;
1706
1707 case ACPI_STATE_C2:
1708 state->flags |= CPUIDLE_FLAG_BALANCED;
1709 state->flags |= CPUIDLE_FLAG_TIME_VALID;
1710 state->enter = acpi_idle_enter_simple;
1711 dev->safe_state = state;
1712 break;
1713
1714 case ACPI_STATE_C3:
1715 state->flags |= CPUIDLE_FLAG_DEEP;
1716 state->flags |= CPUIDLE_FLAG_TIME_VALID;
1717 state->flags |= CPUIDLE_FLAG_CHECK_BM;
1718 state->enter = pr->flags.bm_check ?
1719 acpi_idle_enter_bm :
1720 acpi_idle_enter_simple;
1721 break;
1722 }
1723
1724 count++;
1725 if (count == CPUIDLE_STATE_MAX)
1726 break;
1727 }
1728
1729 dev->state_count = count;
1730
1731 if (!count)
1732 return -EINVAL;
1733
1734 return 0;
1735 }
1736
1737 int acpi_processor_cst_has_changed(struct acpi_processor *pr)
1738 {
1739 int ret;
1740
1741 if (!pr)
1742 return -EINVAL;
1743
1744 if (nocst) {
1745 return -ENODEV;
1746 }
1747
1748 if (!pr->flags.power_setup_done)
1749 return -ENODEV;
1750
1751 cpuidle_pause_and_lock();
1752 cpuidle_disable_device(&pr->power.dev);
1753 acpi_processor_get_power_info(pr);
1754 acpi_processor_setup_cpuidle(pr);
1755 ret = cpuidle_enable_device(&pr->power.dev);
1756 cpuidle_resume_and_unlock();
1757
1758 return ret;
1759 }
1760
1761 #endif /* CONFIG_CPU_IDLE */
1762
1763 int __cpuinit acpi_processor_power_init(struct acpi_processor *pr,
1764 struct acpi_device *device)
1765 {
1766 acpi_status status = 0;
1767 static int first_run;
1768 struct proc_dir_entry *entry = NULL;
1769 unsigned int i;
1770
1771
1772 if (!first_run) {
1773 dmi_check_system(processor_power_dmi_table);
1774 max_cstate = acpi_processor_cstate_check(max_cstate);
1775 if (max_cstate < ACPI_C_STATES_MAX)
1776 printk(KERN_NOTICE
1777 "ACPI: processor limited to max C-state %d\n",
1778 max_cstate);
1779 first_run++;
1780 #if !defined(CONFIG_CPU_IDLE) && defined(CONFIG_SMP)
1781 pm_qos_add_notifier(PM_QOS_CPU_DMA_LATENCY,
1782 &acpi_processor_latency_notifier);
1783 #endif
1784 }
1785
1786 if (!pr)
1787 return -EINVAL;
1788
1789 if (acpi_gbl_FADT.cst_control && !nocst) {
1790 status =
1791 acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8);
1792 if (ACPI_FAILURE(status)) {
1793 ACPI_EXCEPTION((AE_INFO, status,
1794 "Notifying BIOS of _CST ability failed"));
1795 }
1796 }
1797
1798 acpi_processor_get_power_info(pr);
1799 pr->flags.power_setup_done = 1;
1800
1801 /*
1802 * Install the idle handler if processor power management is supported.
1803 * Note that we use previously set idle handler will be used on
1804 * platforms that only support C1.
1805 */
1806 if ((pr->flags.power) && (!boot_option_idle_override)) {
1807 #ifdef CONFIG_CPU_IDLE
1808 acpi_processor_setup_cpuidle(pr);
1809 pr->power.dev.cpu = pr->id;
1810 if (cpuidle_register_device(&pr->power.dev))
1811 return -EIO;
1812 #endif
1813
1814 printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id);
1815 for (i = 1; i <= pr->power.count; i++)
1816 if (pr->power.states[i].valid)
1817 printk(" C%d[C%d]", i,
1818 pr->power.states[i].type);
1819 printk(")\n");
1820
1821 #ifndef CONFIG_CPU_IDLE
1822 if (pr->id == 0) {
1823 pm_idle_save = pm_idle;
1824 pm_idle = acpi_processor_idle;
1825 }
1826 #endif
1827 }
1828
1829 /* 'power' [R] */
1830 entry = create_proc_entry(ACPI_PROCESSOR_FILE_POWER,
1831 S_IRUGO, acpi_device_dir(device));
1832 if (!entry)
1833 return -EIO;
1834 else {
1835 entry->proc_fops = &acpi_processor_power_fops;
1836 entry->data = acpi_driver_data(device);
1837 entry->owner = THIS_MODULE;
1838 }
1839
1840 return 0;
1841 }
1842
1843 int acpi_processor_power_exit(struct acpi_processor *pr,
1844 struct acpi_device *device)
1845 {
1846 #ifdef CONFIG_CPU_IDLE
1847 if ((pr->flags.power) && (!boot_option_idle_override))
1848 cpuidle_unregister_device(&pr->power.dev);
1849 #endif
1850 pr->flags.power_setup_done = 0;
1851
1852 if (acpi_device_dir(device))
1853 remove_proc_entry(ACPI_PROCESSOR_FILE_POWER,
1854 acpi_device_dir(device));
1855
1856 #ifndef CONFIG_CPU_IDLE
1857
1858 /* Unregister the idle handler when processor #0 is removed. */
1859 if (pr->id == 0) {
1860 pm_idle = pm_idle_save;
1861
1862 /*
1863 * We are about to unload the current idle thread pm callback
1864 * (pm_idle), Wait for all processors to update cached/local
1865 * copies of pm_idle before proceeding.
1866 */
1867 cpu_idle_wait();
1868 #ifdef CONFIG_SMP
1869 pm_qos_remove_notifier(PM_QOS_CPU_DMA_LATENCY,
1870 &acpi_processor_latency_notifier);
1871 #endif
1872 }
1873 #endif
1874
1875 return 0;
1876 }
1877
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