1 /*
2 * Low-Level PCI Access for i386 machines.
3 *
4 * (c) 1999 Martin Mares <mj@ucw.cz>
5 */
6
7 #undef DEBUG
8
9 #ifdef DEBUG
10 #define DBG(x...) printk(x)
11 #else
12 #define DBG(x...)
13 #endif
14
15 #define PCI_PROBE_BIOS 0x0001
16 #define PCI_PROBE_CONF1 0x0002
17 #define PCI_PROBE_CONF2 0x0004
18 #define PCI_PROBE_MMCONF 0x0008
19 #define PCI_PROBE_MASK 0x000f
20 #define PCI_PROBE_NOEARLY 0x0010
21
22 #define PCI_NO_SORT 0x0100
23 #define PCI_BIOS_SORT 0x0200
24 #define PCI_NO_CHECKS 0x0400
25 #define PCI_USE_PIRQ_MASK 0x0800
26 #define PCI_ASSIGN_ROMS 0x1000
27 #define PCI_BIOS_IRQ_SCAN 0x2000
28 #define PCI_ASSIGN_ALL_BUSSES 0x4000
29 #define PCI_CAN_SKIP_ISA_ALIGN 0x8000
30 #define PCI_USE__CRS 0x10000
31
32 extern unsigned int pci_probe;
33 extern unsigned long pirq_table_addr;
34
35 enum pci_bf_sort_state {
36 pci_bf_sort_default,
37 pci_force_nobf,
38 pci_force_bf,
39 pci_dmi_bf,
40 };
41
42 /* pci-i386.c */
43
44 extern unsigned int pcibios_max_latency;
45
46 void pcibios_resource_survey(void);
47 int pcibios_enable_resources(struct pci_dev *, int);
48
49 /* pci-pc.c */
50
51 extern int pcibios_last_bus;
52 extern struct pci_bus *pci_root_bus;
53 extern struct pci_ops pci_root_ops;
54
55 /* pci-irq.c */
56
57 struct irq_info {
58 u8 bus, devfn; /* Bus, device and function */
59 struct {
60 u8 link; /* IRQ line ID, chipset dependent, 0=not routed */
61 u16 bitmap; /* Available IRQs */
62 } __attribute__((packed)) irq[4];
63 u8 slot; /* Slot number, 0=onboard */
64 u8 rfu;
65 } __attribute__((packed));
66
67 struct irq_routing_table {
68 u32 signature; /* PIRQ_SIGNATURE should be here */
69 u16 version; /* PIRQ_VERSION */
70 u16 size; /* Table size in bytes */
71 u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
72 u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
73 u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */
74 u32 miniport_data; /* Crap */
75 u8 rfu[11];
76 u8 checksum; /* Modulo 256 checksum must give zero */
77 struct irq_info slots[0];
78 } __attribute__((packed));
79
80 extern unsigned int pcibios_irq_mask;
81
82 extern int pcibios_scanned;
83 extern spinlock_t pci_config_lock;
84
85 extern int (*pcibios_enable_irq)(struct pci_dev *dev);
86 extern void (*pcibios_disable_irq)(struct pci_dev *dev);
87
88 struct pci_raw_ops {
89 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
90 int reg, int len, u32 *val);
91 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
92 int reg, int len, u32 val);
93 };
94
95 extern struct pci_raw_ops *raw_pci_ops;
96 extern struct pci_raw_ops *raw_pci_ext_ops;
97
98 extern struct pci_raw_ops pci_direct_conf1;
99
100 extern int pci_direct_probe(void);
101 extern void pci_direct_init(int type);
102 extern void pci_pcbios_init(void);
103 extern void pci_mmcfg_init(int type);
104 extern void pcibios_sort(void);
105
106 /* pci-mmconfig.c */
107
108 extern int __init pci_mmcfg_arch_init(void);
109
110 /*
111 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
112 * on their northbrige except through the * %eax register. As such, you MUST
113 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
114 * accessor functions.
115 * In fact just use pci_config_*, nothing else please.
116 */
117 static inline unsigned char mmio_config_readb(void __iomem *pos)
118 {
119 u8 val;
120 asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
121 return val;
122 }
123
124 static inline unsigned short mmio_config_readw(void __iomem *pos)
125 {
126 u16 val;
127 asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
128 return val;
129 }
130
131 static inline unsigned int mmio_config_readl(void __iomem *pos)
132 {
133 u32 val;
134 asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
135 return val;
136 }
137
138 static inline void mmio_config_writeb(void __iomem *pos, u8 val)
139 {
140 asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory");
141 }
142
143 static inline void mmio_config_writew(void __iomem *pos, u16 val)
144 {
145 asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory");
146 }
147
148 static inline void mmio_config_writel(void __iomem *pos, u32 val)
149 {
150 asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory");
151 }
152
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