1 /*
2 * Low-Level PCI Access for i386 machines
3 *
4 * Copyright 1993, 1994 Drew Eckhardt
5 * Visionary Computing
6 * (Unix and Linux consulting and custom programming)
7 * Drew@Colorado.EDU
8 * +1 (303) 786-7975
9 *
10 * Drew's work was sponsored by:
11 * iX Multiuser Multitasking Magazine
12 * Hannover, Germany
13 * hm@ix.de
14 *
15 * Copyright 1997--2000 Martin Mares <mj@ucw.cz>
16 *
17 * For more information, please consult the following manuals (look at
18 * http://www.pcisig.com/ for how to get them):
19 *
20 * PCI BIOS Specification
21 * PCI Local Bus Specification
22 * PCI to PCI Bridge Specification
23 * PCI System Design Guide
24 *
25 */
26
27 #include <linux/types.h>
28 #include <linux/kernel.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/errno.h>
33 #include <linux/bootmem.h>
34
35 #include <asm/pat.h>
36 #include <asm/e820.h>
37 #include <asm/pci_x86.h>
38 #include <asm/io_apic.h>
39
40
41 static int
42 skip_isa_ioresource_align(struct pci_dev *dev) {
43
44 if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
45 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
46 return 1;
47 return 0;
48 }
49
50 /*
51 * We need to avoid collisions with `mirrored' VGA ports
52 * and other strange ISA hardware, so we always want the
53 * addresses to be allocated in the 0x000-0x0ff region
54 * modulo 0x400.
55 *
56 * Why? Because some silly external IO cards only decode
57 * the low 10 bits of the IO address. The 0x00-0xff region
58 * is reserved for motherboard devices that decode all 16
59 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
60 * but we want to try to avoid allocating at 0x2900-0x2bff
61 * which might have be mirrored at 0x0100-0x03ff..
62 */
63 void
64 pcibios_align_resource(void *data, struct resource *res,
65 resource_size_t size, resource_size_t align)
66 {
67 struct pci_dev *dev = data;
68
69 if (res->flags & IORESOURCE_IO) {
70 resource_size_t start = res->start;
71
72 if (skip_isa_ioresource_align(dev))
73 return;
74 if (start & 0x300) {
75 start = (start + 0x3ff) & ~0x3ff;
76 res->start = start;
77 }
78 }
79 }
80 EXPORT_SYMBOL(pcibios_align_resource);
81
82 /*
83 * Handle resources of PCI devices. If the world were perfect, we could
84 * just allocate all the resource regions and do nothing more. It isn't.
85 * On the other hand, we cannot just re-allocate all devices, as it would
86 * require us to know lots of host bridge internals. So we attempt to
87 * keep as much of the original configuration as possible, but tweak it
88 * when it's found to be wrong.
89 *
90 * Known BIOS problems we have to work around:
91 * - I/O or memory regions not configured
92 * - regions configured, but not enabled in the command register
93 * - bogus I/O addresses above 64K used
94 * - expansion ROMs left enabled (this may sound harmless, but given
95 * the fact the PCI specs explicitly allow address decoders to be
96 * shared between expansion ROMs and other resource regions, it's
97 * at least dangerous)
98 *
99 * Our solution:
100 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
101 * This gives us fixed barriers on where we can allocate.
102 * (2) Allocate resources for all enabled devices. If there is
103 * a collision, just mark the resource as unallocated. Also
104 * disable expansion ROMs during this step.
105 * (3) Try to allocate resources for disabled devices. If the
106 * resources were assigned correctly, everything goes well,
107 * if they weren't, they won't disturb allocation of other
108 * resources.
109 * (4) Assign new addresses to resources which were either
110 * not configured at all or misconfigured. If explicitly
111 * requested by the user, configure expansion ROM address
112 * as well.
113 */
114
115 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
116 {
117 struct pci_bus *bus;
118 struct pci_dev *dev;
119 int idx;
120 struct resource *r;
121
122 /* Depth-First Search on bus tree */
123 list_for_each_entry(bus, bus_list, node) {
124 if ((dev = bus->self)) {
125 for (idx = PCI_BRIDGE_RESOURCES;
126 idx < PCI_NUM_RESOURCES; idx++) {
127 r = &dev->resource[idx];
128 if (!r->flags)
129 continue;
130 if (!r->start ||
131 pci_claim_resource(dev, idx) < 0) {
132 dev_info(&dev->dev, "BAR %d: can't allocate resource\n", idx);
133 /*
134 * Something is wrong with the region.
135 * Invalidate the resource to prevent
136 * child resource allocations in this
137 * range.
138 */
139 r->flags = 0;
140 }
141 }
142 }
143 pcibios_allocate_bus_resources(&bus->children);
144 }
145 }
146
147 static void __init pcibios_allocate_resources(int pass)
148 {
149 struct pci_dev *dev = NULL;
150 int idx, disabled;
151 u16 command;
152 struct resource *r;
153
154 for_each_pci_dev(dev) {
155 pci_read_config_word(dev, PCI_COMMAND, &command);
156 for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
157 r = &dev->resource[idx];
158 if (r->parent) /* Already allocated */
159 continue;
160 if (!r->start) /* Address not assigned at all */
161 continue;
162 if (r->flags & IORESOURCE_IO)
163 disabled = !(command & PCI_COMMAND_IO);
164 else
165 disabled = !(command & PCI_COMMAND_MEMORY);
166 if (pass == disabled) {
167 dev_dbg(&dev->dev, "resource %#08llx-%#08llx (f=%lx, d=%d, p=%d)\n",
168 (unsigned long long) r->start,
169 (unsigned long long) r->end,
170 r->flags, disabled, pass);
171 if (pci_claim_resource(dev, idx) < 0) {
172 dev_info(&dev->dev, "BAR %d: can't allocate resource\n", idx);
173 /* We'll assign a new address later */
174 r->end -= r->start;
175 r->start = 0;
176 }
177 }
178 }
179 if (!pass) {
180 r = &dev->resource[PCI_ROM_RESOURCE];
181 if (r->flags & IORESOURCE_ROM_ENABLE) {
182 /* Turn the ROM off, leave the resource region,
183 * but keep it unregistered. */
184 u32 reg;
185 dev_dbg(&dev->dev, "disabling ROM\n");
186 r->flags &= ~IORESOURCE_ROM_ENABLE;
187 pci_read_config_dword(dev,
188 dev->rom_base_reg, ®);
189 pci_write_config_dword(dev, dev->rom_base_reg,
190 reg & ~PCI_ROM_ADDRESS_ENABLE);
191 }
192 }
193 }
194 }
195
196 static int __init pcibios_assign_resources(void)
197 {
198 struct pci_dev *dev = NULL;
199 struct resource *r;
200
201 if (!(pci_probe & PCI_ASSIGN_ROMS)) {
202 /*
203 * Try to use BIOS settings for ROMs, otherwise let
204 * pci_assign_unassigned_resources() allocate the new
205 * addresses.
206 */
207 for_each_pci_dev(dev) {
208 r = &dev->resource[PCI_ROM_RESOURCE];
209 if (!r->flags || !r->start)
210 continue;
211 if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) {
212 r->end -= r->start;
213 r->start = 0;
214 }
215 }
216 }
217
218 pci_assign_unassigned_resources();
219
220 return 0;
221 }
222
223 void __init pcibios_resource_survey(void)
224 {
225 DBG("PCI: Allocating resources\n");
226 pcibios_allocate_bus_resources(&pci_root_buses);
227 pcibios_allocate_resources(0);
228 pcibios_allocate_resources(1);
229
230 e820_reserve_resources_late();
231 /*
232 * Insert the IO APIC resources after PCI initialization has
233 * occured to handle IO APICS that are mapped in on a BAR in
234 * PCI space, but before trying to assign unassigned pci res.
235 */
236 ioapic_insert_resources();
237 }
238
239 /**
240 * called in fs_initcall (one below subsys_initcall),
241 * give a chance for motherboard reserve resources
242 */
243 fs_initcall(pcibios_assign_resources);
244
245 void __weak x86_pci_root_bus_res_quirks(struct pci_bus *b)
246 {
247 }
248
249 /*
250 * If we set up a device for bus mastering, we need to check the latency
251 * timer as certain crappy BIOSes forget to set it properly.
252 */
253 unsigned int pcibios_max_latency = 255;
254
255 void pcibios_set_master(struct pci_dev *dev)
256 {
257 u8 lat;
258 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
259 if (lat < 16)
260 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
261 else if (lat > pcibios_max_latency)
262 lat = pcibios_max_latency;
263 else
264 return;
265 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
266 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
267 }
268
269 static struct vm_operations_struct pci_mmap_ops = {
270 .access = generic_access_phys,
271 };
272
273 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
274 enum pci_mmap_state mmap_state, int write_combine)
275 {
276 unsigned long prot;
277
278 /* I/O space cannot be accessed via normal processor loads and
279 * stores on this platform.
280 */
281 if (mmap_state == pci_mmap_io)
282 return -EINVAL;
283
284 prot = pgprot_val(vma->vm_page_prot);
285
286 /*
287 * Return error if pat is not enabled and write_combine is requested.
288 * Caller can followup with UC MINUS request and add a WC mtrr if there
289 * is a free mtrr slot.
290 */
291 if (!pat_enabled && write_combine)
292 return -EINVAL;
293
294 if (pat_enabled && write_combine)
295 prot |= _PAGE_CACHE_WC;
296 else if (pat_enabled || boot_cpu_data.x86 > 3)
297 /*
298 * ioremap() and ioremap_nocache() defaults to UC MINUS for now.
299 * To avoid attribute conflicts, request UC MINUS here
300 * aswell.
301 */
302 prot |= _PAGE_CACHE_UC_MINUS;
303
304 vma->vm_page_prot = __pgprot(prot);
305
306 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
307 vma->vm_end - vma->vm_start,
308 vma->vm_page_prot))
309 return -EAGAIN;
310
311 vma->vm_ops = &pci_mmap_ops;
312
313 return 0;
314 }
315
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