1 /*
2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
4 */
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
9 #include <linux/slab.h>
10 #include <linux/mm.h>
11 #include <linux/interrupt.h>
12 #include <linux/seq_file.h>
13 #include <linux/debugfs.h>
14 #include <linux/pfn.h>
15
16 #include <asm/e820.h>
17 #include <asm/processor.h>
18 #include <asm/tlbflush.h>
19 #include <asm/sections.h>
20 #include <asm/setup.h>
21 #include <asm/uaccess.h>
22 #include <asm/pgalloc.h>
23 #include <asm/proto.h>
24 #include <asm/pat.h>
25
26 /*
27 * The current flushing context - we pass it instead of 5 arguments:
28 */
29 struct cpa_data {
30 unsigned long *vaddr;
31 pgprot_t mask_set;
32 pgprot_t mask_clr;
33 int numpages;
34 int flags;
35 unsigned long pfn;
36 unsigned force_split : 1;
37 int curpage;
38 struct page **pages;
39 };
40
41 /*
42 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
43 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
44 * entries change the page attribute in parallel to some other cpu
45 * splitting a large page entry along with changing the attribute.
46 */
47 static DEFINE_SPINLOCK(cpa_lock);
48
49 #define CPA_FLUSHTLB 1
50 #define CPA_ARRAY 2
51 #define CPA_PAGES_ARRAY 4
52
53 #ifdef CONFIG_PROC_FS
54 static unsigned long direct_pages_count[PG_LEVEL_NUM];
55
56 void update_page_count(int level, unsigned long pages)
57 {
58 unsigned long flags;
59
60 /* Protect against CPA */
61 spin_lock_irqsave(&pgd_lock, flags);
62 direct_pages_count[level] += pages;
63 spin_unlock_irqrestore(&pgd_lock, flags);
64 }
65
66 static void split_page_count(int level)
67 {
68 direct_pages_count[level]--;
69 direct_pages_count[level - 1] += PTRS_PER_PTE;
70 }
71
72 void arch_report_meminfo(struct seq_file *m)
73 {
74 seq_printf(m, "DirectMap4k: %8lu kB\n",
75 direct_pages_count[PG_LEVEL_4K] << 2);
76 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
77 seq_printf(m, "DirectMap2M: %8lu kB\n",
78 direct_pages_count[PG_LEVEL_2M] << 11);
79 #else
80 seq_printf(m, "DirectMap4M: %8lu kB\n",
81 direct_pages_count[PG_LEVEL_2M] << 12);
82 #endif
83 #ifdef CONFIG_X86_64
84 if (direct_gbpages)
85 seq_printf(m, "DirectMap1G: %8lu kB\n",
86 direct_pages_count[PG_LEVEL_1G] << 20);
87 #endif
88 }
89 #else
90 static inline void split_page_count(int level) { }
91 #endif
92
93 #ifdef CONFIG_X86_64
94
95 static inline unsigned long highmap_start_pfn(void)
96 {
97 return __pa(_text) >> PAGE_SHIFT;
98 }
99
100 static inline unsigned long highmap_end_pfn(void)
101 {
102 return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT;
103 }
104
105 #endif
106
107 #ifdef CONFIG_DEBUG_PAGEALLOC
108 # define debug_pagealloc 1
109 #else
110 # define debug_pagealloc 0
111 #endif
112
113 static inline int
114 within(unsigned long addr, unsigned long start, unsigned long end)
115 {
116 return addr >= start && addr < end;
117 }
118
119 /*
120 * Flushing functions
121 */
122
123 /**
124 * clflush_cache_range - flush a cache range with clflush
125 * @addr: virtual start address
126 * @size: number of bytes to flush
127 *
128 * clflush is an unordered instruction which needs fencing with mfence
129 * to avoid ordering issues.
130 */
131 void clflush_cache_range(void *vaddr, unsigned int size)
132 {
133 void *vend = vaddr + size - 1;
134
135 mb();
136
137 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
138 clflush(vaddr);
139 /*
140 * Flush any possible final partial cacheline:
141 */
142 clflush(vend);
143
144 mb();
145 }
146 EXPORT_SYMBOL_GPL(clflush_cache_range);
147
148 static void __cpa_flush_all(void *arg)
149 {
150 unsigned long cache = (unsigned long)arg;
151
152 /*
153 * Flush all to work around Errata in early athlons regarding
154 * large page flushing.
155 */
156 __flush_tlb_all();
157
158 if (cache && boot_cpu_data.x86 >= 4)
159 wbinvd();
160 }
161
162 static void cpa_flush_all(unsigned long cache)
163 {
164 BUG_ON(irqs_disabled());
165
166 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
167 }
168
169 static void __cpa_flush_range(void *arg)
170 {
171 /*
172 * We could optimize that further and do individual per page
173 * tlb invalidates for a low number of pages. Caveat: we must
174 * flush the high aliases on 64bit as well.
175 */
176 __flush_tlb_all();
177 }
178
179 static void cpa_flush_range(unsigned long start, int numpages, int cache)
180 {
181 unsigned int i, level;
182 unsigned long addr;
183
184 BUG_ON(irqs_disabled());
185 WARN_ON(PAGE_ALIGN(start) != start);
186
187 on_each_cpu(__cpa_flush_range, NULL, 1);
188
189 if (!cache)
190 return;
191
192 /*
193 * We only need to flush on one CPU,
194 * clflush is a MESI-coherent instruction that
195 * will cause all other CPUs to flush the same
196 * cachelines:
197 */
198 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
199 pte_t *pte = lookup_address(addr, &level);
200
201 /*
202 * Only flush present addresses:
203 */
204 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
205 clflush_cache_range((void *) addr, PAGE_SIZE);
206 }
207 }
208
209 static void cpa_flush_array(unsigned long *start, int numpages, int cache,
210 int in_flags, struct page **pages)
211 {
212 unsigned int i, level;
213 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
214
215 BUG_ON(irqs_disabled());
216
217 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
218
219 if (!cache || do_wbinvd)
220 return;
221
222 /*
223 * We only need to flush on one CPU,
224 * clflush is a MESI-coherent instruction that
225 * will cause all other CPUs to flush the same
226 * cachelines:
227 */
228 for (i = 0; i < numpages; i++) {
229 unsigned long addr;
230 pte_t *pte;
231
232 if (in_flags & CPA_PAGES_ARRAY)
233 addr = (unsigned long)page_address(pages[i]);
234 else
235 addr = start[i];
236
237 pte = lookup_address(addr, &level);
238
239 /*
240 * Only flush present addresses:
241 */
242 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
243 clflush_cache_range((void *)addr, PAGE_SIZE);
244 }
245 }
246
247 /*
248 * Certain areas of memory on x86 require very specific protection flags,
249 * for example the BIOS area or kernel text. Callers don't always get this
250 * right (again, ioremap() on BIOS memory is not uncommon) so this function
251 * checks and fixes these known static required protection bits.
252 */
253 static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
254 unsigned long pfn)
255 {
256 pgprot_t forbidden = __pgprot(0);
257
258 /*
259 * The BIOS area between 640k and 1Mb needs to be executable for
260 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
261 */
262 if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
263 pgprot_val(forbidden) |= _PAGE_NX;
264
265 /*
266 * The kernel text needs to be executable for obvious reasons
267 * Does not cover __inittext since that is gone later on. On
268 * 64bit we do not enforce !NX on the low mapping
269 */
270 if (within(address, (unsigned long)_text, (unsigned long)_etext))
271 pgprot_val(forbidden) |= _PAGE_NX;
272
273 /*
274 * The .rodata section needs to be read-only. Using the pfn
275 * catches all aliases.
276 */
277 if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT,
278 __pa((unsigned long)__end_rodata) >> PAGE_SHIFT))
279 pgprot_val(forbidden) |= _PAGE_RW;
280
281 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
282
283 return prot;
284 }
285
286 /*
287 * Lookup the page table entry for a virtual address. Return a pointer
288 * to the entry and the level of the mapping.
289 *
290 * Note: We return pud and pmd either when the entry is marked large
291 * or when the present bit is not set. Otherwise we would return a
292 * pointer to a nonexisting mapping.
293 */
294 pte_t *lookup_address(unsigned long address, unsigned int *level)
295 {
296 pgd_t *pgd = pgd_offset_k(address);
297 pud_t *pud;
298 pmd_t *pmd;
299
300 *level = PG_LEVEL_NONE;
301
302 if (pgd_none(*pgd))
303 return NULL;
304
305 pud = pud_offset(pgd, address);
306 if (pud_none(*pud))
307 return NULL;
308
309 *level = PG_LEVEL_1G;
310 if (pud_large(*pud) || !pud_present(*pud))
311 return (pte_t *)pud;
312
313 pmd = pmd_offset(pud, address);
314 if (pmd_none(*pmd))
315 return NULL;
316
317 *level = PG_LEVEL_2M;
318 if (pmd_large(*pmd) || !pmd_present(*pmd))
319 return (pte_t *)pmd;
320
321 *level = PG_LEVEL_4K;
322
323 return pte_offset_kernel(pmd, address);
324 }
325 EXPORT_SYMBOL_GPL(lookup_address);
326
327 /*
328 * Set the new pmd in all the pgds we know about:
329 */
330 static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
331 {
332 /* change init_mm */
333 set_pte_atomic(kpte, pte);
334 #ifdef CONFIG_X86_32
335 if (!SHARED_KERNEL_PMD) {
336 struct page *page;
337
338 list_for_each_entry(page, &pgd_list, lru) {
339 pgd_t *pgd;
340 pud_t *pud;
341 pmd_t *pmd;
342
343 pgd = (pgd_t *)page_address(page) + pgd_index(address);
344 pud = pud_offset(pgd, address);
345 pmd = pmd_offset(pud, address);
346 set_pte_atomic((pte_t *)pmd, pte);
347 }
348 }
349 #endif
350 }
351
352 static int
353 try_preserve_large_page(pte_t *kpte, unsigned long address,
354 struct cpa_data *cpa)
355 {
356 unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn;
357 pte_t new_pte, old_pte, *tmp;
358 pgprot_t old_prot, new_prot;
359 int i, do_split = 1;
360 unsigned int level;
361
362 if (cpa->force_split)
363 return 1;
364
365 spin_lock_irqsave(&pgd_lock, flags);
366 /*
367 * Check for races, another CPU might have split this page
368 * up already:
369 */
370 tmp = lookup_address(address, &level);
371 if (tmp != kpte)
372 goto out_unlock;
373
374 switch (level) {
375 case PG_LEVEL_2M:
376 psize = PMD_PAGE_SIZE;
377 pmask = PMD_PAGE_MASK;
378 break;
379 #ifdef CONFIG_X86_64
380 case PG_LEVEL_1G:
381 psize = PUD_PAGE_SIZE;
382 pmask = PUD_PAGE_MASK;
383 break;
384 #endif
385 default:
386 do_split = -EINVAL;
387 goto out_unlock;
388 }
389
390 /*
391 * Calculate the number of pages, which fit into this large
392 * page starting at address:
393 */
394 nextpage_addr = (address + psize) & pmask;
395 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
396 if (numpages < cpa->numpages)
397 cpa->numpages = numpages;
398
399 /*
400 * We are safe now. Check whether the new pgprot is the same:
401 */
402 old_pte = *kpte;
403 old_prot = new_prot = pte_pgprot(old_pte);
404
405 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
406 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
407
408 /*
409 * old_pte points to the large page base address. So we need
410 * to add the offset of the virtual address:
411 */
412 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
413 cpa->pfn = pfn;
414
415 new_prot = static_protections(new_prot, address, pfn);
416
417 /*
418 * We need to check the full range, whether
419 * static_protection() requires a different pgprot for one of
420 * the pages in the range we try to preserve:
421 */
422 addr = address + PAGE_SIZE;
423 pfn++;
424 for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) {
425 pgprot_t chk_prot = static_protections(new_prot, addr, pfn);
426
427 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
428 goto out_unlock;
429 }
430
431 /*
432 * If there are no changes, return. maxpages has been updated
433 * above:
434 */
435 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
436 do_split = 0;
437 goto out_unlock;
438 }
439
440 /*
441 * We need to change the attributes. Check, whether we can
442 * change the large page in one go. We request a split, when
443 * the address is not aligned and the number of pages is
444 * smaller than the number of pages in the large page. Note
445 * that we limited the number of possible pages already to
446 * the number of pages in the large page.
447 */
448 if (address == (nextpage_addr - psize) && cpa->numpages == numpages) {
449 /*
450 * The address is aligned and the number of pages
451 * covers the full page.
452 */
453 new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
454 __set_pmd_pte(kpte, address, new_pte);
455 cpa->flags |= CPA_FLUSHTLB;
456 do_split = 0;
457 }
458
459 out_unlock:
460 spin_unlock_irqrestore(&pgd_lock, flags);
461
462 return do_split;
463 }
464
465 static int split_large_page(pte_t *kpte, unsigned long address)
466 {
467 unsigned long flags, pfn, pfninc = 1;
468 unsigned int i, level;
469 pte_t *pbase, *tmp;
470 pgprot_t ref_prot;
471 struct page *base;
472
473 if (!debug_pagealloc)
474 spin_unlock(&cpa_lock);
475 base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
476 if (!debug_pagealloc)
477 spin_lock(&cpa_lock);
478 if (!base)
479 return -ENOMEM;
480
481 spin_lock_irqsave(&pgd_lock, flags);
482 /*
483 * Check for races, another CPU might have split this page
484 * up for us already:
485 */
486 tmp = lookup_address(address, &level);
487 if (tmp != kpte)
488 goto out_unlock;
489
490 pbase = (pte_t *)page_address(base);
491 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
492 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
493 /*
494 * If we ever want to utilize the PAT bit, we need to
495 * update this function to make sure it's converted from
496 * bit 12 to bit 7 when we cross from the 2MB level to
497 * the 4K level:
498 */
499 WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE);
500
501 #ifdef CONFIG_X86_64
502 if (level == PG_LEVEL_1G) {
503 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
504 pgprot_val(ref_prot) |= _PAGE_PSE;
505 }
506 #endif
507
508 /*
509 * Get the target pfn from the original entry:
510 */
511 pfn = pte_pfn(*kpte);
512 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
513 set_pte(&pbase[i], pfn_pte(pfn, ref_prot));
514
515 if (address >= (unsigned long)__va(0) &&
516 address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT))
517 split_page_count(level);
518
519 #ifdef CONFIG_X86_64
520 if (address >= (unsigned long)__va(1UL<<32) &&
521 address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT))
522 split_page_count(level);
523 #endif
524
525 /*
526 * Install the new, split up pagetable.
527 *
528 * We use the standard kernel pagetable protections for the new
529 * pagetable protections, the actual ptes set above control the
530 * primary protection behavior:
531 */
532 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
533
534 /*
535 * Intel Atom errata AAH41 workaround.
536 *
537 * The real fix should be in hw or in a microcode update, but
538 * we also probabilistically try to reduce the window of having
539 * a large TLB mixed with 4K TLBs while instruction fetches are
540 * going on.
541 */
542 __flush_tlb_all();
543
544 base = NULL;
545
546 out_unlock:
547 /*
548 * If we dropped out via the lookup_address check under
549 * pgd_lock then stick the page back into the pool:
550 */
551 if (base)
552 __free_page(base);
553 spin_unlock_irqrestore(&pgd_lock, flags);
554
555 return 0;
556 }
557
558 static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
559 int primary)
560 {
561 /*
562 * Ignore all non primary paths.
563 */
564 if (!primary)
565 return 0;
566
567 /*
568 * Ignore the NULL PTE for kernel identity mapping, as it is expected
569 * to have holes.
570 * Also set numpages to '1' indicating that we processed cpa req for
571 * one virtual address page and its pfn. TBD: numpages can be set based
572 * on the initial value and the level returned by lookup_address().
573 */
574 if (within(vaddr, PAGE_OFFSET,
575 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
576 cpa->numpages = 1;
577 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
578 return 0;
579 } else {
580 WARN(1, KERN_WARNING "CPA: called for zero pte. "
581 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
582 *cpa->vaddr);
583
584 return -EFAULT;
585 }
586 }
587
588 static int __change_page_attr(struct cpa_data *cpa, int primary)
589 {
590 unsigned long address;
591 int do_split, err;
592 unsigned int level;
593 pte_t *kpte, old_pte;
594
595 if (cpa->flags & CPA_PAGES_ARRAY) {
596 struct page *page = cpa->pages[cpa->curpage];
597 if (unlikely(PageHighMem(page)))
598 return 0;
599 address = (unsigned long)page_address(page);
600 } else if (cpa->flags & CPA_ARRAY)
601 address = cpa->vaddr[cpa->curpage];
602 else
603 address = *cpa->vaddr;
604 repeat:
605 kpte = lookup_address(address, &level);
606 if (!kpte)
607 return __cpa_process_fault(cpa, address, primary);
608
609 old_pte = *kpte;
610 if (!pte_val(old_pte))
611 return __cpa_process_fault(cpa, address, primary);
612
613 if (level == PG_LEVEL_4K) {
614 pte_t new_pte;
615 pgprot_t new_prot = pte_pgprot(old_pte);
616 unsigned long pfn = pte_pfn(old_pte);
617
618 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
619 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
620
621 new_prot = static_protections(new_prot, address, pfn);
622
623 /*
624 * We need to keep the pfn from the existing PTE,
625 * after all we're only going to change it's attributes
626 * not the memory it points to
627 */
628 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
629 cpa->pfn = pfn;
630 /*
631 * Do we really change anything ?
632 */
633 if (pte_val(old_pte) != pte_val(new_pte)) {
634 set_pte_atomic(kpte, new_pte);
635 cpa->flags |= CPA_FLUSHTLB;
636 }
637 cpa->numpages = 1;
638 return 0;
639 }
640
641 /*
642 * Check, whether we can keep the large page intact
643 * and just change the pte:
644 */
645 do_split = try_preserve_large_page(kpte, address, cpa);
646 /*
647 * When the range fits into the existing large page,
648 * return. cp->numpages and cpa->tlbflush have been updated in
649 * try_large_page:
650 */
651 if (do_split <= 0)
652 return do_split;
653
654 /*
655 * We have to split the large page:
656 */
657 err = split_large_page(kpte, address);
658 if (!err) {
659 /*
660 * Do a global flush tlb after splitting the large page
661 * and before we do the actual change page attribute in the PTE.
662 *
663 * With out this, we violate the TLB application note, that says
664 * "The TLBs may contain both ordinary and large-page
665 * translations for a 4-KByte range of linear addresses. This
666 * may occur if software modifies the paging structures so that
667 * the page size used for the address range changes. If the two
668 * translations differ with respect to page frame or attributes
669 * (e.g., permissions), processor behavior is undefined and may
670 * be implementation-specific."
671 *
672 * We do this global tlb flush inside the cpa_lock, so that we
673 * don't allow any other cpu, with stale tlb entries change the
674 * page attribute in parallel, that also falls into the
675 * just split large page entry.
676 */
677 flush_tlb_all();
678 goto repeat;
679 }
680
681 return err;
682 }
683
684 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
685
686 static int cpa_process_alias(struct cpa_data *cpa)
687 {
688 struct cpa_data alias_cpa;
689 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
690 unsigned long vaddr, remapped;
691 int ret;
692
693 if (cpa->pfn >= max_pfn_mapped)
694 return 0;
695
696 #ifdef CONFIG_X86_64
697 if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT)))
698 return 0;
699 #endif
700 /*
701 * No need to redo, when the primary call touched the direct
702 * mapping already:
703 */
704 if (cpa->flags & CPA_PAGES_ARRAY) {
705 struct page *page = cpa->pages[cpa->curpage];
706 if (unlikely(PageHighMem(page)))
707 return 0;
708 vaddr = (unsigned long)page_address(page);
709 } else if (cpa->flags & CPA_ARRAY)
710 vaddr = cpa->vaddr[cpa->curpage];
711 else
712 vaddr = *cpa->vaddr;
713
714 if (!(within(vaddr, PAGE_OFFSET,
715 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
716
717 alias_cpa = *cpa;
718 alias_cpa.vaddr = &laddr;
719 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
720
721 ret = __change_page_attr_set_clr(&alias_cpa, 0);
722 if (ret)
723 return ret;
724 }
725
726 #ifdef CONFIG_X86_64
727 /*
728 * If the primary call didn't touch the high mapping already
729 * and the physical address is inside the kernel map, we need
730 * to touch the high mapped kernel as well:
731 */
732 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
733 within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) {
734 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
735 __START_KERNEL_map - phys_base;
736 alias_cpa = *cpa;
737 alias_cpa.vaddr = &temp_cpa_vaddr;
738 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
739
740 /*
741 * The high mapping range is imprecise, so ignore the
742 * return value.
743 */
744 __change_page_attr_set_clr(&alias_cpa, 0);
745 }
746 #endif
747
748 /*
749 * If the PMD page was partially used for per-cpu remapping,
750 * the recycled area needs to be split and modified. Because
751 * the area is always proper subset of a PMD page
752 * cpa->numpages is guaranteed to be 1 for these areas, so
753 * there's no need to loop over and check for further remaps.
754 */
755 remapped = (unsigned long)pcpu_lpage_remapped((void *)laddr);
756 if (remapped) {
757 WARN_ON(cpa->numpages > 1);
758 alias_cpa = *cpa;
759 alias_cpa.vaddr = &remapped;
760 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
761 ret = __change_page_attr_set_clr(&alias_cpa, 0);
762 if (ret)
763 return ret;
764 }
765
766 return 0;
767 }
768
769 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
770 {
771 int ret, numpages = cpa->numpages;
772
773 while (numpages) {
774 /*
775 * Store the remaining nr of pages for the large page
776 * preservation check.
777 */
778 cpa->numpages = numpages;
779 /* for array changes, we can't use large page */
780 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
781 cpa->numpages = 1;
782
783 if (!debug_pagealloc)
784 spin_lock(&cpa_lock);
785 ret = __change_page_attr(cpa, checkalias);
786 if (!debug_pagealloc)
787 spin_unlock(&cpa_lock);
788 if (ret)
789 return ret;
790
791 if (checkalias) {
792 ret = cpa_process_alias(cpa);
793 if (ret)
794 return ret;
795 }
796
797 /*
798 * Adjust the number of pages with the result of the
799 * CPA operation. Either a large page has been
800 * preserved or a single page update happened.
801 */
802 BUG_ON(cpa->numpages > numpages);
803 numpages -= cpa->numpages;
804 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
805 cpa->curpage++;
806 else
807 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
808
809 }
810 return 0;
811 }
812
813 static inline int cache_attr(pgprot_t attr)
814 {
815 return pgprot_val(attr) &
816 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
817 }
818
819 static int change_page_attr_set_clr(unsigned long *addr, int numpages,
820 pgprot_t mask_set, pgprot_t mask_clr,
821 int force_split, int in_flag,
822 struct page **pages)
823 {
824 struct cpa_data cpa;
825 int ret, cache, checkalias;
826 unsigned long baddr = 0;
827
828 /*
829 * Check, if we are requested to change a not supported
830 * feature:
831 */
832 mask_set = canon_pgprot(mask_set);
833 mask_clr = canon_pgprot(mask_clr);
834 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
835 return 0;
836
837 /* Ensure we are PAGE_SIZE aligned */
838 if (in_flag & CPA_ARRAY) {
839 int i;
840 for (i = 0; i < numpages; i++) {
841 if (addr[i] & ~PAGE_MASK) {
842 addr[i] &= PAGE_MASK;
843 WARN_ON_ONCE(1);
844 }
845 }
846 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
847 /*
848 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
849 * No need to cehck in that case
850 */
851 if (*addr & ~PAGE_MASK) {
852 *addr &= PAGE_MASK;
853 /*
854 * People should not be passing in unaligned addresses:
855 */
856 WARN_ON_ONCE(1);
857 }
858 /*
859 * Save address for cache flush. *addr is modified in the call
860 * to __change_page_attr_set_clr() below.
861 */
862 baddr = *addr;
863 }
864
865 /* Must avoid aliasing mappings in the highmem code */
866 kmap_flush_unused();
867
868 vm_unmap_aliases();
869
870 cpa.vaddr = addr;
871 cpa.pages = pages;
872 cpa.numpages = numpages;
873 cpa.mask_set = mask_set;
874 cpa.mask_clr = mask_clr;
875 cpa.flags = 0;
876 cpa.curpage = 0;
877 cpa.force_split = force_split;
878
879 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
880 cpa.flags |= in_flag;
881
882 /* No alias checking for _NX bit modifications */
883 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
884
885 ret = __change_page_attr_set_clr(&cpa, checkalias);
886
887 /*
888 * Check whether we really changed something:
889 */
890 if (!(cpa.flags & CPA_FLUSHTLB))
891 goto out;
892
893 /*
894 * No need to flush, when we did not set any of the caching
895 * attributes:
896 */
897 cache = cache_attr(mask_set);
898
899 /*
900 * On success we use clflush, when the CPU supports it to
901 * avoid the wbindv. If the CPU does not support it and in the
902 * error case we fall back to cpa_flush_all (which uses
903 * wbindv):
904 */
905 if (!ret && cpu_has_clflush) {
906 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
907 cpa_flush_array(addr, numpages, cache,
908 cpa.flags, pages);
909 } else
910 cpa_flush_range(baddr, numpages, cache);
911 } else
912 cpa_flush_all(cache);
913
914 out:
915 return ret;
916 }
917
918 static inline int change_page_attr_set(unsigned long *addr, int numpages,
919 pgprot_t mask, int array)
920 {
921 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
922 (array ? CPA_ARRAY : 0), NULL);
923 }
924
925 static inline int change_page_attr_clear(unsigned long *addr, int numpages,
926 pgprot_t mask, int array)
927 {
928 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
929 (array ? CPA_ARRAY : 0), NULL);
930 }
931
932 static inline int cpa_set_pages_array(struct page **pages, int numpages,
933 pgprot_t mask)
934 {
935 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
936 CPA_PAGES_ARRAY, pages);
937 }
938
939 static inline int cpa_clear_pages_array(struct page **pages, int numpages,
940 pgprot_t mask)
941 {
942 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
943 CPA_PAGES_ARRAY, pages);
944 }
945
946 int _set_memory_uc(unsigned long addr, int numpages)
947 {
948 /*
949 * for now UC MINUS. see comments in ioremap_nocache()
950 */
951 return change_page_attr_set(&addr, numpages,
952 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
953 }
954
955 int set_memory_uc(unsigned long addr, int numpages)
956 {
957 int ret;
958
959 /*
960 * for now UC MINUS. see comments in ioremap_nocache()
961 */
962 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
963 _PAGE_CACHE_UC_MINUS, NULL);
964 if (ret)
965 goto out_err;
966
967 ret = _set_memory_uc(addr, numpages);
968 if (ret)
969 goto out_free;
970
971 return 0;
972
973 out_free:
974 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
975 out_err:
976 return ret;
977 }
978 EXPORT_SYMBOL(set_memory_uc);
979
980 int set_memory_array_uc(unsigned long *addr, int addrinarray)
981 {
982 int i, j;
983 int ret;
984
985 /*
986 * for now UC MINUS. see comments in ioremap_nocache()
987 */
988 for (i = 0; i < addrinarray; i++) {
989 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
990 _PAGE_CACHE_UC_MINUS, NULL);
991 if (ret)
992 goto out_free;
993 }
994
995 ret = change_page_attr_set(addr, addrinarray,
996 __pgprot(_PAGE_CACHE_UC_MINUS), 1);
997 if (ret)
998 goto out_free;
999
1000 return 0;
1001
1002 out_free:
1003 for (j = 0; j < i; j++)
1004 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
1005
1006 return ret;
1007 }
1008 EXPORT_SYMBOL(set_memory_array_uc);
1009
1010 int _set_memory_wc(unsigned long addr, int numpages)
1011 {
1012 int ret;
1013 unsigned long addr_copy = addr;
1014
1015 ret = change_page_attr_set(&addr, numpages,
1016 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
1017 if (!ret) {
1018 ret = change_page_attr_set_clr(&addr_copy, numpages,
1019 __pgprot(_PAGE_CACHE_WC),
1020 __pgprot(_PAGE_CACHE_MASK),
1021 0, 0, NULL);
1022 }
1023 return ret;
1024 }
1025
1026 int set_memory_wc(unsigned long addr, int numpages)
1027 {
1028 int ret;
1029
1030 if (!pat_enabled)
1031 return set_memory_uc(addr, numpages);
1032
1033 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1034 _PAGE_CACHE_WC, NULL);
1035 if (ret)
1036 goto out_err;
1037
1038 ret = _set_memory_wc(addr, numpages);
1039 if (ret)
1040 goto out_free;
1041
1042 return 0;
1043
1044 out_free:
1045 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1046 out_err:
1047 return ret;
1048 }
1049 EXPORT_SYMBOL(set_memory_wc);
1050
1051 int _set_memory_wb(unsigned long addr, int numpages)
1052 {
1053 return change_page_attr_clear(&addr, numpages,
1054 __pgprot(_PAGE_CACHE_MASK), 0);
1055 }
1056
1057 int set_memory_wb(unsigned long addr, int numpages)
1058 {
1059 int ret;
1060
1061 ret = _set_memory_wb(addr, numpages);
1062 if (ret)
1063 return ret;
1064
1065 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1066 return 0;
1067 }
1068 EXPORT_SYMBOL(set_memory_wb);
1069
1070 int set_memory_array_wb(unsigned long *addr, int addrinarray)
1071 {
1072 int i;
1073 int ret;
1074
1075 ret = change_page_attr_clear(addr, addrinarray,
1076 __pgprot(_PAGE_CACHE_MASK), 1);
1077 if (ret)
1078 return ret;
1079
1080 for (i = 0; i < addrinarray; i++)
1081 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
1082
1083 return 0;
1084 }
1085 EXPORT_SYMBOL(set_memory_array_wb);
1086
1087 int set_memory_x(unsigned long addr, int numpages)
1088 {
1089 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
1090 }
1091 EXPORT_SYMBOL(set_memory_x);
1092
1093 int set_memory_nx(unsigned long addr, int numpages)
1094 {
1095 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
1096 }
1097 EXPORT_SYMBOL(set_memory_nx);
1098
1099 int set_memory_ro(unsigned long addr, int numpages)
1100 {
1101 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
1102 }
1103 EXPORT_SYMBOL_GPL(set_memory_ro);
1104
1105 int set_memory_rw(unsigned long addr, int numpages)
1106 {
1107 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
1108 }
1109 EXPORT_SYMBOL_GPL(set_memory_rw);
1110
1111 int set_memory_np(unsigned long addr, int numpages)
1112 {
1113 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
1114 }
1115
1116 int set_memory_4k(unsigned long addr, int numpages)
1117 {
1118 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
1119 __pgprot(0), 1, 0, NULL);
1120 }
1121
1122 int set_pages_uc(struct page *page, int numpages)
1123 {
1124 unsigned long addr = (unsigned long)page_address(page);
1125
1126 return set_memory_uc(addr, numpages);
1127 }
1128 EXPORT_SYMBOL(set_pages_uc);
1129
1130 int set_pages_array_uc(struct page **pages, int addrinarray)
1131 {
1132 unsigned long start;
1133 unsigned long end;
1134 int i;
1135 int free_idx;
1136
1137 for (i = 0; i < addrinarray; i++) {
1138 if (PageHighMem(pages[i]))
1139 continue;
1140 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1141 end = start + PAGE_SIZE;
1142 if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL))
1143 goto err_out;
1144 }
1145
1146 if (cpa_set_pages_array(pages, addrinarray,
1147 __pgprot(_PAGE_CACHE_UC_MINUS)) == 0) {
1148 return 0; /* Success */
1149 }
1150 err_out:
1151 free_idx = i;
1152 for (i = 0; i < free_idx; i++) {
1153 if (PageHighMem(pages[i]))
1154 continue;
1155 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1156 end = start + PAGE_SIZE;
1157 free_memtype(start, end);
1158 }
1159 return -EINVAL;
1160 }
1161 EXPORT_SYMBOL(set_pages_array_uc);
1162
1163 int set_pages_wb(struct page *page, int numpages)
1164 {
1165 unsigned long addr = (unsigned long)page_address(page);
1166
1167 return set_memory_wb(addr, numpages);
1168 }
1169 EXPORT_SYMBOL(set_pages_wb);
1170
1171 int set_pages_array_wb(struct page **pages, int addrinarray)
1172 {
1173 int retval;
1174 unsigned long start;
1175 unsigned long end;
1176 int i;
1177
1178 retval = cpa_clear_pages_array(pages, addrinarray,
1179 __pgprot(_PAGE_CACHE_MASK));
1180 if (retval)
1181 return retval;
1182
1183 for (i = 0; i < addrinarray; i++) {
1184 if (PageHighMem(pages[i]))
1185 continue;
1186 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1187 end = start + PAGE_SIZE;
1188 free_memtype(start, end);
1189 }
1190
1191 return 0;
1192 }
1193 EXPORT_SYMBOL(set_pages_array_wb);
1194
1195 int set_pages_x(struct page *page, int numpages)
1196 {
1197 unsigned long addr = (unsigned long)page_address(page);
1198
1199 return set_memory_x(addr, numpages);
1200 }
1201 EXPORT_SYMBOL(set_pages_x);
1202
1203 int set_pages_nx(struct page *page, int numpages)
1204 {
1205 unsigned long addr = (unsigned long)page_address(page);
1206
1207 return set_memory_nx(addr, numpages);
1208 }
1209 EXPORT_SYMBOL(set_pages_nx);
1210
1211 int set_pages_ro(struct page *page, int numpages)
1212 {
1213 unsigned long addr = (unsigned long)page_address(page);
1214
1215 return set_memory_ro(addr, numpages);
1216 }
1217
1218 int set_pages_rw(struct page *page, int numpages)
1219 {
1220 unsigned long addr = (unsigned long)page_address(page);
1221
1222 return set_memory_rw(addr, numpages);
1223 }
1224
1225 #ifdef CONFIG_DEBUG_PAGEALLOC
1226
1227 static int __set_pages_p(struct page *page, int numpages)
1228 {
1229 unsigned long tempaddr = (unsigned long) page_address(page);
1230 struct cpa_data cpa = { .vaddr = &tempaddr,
1231 .numpages = numpages,
1232 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1233 .mask_clr = __pgprot(0),
1234 .flags = 0};
1235
1236 /*
1237 * No alias checking needed for setting present flag. otherwise,
1238 * we may need to break large pages for 64-bit kernel text
1239 * mappings (this adds to complexity if we want to do this from
1240 * atomic context especially). Let's keep it simple!
1241 */
1242 return __change_page_attr_set_clr(&cpa, 0);
1243 }
1244
1245 static int __set_pages_np(struct page *page, int numpages)
1246 {
1247 unsigned long tempaddr = (unsigned long) page_address(page);
1248 struct cpa_data cpa = { .vaddr = &tempaddr,
1249 .numpages = numpages,
1250 .mask_set = __pgprot(0),
1251 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1252 .flags = 0};
1253
1254 /*
1255 * No alias checking needed for setting not present flag. otherwise,
1256 * we may need to break large pages for 64-bit kernel text
1257 * mappings (this adds to complexity if we want to do this from
1258 * atomic context especially). Let's keep it simple!
1259 */
1260 return __change_page_attr_set_clr(&cpa, 0);
1261 }
1262
1263 void kernel_map_pages(struct page *page, int numpages, int enable)
1264 {
1265 if (PageHighMem(page))
1266 return;
1267 if (!enable) {
1268 debug_check_no_locks_freed(page_address(page),
1269 numpages * PAGE_SIZE);
1270 }
1271
1272 /*
1273 * If page allocator is not up yet then do not call c_p_a():
1274 */
1275 if (!debug_pagealloc_enabled)
1276 return;
1277
1278 /*
1279 * The return value is ignored as the calls cannot fail.
1280 * Large pages for identity mappings are not used at boot time
1281 * and hence no memory allocations during large page split.
1282 */
1283 if (enable)
1284 __set_pages_p(page, numpages);
1285 else
1286 __set_pages_np(page, numpages);
1287
1288 /*
1289 * We should perform an IPI and flush all tlbs,
1290 * but that can deadlock->flush only current cpu:
1291 */
1292 __flush_tlb_all();
1293 }
1294
1295 #ifdef CONFIG_HIBERNATION
1296
1297 bool kernel_page_present(struct page *page)
1298 {
1299 unsigned int level;
1300 pte_t *pte;
1301
1302 if (PageHighMem(page))
1303 return false;
1304
1305 pte = lookup_address((unsigned long)page_address(page), &level);
1306 return (pte_val(*pte) & _PAGE_PRESENT);
1307 }
1308
1309 #endif /* CONFIG_HIBERNATION */
1310
1311 #endif /* CONFIG_DEBUG_PAGEALLOC */
1312
1313 /*
1314 * The testcases use internal knowledge of the implementation that shouldn't
1315 * be exposed to the rest of the kernel. Include these directly here.
1316 */
1317 #ifdef CONFIG_CPA_DEBUG
1318 #include "pageattr-test.c"
1319 #endif
1320
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