1 /******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22 #ifndef __KERNEL__
23 #include <stdio.h>
24 #include <stdint.h>
25 #include <public/xen.h>
26 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
27 #else
28 #include <linux/kvm_host.h>
29 #include "kvm_cache_regs.h"
30 #define DPRINTF(x...) do {} while (0)
31 #endif
32 #include <linux/module.h>
33 #include <asm/kvm_x86_emulate.h>
34
35 /*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44 /* Operand sizes: 8-bit operands or specified/overridden size. */
45 #define ByteOp (1<<0) /* 8-bit operands. */
46 /* Destination operand type. */
47 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48 #define DstReg (2<<1) /* Register operand. */
49 #define DstMem (3<<1) /* Memory operand. */
50 #define DstAcc (4<<1) /* Destination Accumulator */
51 #define DstMask (7<<1)
52 /* Source operand type. */
53 #define SrcNone (0<<4) /* No source operand. */
54 #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
55 #define SrcReg (1<<4) /* Register operand. */
56 #define SrcMem (2<<4) /* Memory operand. */
57 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
58 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
59 #define SrcImm (5<<4) /* Immediate operand. */
60 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
61 #define SrcOne (7<<4) /* Implied '1' */
62 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
63 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
64 #define SrcMask (0xf<<4)
65 /* Generic ModRM decode. */
66 #define ModRM (1<<8)
67 /* Destination is only written; never read. */
68 #define Mov (1<<9)
69 #define BitOp (1<<10)
70 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
71 #define String (1<<12) /* String instruction (rep capable) */
72 #define Stack (1<<13) /* Stack instruction (push/pop) */
73 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
74 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
75 #define GroupMask 0xff /* Group number stored in bits 0:7 */
76 /* Source 2 operand type */
77 #define Src2None (0<<29)
78 #define Src2CL (1<<29)
79 #define Src2ImmByte (2<<29)
80 #define Src2One (3<<29)
81 #define Src2Imm16 (4<<29)
82 #define Src2Mask (7<<29)
83
84 enum {
85 Group1_80, Group1_81, Group1_82, Group1_83,
86 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
87 };
88
89 static u32 opcode_table[256] = {
90 /* 0x00 - 0x07 */
91 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
92 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
93 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 0, 0,
94 /* 0x08 - 0x0F */
95 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
96 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
97 0, 0, 0, 0,
98 /* 0x10 - 0x17 */
99 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
100 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
101 0, 0, 0, 0,
102 /* 0x18 - 0x1F */
103 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
104 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
105 0, 0, 0, 0,
106 /* 0x20 - 0x27 */
107 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
108 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
109 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
110 /* 0x28 - 0x2F */
111 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
112 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
113 0, 0, 0, 0,
114 /* 0x30 - 0x37 */
115 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
116 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
117 0, 0, 0, 0,
118 /* 0x38 - 0x3F */
119 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
120 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
121 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
122 0, 0,
123 /* 0x40 - 0x47 */
124 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
125 /* 0x48 - 0x4F */
126 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
127 /* 0x50 - 0x57 */
128 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
129 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
130 /* 0x58 - 0x5F */
131 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
132 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
133 /* 0x60 - 0x67 */
134 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
135 0, 0, 0, 0,
136 /* 0x68 - 0x6F */
137 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
138 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
139 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
140 /* 0x70 - 0x77 */
141 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
142 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
143 /* 0x78 - 0x7F */
144 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
145 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
146 /* 0x80 - 0x87 */
147 Group | Group1_80, Group | Group1_81,
148 Group | Group1_82, Group | Group1_83,
149 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
150 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
151 /* 0x88 - 0x8F */
152 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
153 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
154 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
155 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
156 /* 0x90 - 0x97 */
157 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
158 /* 0x98 - 0x9F */
159 0, 0, SrcImm | Src2Imm16, 0,
160 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
161 /* 0xA0 - 0xA7 */
162 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
163 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
164 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
165 ByteOp | ImplicitOps | String, ImplicitOps | String,
166 /* 0xA8 - 0xAF */
167 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
168 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
169 ByteOp | ImplicitOps | String, ImplicitOps | String,
170 /* 0xB0 - 0xB7 */
171 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
172 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
173 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
174 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
175 /* 0xB8 - 0xBF */
176 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
177 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
178 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
179 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
180 /* 0xC0 - 0xC7 */
181 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
182 0, ImplicitOps | Stack, 0, 0,
183 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
184 /* 0xC8 - 0xCF */
185 0, 0, 0, ImplicitOps | Stack,
186 ImplicitOps, SrcImmByte, ImplicitOps, ImplicitOps,
187 /* 0xD0 - 0xD7 */
188 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
189 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
190 0, 0, 0, 0,
191 /* 0xD8 - 0xDF */
192 0, 0, 0, 0, 0, 0, 0, 0,
193 /* 0xE0 - 0xE7 */
194 0, 0, 0, 0,
195 ByteOp | SrcImmUByte, SrcImmUByte,
196 ByteOp | SrcImmUByte, SrcImmUByte,
197 /* 0xE8 - 0xEF */
198 SrcImm | Stack, SrcImm | ImplicitOps,
199 SrcImmU | Src2Imm16, SrcImmByte | ImplicitOps,
200 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
201 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
202 /* 0xF0 - 0xF7 */
203 0, 0, 0, 0,
204 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
205 /* 0xF8 - 0xFF */
206 ImplicitOps, 0, ImplicitOps, ImplicitOps,
207 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
208 };
209
210 static u32 twobyte_table[256] = {
211 /* 0x00 - 0x0F */
212 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
213 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
214 /* 0x10 - 0x1F */
215 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
216 /* 0x20 - 0x2F */
217 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
218 0, 0, 0, 0, 0, 0, 0, 0,
219 /* 0x30 - 0x3F */
220 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
221 /* 0x40 - 0x47 */
222 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
223 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
224 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
225 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
226 /* 0x48 - 0x4F */
227 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
228 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
229 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
230 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
231 /* 0x50 - 0x5F */
232 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
233 /* 0x60 - 0x6F */
234 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
235 /* 0x70 - 0x7F */
236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
237 /* 0x80 - 0x8F */
238 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
239 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
240 /* 0x90 - 0x9F */
241 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
242 /* 0xA0 - 0xA7 */
243 0, 0, 0, DstMem | SrcReg | ModRM | BitOp,
244 DstMem | SrcReg | Src2ImmByte | ModRM,
245 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
246 /* 0xA8 - 0xAF */
247 0, 0, 0, DstMem | SrcReg | ModRM | BitOp,
248 DstMem | SrcReg | Src2ImmByte | ModRM,
249 DstMem | SrcReg | Src2CL | ModRM,
250 ModRM, 0,
251 /* 0xB0 - 0xB7 */
252 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
253 DstMem | SrcReg | ModRM | BitOp,
254 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
255 DstReg | SrcMem16 | ModRM | Mov,
256 /* 0xB8 - 0xBF */
257 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
258 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
259 DstReg | SrcMem16 | ModRM | Mov,
260 /* 0xC0 - 0xCF */
261 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
262 0, 0, 0, 0, 0, 0, 0, 0,
263 /* 0xD0 - 0xDF */
264 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
265 /* 0xE0 - 0xEF */
266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
267 /* 0xF0 - 0xFF */
268 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
269 };
270
271 static u32 group_table[] = {
272 [Group1_80*8] =
273 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
274 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
275 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
276 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
277 [Group1_81*8] =
278 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
279 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
280 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
281 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
282 [Group1_82*8] =
283 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
284 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
285 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
286 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
287 [Group1_83*8] =
288 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
289 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
290 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
291 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
292 [Group1A*8] =
293 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
294 [Group3_Byte*8] =
295 ByteOp | SrcImm | DstMem | ModRM, 0,
296 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
297 0, 0, 0, 0,
298 [Group3*8] =
299 DstMem | SrcImm | ModRM, 0,
300 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
301 0, 0, 0, 0,
302 [Group4*8] =
303 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
304 0, 0, 0, 0, 0, 0,
305 [Group5*8] =
306 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
307 SrcMem | ModRM | Stack, 0,
308 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
309 [Group7*8] =
310 0, 0, ModRM | SrcMem, ModRM | SrcMem,
311 SrcNone | ModRM | DstMem | Mov, 0,
312 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
313 };
314
315 static u32 group2_table[] = {
316 [Group7*8] =
317 SrcNone | ModRM, 0, 0, SrcNone | ModRM,
318 SrcNone | ModRM | DstMem | Mov, 0,
319 SrcMem16 | ModRM | Mov, 0,
320 };
321
322 /* EFLAGS bit definitions. */
323 #define EFLG_OF (1<<11)
324 #define EFLG_DF (1<<10)
325 #define EFLG_SF (1<<7)
326 #define EFLG_ZF (1<<6)
327 #define EFLG_AF (1<<4)
328 #define EFLG_PF (1<<2)
329 #define EFLG_CF (1<<0)
330
331 /*
332 * Instruction emulation:
333 * Most instructions are emulated directly via a fragment of inline assembly
334 * code. This allows us to save/restore EFLAGS and thus very easily pick up
335 * any modified flags.
336 */
337
338 #if defined(CONFIG_X86_64)
339 #define _LO32 "k" /* force 32-bit operand */
340 #define _STK "%%rsp" /* stack pointer */
341 #elif defined(__i386__)
342 #define _LO32 "" /* force 32-bit operand */
343 #define _STK "%%esp" /* stack pointer */
344 #endif
345
346 /*
347 * These EFLAGS bits are restored from saved value during emulation, and
348 * any changes are written back to the saved value after emulation.
349 */
350 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
351
352 /* Before executing instruction: restore necessary bits in EFLAGS. */
353 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
354 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
355 "movl %"_sav",%"_LO32 _tmp"; " \
356 "push %"_tmp"; " \
357 "push %"_tmp"; " \
358 "movl %"_msk",%"_LO32 _tmp"; " \
359 "andl %"_LO32 _tmp",("_STK"); " \
360 "pushf; " \
361 "notl %"_LO32 _tmp"; " \
362 "andl %"_LO32 _tmp",("_STK"); " \
363 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
364 "pop %"_tmp"; " \
365 "orl %"_LO32 _tmp",("_STK"); " \
366 "popf; " \
367 "pop %"_sav"; "
368
369 /* After executing instruction: write-back necessary bits in EFLAGS. */
370 #define _POST_EFLAGS(_sav, _msk, _tmp) \
371 /* _sav |= EFLAGS & _msk; */ \
372 "pushf; " \
373 "pop %"_tmp"; " \
374 "andl %"_msk",%"_LO32 _tmp"; " \
375 "orl %"_LO32 _tmp",%"_sav"; "
376
377 #ifdef CONFIG_X86_64
378 #define ON64(x) x
379 #else
380 #define ON64(x)
381 #endif
382
383 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
384 do { \
385 __asm__ __volatile__ ( \
386 _PRE_EFLAGS("", "4", "2") \
387 _op _suffix " %"_x"3,%1; " \
388 _POST_EFLAGS("", "4", "2") \
389 : "=m" (_eflags), "=m" ((_dst).val), \
390 "=&r" (_tmp) \
391 : _y ((_src).val), "i" (EFLAGS_MASK)); \
392 } while (0)
393
394
395 /* Raw emulation: instruction has two explicit operands. */
396 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
397 do { \
398 unsigned long _tmp; \
399 \
400 switch ((_dst).bytes) { \
401 case 2: \
402 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
403 break; \
404 case 4: \
405 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
406 break; \
407 case 8: \
408 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
409 break; \
410 } \
411 } while (0)
412
413 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
414 do { \
415 unsigned long _tmp; \
416 switch ((_dst).bytes) { \
417 case 1: \
418 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
419 break; \
420 default: \
421 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
422 _wx, _wy, _lx, _ly, _qx, _qy); \
423 break; \
424 } \
425 } while (0)
426
427 /* Source operand is byte-sized and may be restricted to just %cl. */
428 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
429 __emulate_2op(_op, _src, _dst, _eflags, \
430 "b", "c", "b", "c", "b", "c", "b", "c")
431
432 /* Source operand is byte, word, long or quad sized. */
433 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
434 __emulate_2op(_op, _src, _dst, _eflags, \
435 "b", "q", "w", "r", _LO32, "r", "", "r")
436
437 /* Source operand is word, long or quad sized. */
438 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
439 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
440 "w", "r", _LO32, "r", "", "r")
441
442 /* Instruction has three operands and one operand is stored in ECX register */
443 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
444 do { \
445 unsigned long _tmp; \
446 _type _clv = (_cl).val; \
447 _type _srcv = (_src).val; \
448 _type _dstv = (_dst).val; \
449 \
450 __asm__ __volatile__ ( \
451 _PRE_EFLAGS("", "5", "2") \
452 _op _suffix " %4,%1 \n" \
453 _POST_EFLAGS("", "5", "2") \
454 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
455 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
456 ); \
457 \
458 (_cl).val = (unsigned long) _clv; \
459 (_src).val = (unsigned long) _srcv; \
460 (_dst).val = (unsigned long) _dstv; \
461 } while (0)
462
463 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
464 do { \
465 switch ((_dst).bytes) { \
466 case 2: \
467 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
468 "w", unsigned short); \
469 break; \
470 case 4: \
471 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
472 "l", unsigned int); \
473 break; \
474 case 8: \
475 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
476 "q", unsigned long)); \
477 break; \
478 } \
479 } while (0)
480
481 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
482 do { \
483 unsigned long _tmp; \
484 \
485 __asm__ __volatile__ ( \
486 _PRE_EFLAGS("", "3", "2") \
487 _op _suffix " %1; " \
488 _POST_EFLAGS("", "3", "2") \
489 : "=m" (_eflags), "+m" ((_dst).val), \
490 "=&r" (_tmp) \
491 : "i" (EFLAGS_MASK)); \
492 } while (0)
493
494 /* Instruction has only one explicit operand (no source operand). */
495 #define emulate_1op(_op, _dst, _eflags) \
496 do { \
497 switch ((_dst).bytes) { \
498 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
499 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
500 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
501 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
502 } \
503 } while (0)
504
505 /* Fetch next part of the instruction being emulated. */
506 #define insn_fetch(_type, _size, _eip) \
507 ({ unsigned long _x; \
508 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
509 if (rc != 0) \
510 goto done; \
511 (_eip) += (_size); \
512 (_type)_x; \
513 })
514
515 static inline unsigned long ad_mask(struct decode_cache *c)
516 {
517 return (1UL << (c->ad_bytes << 3)) - 1;
518 }
519
520 /* Access/update address held in a register, based on addressing mode. */
521 static inline unsigned long
522 address_mask(struct decode_cache *c, unsigned long reg)
523 {
524 if (c->ad_bytes == sizeof(unsigned long))
525 return reg;
526 else
527 return reg & ad_mask(c);
528 }
529
530 static inline unsigned long
531 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
532 {
533 return base + address_mask(c, reg);
534 }
535
536 static inline void
537 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
538 {
539 if (c->ad_bytes == sizeof(unsigned long))
540 *reg += inc;
541 else
542 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
543 }
544
545 static inline void jmp_rel(struct decode_cache *c, int rel)
546 {
547 register_address_increment(c, &c->eip, rel);
548 }
549
550 static void set_seg_override(struct decode_cache *c, int seg)
551 {
552 c->has_seg_override = true;
553 c->seg_override = seg;
554 }
555
556 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
557 {
558 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
559 return 0;
560
561 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
562 }
563
564 static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
565 struct decode_cache *c)
566 {
567 if (!c->has_seg_override)
568 return 0;
569
570 return seg_base(ctxt, c->seg_override);
571 }
572
573 static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
574 {
575 return seg_base(ctxt, VCPU_SREG_ES);
576 }
577
578 static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
579 {
580 return seg_base(ctxt, VCPU_SREG_SS);
581 }
582
583 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
584 struct x86_emulate_ops *ops,
585 unsigned long linear, u8 *dest)
586 {
587 struct fetch_cache *fc = &ctxt->decode.fetch;
588 int rc;
589 int size;
590
591 if (linear < fc->start || linear >= fc->end) {
592 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
593 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
594 if (rc)
595 return rc;
596 fc->start = linear;
597 fc->end = linear + size;
598 }
599 *dest = fc->data[linear - fc->start];
600 return 0;
601 }
602
603 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
604 struct x86_emulate_ops *ops,
605 unsigned long eip, void *dest, unsigned size)
606 {
607 int rc = 0;
608
609 /* x86 instructions are limited to 15 bytes. */
610 if (eip + size - ctxt->decode.eip_orig > 15)
611 return X86EMUL_UNHANDLEABLE;
612 eip += ctxt->cs_base;
613 while (size--) {
614 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
615 if (rc)
616 return rc;
617 }
618 return 0;
619 }
620
621 /*
622 * Given the 'reg' portion of a ModRM byte, and a register block, return a
623 * pointer into the block that addresses the relevant register.
624 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
625 */
626 static void *decode_register(u8 modrm_reg, unsigned long *regs,
627 int highbyte_regs)
628 {
629 void *p;
630
631 p = ®s[modrm_reg];
632 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
633 p = (unsigned char *)®s[modrm_reg & 3] + 1;
634 return p;
635 }
636
637 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
638 struct x86_emulate_ops *ops,
639 void *ptr,
640 u16 *size, unsigned long *address, int op_bytes)
641 {
642 int rc;
643
644 if (op_bytes == 2)
645 op_bytes = 3;
646 *address = 0;
647 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
648 ctxt->vcpu);
649 if (rc)
650 return rc;
651 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
652 ctxt->vcpu);
653 return rc;
654 }
655
656 static int test_cc(unsigned int condition, unsigned int flags)
657 {
658 int rc = 0;
659
660 switch ((condition & 15) >> 1) {
661 case 0: /* o */
662 rc |= (flags & EFLG_OF);
663 break;
664 case 1: /* b/c/nae */
665 rc |= (flags & EFLG_CF);
666 break;
667 case 2: /* z/e */
668 rc |= (flags & EFLG_ZF);
669 break;
670 case 3: /* be/na */
671 rc |= (flags & (EFLG_CF|EFLG_ZF));
672 break;
673 case 4: /* s */
674 rc |= (flags & EFLG_SF);
675 break;
676 case 5: /* p/pe */
677 rc |= (flags & EFLG_PF);
678 break;
679 case 7: /* le/ng */
680 rc |= (flags & EFLG_ZF);
681 /* fall through */
682 case 6: /* l/nge */
683 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
684 break;
685 }
686
687 /* Odd condition identifiers (lsb == 1) have inverted sense. */
688 return (!!rc ^ (condition & 1));
689 }
690
691 static void decode_register_operand(struct operand *op,
692 struct decode_cache *c,
693 int inhibit_bytereg)
694 {
695 unsigned reg = c->modrm_reg;
696 int highbyte_regs = c->rex_prefix == 0;
697
698 if (!(c->d & ModRM))
699 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
700 op->type = OP_REG;
701 if ((c->d & ByteOp) && !inhibit_bytereg) {
702 op->ptr = decode_register(reg, c->regs, highbyte_regs);
703 op->val = *(u8 *)op->ptr;
704 op->bytes = 1;
705 } else {
706 op->ptr = decode_register(reg, c->regs, 0);
707 op->bytes = c->op_bytes;
708 switch (op->bytes) {
709 case 2:
710 op->val = *(u16 *)op->ptr;
711 break;
712 case 4:
713 op->val = *(u32 *)op->ptr;
714 break;
715 case 8:
716 op->val = *(u64 *) op->ptr;
717 break;
718 }
719 }
720 op->orig_val = op->val;
721 }
722
723 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
724 struct x86_emulate_ops *ops)
725 {
726 struct decode_cache *c = &ctxt->decode;
727 u8 sib;
728 int index_reg = 0, base_reg = 0, scale;
729 int rc = 0;
730
731 if (c->rex_prefix) {
732 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
733 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
734 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
735 }
736
737 c->modrm = insn_fetch(u8, 1, c->eip);
738 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
739 c->modrm_reg |= (c->modrm & 0x38) >> 3;
740 c->modrm_rm |= (c->modrm & 0x07);
741 c->modrm_ea = 0;
742 c->use_modrm_ea = 1;
743
744 if (c->modrm_mod == 3) {
745 c->modrm_ptr = decode_register(c->modrm_rm,
746 c->regs, c->d & ByteOp);
747 c->modrm_val = *(unsigned long *)c->modrm_ptr;
748 return rc;
749 }
750
751 if (c->ad_bytes == 2) {
752 unsigned bx = c->regs[VCPU_REGS_RBX];
753 unsigned bp = c->regs[VCPU_REGS_RBP];
754 unsigned si = c->regs[VCPU_REGS_RSI];
755 unsigned di = c->regs[VCPU_REGS_RDI];
756
757 /* 16-bit ModR/M decode. */
758 switch (c->modrm_mod) {
759 case 0:
760 if (c->modrm_rm == 6)
761 c->modrm_ea += insn_fetch(u16, 2, c->eip);
762 break;
763 case 1:
764 c->modrm_ea += insn_fetch(s8, 1, c->eip);
765 break;
766 case 2:
767 c->modrm_ea += insn_fetch(u16, 2, c->eip);
768 break;
769 }
770 switch (c->modrm_rm) {
771 case 0:
772 c->modrm_ea += bx + si;
773 break;
774 case 1:
775 c->modrm_ea += bx + di;
776 break;
777 case 2:
778 c->modrm_ea += bp + si;
779 break;
780 case 3:
781 c->modrm_ea += bp + di;
782 break;
783 case 4:
784 c->modrm_ea += si;
785 break;
786 case 5:
787 c->modrm_ea += di;
788 break;
789 case 6:
790 if (c->modrm_mod != 0)
791 c->modrm_ea += bp;
792 break;
793 case 7:
794 c->modrm_ea += bx;
795 break;
796 }
797 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
798 (c->modrm_rm == 6 && c->modrm_mod != 0))
799 if (!c->has_seg_override)
800 set_seg_override(c, VCPU_SREG_SS);
801 c->modrm_ea = (u16)c->modrm_ea;
802 } else {
803 /* 32/64-bit ModR/M decode. */
804 if ((c->modrm_rm & 7) == 4) {
805 sib = insn_fetch(u8, 1, c->eip);
806 index_reg |= (sib >> 3) & 7;
807 base_reg |= sib & 7;
808 scale = sib >> 6;
809
810 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
811 c->modrm_ea += insn_fetch(s32, 4, c->eip);
812 else
813 c->modrm_ea += c->regs[base_reg];
814 if (index_reg != 4)
815 c->modrm_ea += c->regs[index_reg] << scale;
816 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
817 if (ctxt->mode == X86EMUL_MODE_PROT64)
818 c->rip_relative = 1;
819 } else
820 c->modrm_ea += c->regs[c->modrm_rm];
821 switch (c->modrm_mod) {
822 case 0:
823 if (c->modrm_rm == 5)
824 c->modrm_ea += insn_fetch(s32, 4, c->eip);
825 break;
826 case 1:
827 c->modrm_ea += insn_fetch(s8, 1, c->eip);
828 break;
829 case 2:
830 c->modrm_ea += insn_fetch(s32, 4, c->eip);
831 break;
832 }
833 }
834 done:
835 return rc;
836 }
837
838 static int decode_abs(struct x86_emulate_ctxt *ctxt,
839 struct x86_emulate_ops *ops)
840 {
841 struct decode_cache *c = &ctxt->decode;
842 int rc = 0;
843
844 switch (c->ad_bytes) {
845 case 2:
846 c->modrm_ea = insn_fetch(u16, 2, c->eip);
847 break;
848 case 4:
849 c->modrm_ea = insn_fetch(u32, 4, c->eip);
850 break;
851 case 8:
852 c->modrm_ea = insn_fetch(u64, 8, c->eip);
853 break;
854 }
855 done:
856 return rc;
857 }
858
859 int
860 x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
861 {
862 struct decode_cache *c = &ctxt->decode;
863 int rc = 0;
864 int mode = ctxt->mode;
865 int def_op_bytes, def_ad_bytes, group;
866
867 /* Shadow copy of register state. Committed on successful emulation. */
868
869 memset(c, 0, sizeof(struct decode_cache));
870 c->eip = c->eip_orig = kvm_rip_read(ctxt->vcpu);
871 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
872 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
873
874 switch (mode) {
875 case X86EMUL_MODE_REAL:
876 case X86EMUL_MODE_PROT16:
877 def_op_bytes = def_ad_bytes = 2;
878 break;
879 case X86EMUL_MODE_PROT32:
880 def_op_bytes = def_ad_bytes = 4;
881 break;
882 #ifdef CONFIG_X86_64
883 case X86EMUL_MODE_PROT64:
884 def_op_bytes = 4;
885 def_ad_bytes = 8;
886 break;
887 #endif
888 default:
889 return -1;
890 }
891
892 c->op_bytes = def_op_bytes;
893 c->ad_bytes = def_ad_bytes;
894
895 /* Legacy prefixes. */
896 for (;;) {
897 switch (c->b = insn_fetch(u8, 1, c->eip)) {
898 case 0x66: /* operand-size override */
899 /* switch between 2/4 bytes */
900 c->op_bytes = def_op_bytes ^ 6;
901 break;
902 case 0x67: /* address-size override */
903 if (mode == X86EMUL_MODE_PROT64)
904 /* switch between 4/8 bytes */
905 c->ad_bytes = def_ad_bytes ^ 12;
906 else
907 /* switch between 2/4 bytes */
908 c->ad_bytes = def_ad_bytes ^ 6;
909 break;
910 case 0x26: /* ES override */
911 case 0x2e: /* CS override */
912 case 0x36: /* SS override */
913 case 0x3e: /* DS override */
914 set_seg_override(c, (c->b >> 3) & 3);
915 break;
916 case 0x64: /* FS override */
917 case 0x65: /* GS override */
918 set_seg_override(c, c->b & 7);
919 break;
920 case 0x40 ... 0x4f: /* REX */
921 if (mode != X86EMUL_MODE_PROT64)
922 goto done_prefixes;
923 c->rex_prefix = c->b;
924 continue;
925 case 0xf0: /* LOCK */
926 c->lock_prefix = 1;
927 break;
928 case 0xf2: /* REPNE/REPNZ */
929 c->rep_prefix = REPNE_PREFIX;
930 break;
931 case 0xf3: /* REP/REPE/REPZ */
932 c->rep_prefix = REPE_PREFIX;
933 break;
934 default:
935 goto done_prefixes;
936 }
937
938 /* Any legacy prefix after a REX prefix nullifies its effect. */
939
940 c->rex_prefix = 0;
941 }
942
943 done_prefixes:
944
945 /* REX prefix. */
946 if (c->rex_prefix)
947 if (c->rex_prefix & 8)
948 c->op_bytes = 8; /* REX.W */
949
950 /* Opcode byte(s). */
951 c->d = opcode_table[c->b];
952 if (c->d == 0) {
953 /* Two-byte opcode? */
954 if (c->b == 0x0f) {
955 c->twobyte = 1;
956 c->b = insn_fetch(u8, 1, c->eip);
957 c->d = twobyte_table[c->b];
958 }
959 }
960
961 if (c->d & Group) {
962 group = c->d & GroupMask;
963 c->modrm = insn_fetch(u8, 1, c->eip);
964 --c->eip;
965
966 group = (group << 3) + ((c->modrm >> 3) & 7);
967 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
968 c->d = group2_table[group];
969 else
970 c->d = group_table[group];
971 }
972
973 /* Unrecognised? */
974 if (c->d == 0) {
975 DPRINTF("Cannot emulate %02x\n", c->b);
976 return -1;
977 }
978
979 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
980 c->op_bytes = 8;
981
982 /* ModRM and SIB bytes. */
983 if (c->d & ModRM)
984 rc = decode_modrm(ctxt, ops);
985 else if (c->d & MemAbs)
986 rc = decode_abs(ctxt, ops);
987 if (rc)
988 goto done;
989
990 if (!c->has_seg_override)
991 set_seg_override(c, VCPU_SREG_DS);
992
993 if (!(!c->twobyte && c->b == 0x8d))
994 c->modrm_ea += seg_override_base(ctxt, c);
995
996 if (c->ad_bytes != 8)
997 c->modrm_ea = (u32)c->modrm_ea;
998 /*
999 * Decode and fetch the source operand: register, memory
1000 * or immediate.
1001 */
1002 switch (c->d & SrcMask) {
1003 case SrcNone:
1004 break;
1005 case SrcReg:
1006 decode_register_operand(&c->src, c, 0);
1007 break;
1008 case SrcMem16:
1009 c->src.bytes = 2;
1010 goto srcmem_common;
1011 case SrcMem32:
1012 c->src.bytes = 4;
1013 goto srcmem_common;
1014 case SrcMem:
1015 c->src.bytes = (c->d & ByteOp) ? 1 :
1016 c->op_bytes;
1017 /* Don't fetch the address for invlpg: it could be unmapped. */
1018 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
1019 break;
1020 srcmem_common:
1021 /*
1022 * For instructions with a ModR/M byte, switch to register
1023 * access if Mod = 3.
1024 */
1025 if ((c->d & ModRM) && c->modrm_mod == 3) {
1026 c->src.type = OP_REG;
1027 c->src.val = c->modrm_val;
1028 c->src.ptr = c->modrm_ptr;
1029 break;
1030 }
1031 c->src.type = OP_MEM;
1032 break;
1033 case SrcImm:
1034 case SrcImmU:
1035 c->src.type = OP_IMM;
1036 c->src.ptr = (unsigned long *)c->eip;
1037 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1038 if (c->src.bytes == 8)
1039 c->src.bytes = 4;
1040 /* NB. Immediates are sign-extended as necessary. */
1041 switch (c->src.bytes) {
1042 case 1:
1043 c->src.val = insn_fetch(s8, 1, c->eip);
1044 break;
1045 case 2:
1046 c->src.val = insn_fetch(s16, 2, c->eip);
1047 break;
1048 case 4:
1049 c->src.val = insn_fetch(s32, 4, c->eip);
1050 break;
1051 }
1052 if ((c->d & SrcMask) == SrcImmU) {
1053 switch (c->src.bytes) {
1054 case 1:
1055 c->src.val &= 0xff;
1056 break;
1057 case 2:
1058 c->src.val &= 0xffff;
1059 break;
1060 case 4:
1061 c->src.val &= 0xffffffff;
1062 break;
1063 }
1064 }
1065 break;
1066 case SrcImmByte:
1067 case SrcImmUByte:
1068 c->src.type = OP_IMM;
1069 c->src.ptr = (unsigned long *)c->eip;
1070 c->src.bytes = 1;
1071 if ((c->d & SrcMask) == SrcImmByte)
1072 c->src.val = insn_fetch(s8, 1, c->eip);
1073 else
1074 c->src.val = insn_fetch(u8, 1, c->eip);
1075 break;
1076 case SrcOne:
1077 c->src.bytes = 1;
1078 c->src.val = 1;
1079 break;
1080 }
1081
1082 /*
1083 * Decode and fetch the second source operand: register, memory
1084 * or immediate.
1085 */
1086 switch (c->d & Src2Mask) {
1087 case Src2None:
1088 break;
1089 case Src2CL:
1090 c->src2.bytes = 1;
1091 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1092 break;
1093 case Src2ImmByte:
1094 c->src2.type = OP_IMM;
1095 c->src2.ptr = (unsigned long *)c->eip;
1096 c->src2.bytes = 1;
1097 c->src2.val = insn_fetch(u8, 1, c->eip);
1098 break;
1099 case Src2Imm16:
1100 c->src2.type = OP_IMM;
1101 c->src2.ptr = (unsigned long *)c->eip;
1102 c->src2.bytes = 2;
1103 c->src2.val = insn_fetch(u16, 2, c->eip);
1104 break;
1105 case Src2One:
1106 c->src2.bytes = 1;
1107 c->src2.val = 1;
1108 break;
1109 }
1110
1111 /* Decode and fetch the destination operand: register or memory. */
1112 switch (c->d & DstMask) {
1113 case ImplicitOps:
1114 /* Special instructions do their own operand decoding. */
1115 return 0;
1116 case DstReg:
1117 decode_register_operand(&c->dst, c,
1118 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
1119 break;
1120 case DstMem:
1121 if ((c->d & ModRM) && c->modrm_mod == 3) {
1122 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1123 c->dst.type = OP_REG;
1124 c->dst.val = c->dst.orig_val = c->modrm_val;
1125 c->dst.ptr = c->modrm_ptr;
1126 break;
1127 }
1128 c->dst.type = OP_MEM;
1129 break;
1130 case DstAcc:
1131 c->dst.type = OP_REG;
1132 c->dst.bytes = c->op_bytes;
1133 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1134 switch (c->op_bytes) {
1135 case 1:
1136 c->dst.val = *(u8 *)c->dst.ptr;
1137 break;
1138 case 2:
1139 c->dst.val = *(u16 *)c->dst.ptr;
1140 break;
1141 case 4:
1142 c->dst.val = *(u32 *)c->dst.ptr;
1143 break;
1144 }
1145 c->dst.orig_val = c->dst.val;
1146 break;
1147 }
1148
1149 if (c->rip_relative)
1150 c->modrm_ea += c->eip;
1151
1152 done:
1153 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1154 }
1155
1156 static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1157 {
1158 struct decode_cache *c = &ctxt->decode;
1159
1160 c->dst.type = OP_MEM;
1161 c->dst.bytes = c->op_bytes;
1162 c->dst.val = c->src.val;
1163 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1164 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
1165 c->regs[VCPU_REGS_RSP]);
1166 }
1167
1168 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1169 struct x86_emulate_ops *ops,
1170 void *dest, int len)
1171 {
1172 struct decode_cache *c = &ctxt->decode;
1173 int rc;
1174
1175 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1176 c->regs[VCPU_REGS_RSP]),
1177 dest, len, ctxt->vcpu);
1178 if (rc != 0)
1179 return rc;
1180
1181 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1182 return rc;
1183 }
1184
1185 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1186 struct x86_emulate_ops *ops)
1187 {
1188 struct decode_cache *c = &ctxt->decode;
1189 int rc;
1190
1191 rc = emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1192 if (rc != 0)
1193 return rc;
1194 return 0;
1195 }
1196
1197 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1198 {
1199 struct decode_cache *c = &ctxt->decode;
1200 switch (c->modrm_reg) {
1201 case 0: /* rol */
1202 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1203 break;
1204 case 1: /* ror */
1205 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1206 break;
1207 case 2: /* rcl */
1208 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1209 break;
1210 case 3: /* rcr */
1211 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1212 break;
1213 case 4: /* sal/shl */
1214 case 6: /* sal/shl */
1215 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1216 break;
1217 case 5: /* shr */
1218 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1219 break;
1220 case 7: /* sar */
1221 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1222 break;
1223 }
1224 }
1225
1226 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1227 struct x86_emulate_ops *ops)
1228 {
1229 struct decode_cache *c = &ctxt->decode;
1230 int rc = 0;
1231
1232 switch (c->modrm_reg) {
1233 case 0 ... 1: /* test */
1234 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1235 break;
1236 case 2: /* not */
1237 c->dst.val = ~c->dst.val;
1238 break;
1239 case 3: /* neg */
1240 emulate_1op("neg", c->dst, ctxt->eflags);
1241 break;
1242 default:
1243 DPRINTF("Cannot emulate %02x\n", c->b);
1244 rc = X86EMUL_UNHANDLEABLE;
1245 break;
1246 }
1247 return rc;
1248 }
1249
1250 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1251 struct x86_emulate_ops *ops)
1252 {
1253 struct decode_cache *c = &ctxt->decode;
1254
1255 switch (c->modrm_reg) {
1256 case 0: /* inc */
1257 emulate_1op("inc", c->dst, ctxt->eflags);
1258 break;
1259 case 1: /* dec */
1260 emulate_1op("dec", c->dst, ctxt->eflags);
1261 break;
1262 case 2: /* call near abs */ {
1263 long int old_eip;
1264 old_eip = c->eip;
1265 c->eip = c->src.val;
1266 c->src.val = old_eip;
1267 emulate_push(ctxt);
1268 break;
1269 }
1270 case 4: /* jmp abs */
1271 c->eip = c->src.val;
1272 break;
1273 case 6: /* push */
1274 emulate_push(ctxt);
1275 break;
1276 }
1277 return 0;
1278 }
1279
1280 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1281 struct x86_emulate_ops *ops,
1282 unsigned long memop)
1283 {
1284 struct decode_cache *c = &ctxt->decode;
1285 u64 old, new;
1286 int rc;
1287
1288 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
1289 if (rc != 0)
1290 return rc;
1291
1292 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1293 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1294
1295 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1296 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1297 ctxt->eflags &= ~EFLG_ZF;
1298
1299 } else {
1300 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1301 (u32) c->regs[VCPU_REGS_RBX];
1302
1303 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
1304 if (rc != 0)
1305 return rc;
1306 ctxt->eflags |= EFLG_ZF;
1307 }
1308 return 0;
1309 }
1310
1311 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1312 struct x86_emulate_ops *ops)
1313 {
1314 struct decode_cache *c = &ctxt->decode;
1315 int rc;
1316 unsigned long cs;
1317
1318 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1319 if (rc)
1320 return rc;
1321 if (c->op_bytes == 4)
1322 c->eip = (u32)c->eip;
1323 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1324 if (rc)
1325 return rc;
1326 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)cs, 1, VCPU_SREG_CS);
1327 return rc;
1328 }
1329
1330 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1331 struct x86_emulate_ops *ops)
1332 {
1333 int rc;
1334 struct decode_cache *c = &ctxt->decode;
1335
1336 switch (c->dst.type) {
1337 case OP_REG:
1338 /* The 4-byte case *is* correct:
1339 * in 64-bit mode we zero-extend.
1340 */
1341 switch (c->dst.bytes) {
1342 case 1:
1343 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1344 break;
1345 case 2:
1346 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1347 break;
1348 case 4:
1349 *c->dst.ptr = (u32)c->dst.val;
1350 break; /* 64b: zero-ext */
1351 case 8:
1352 *c->dst.ptr = c->dst.val;
1353 break;
1354 }
1355 break;
1356 case OP_MEM:
1357 if (c->lock_prefix)
1358 rc = ops->cmpxchg_emulated(
1359 (unsigned long)c->dst.ptr,
1360 &c->dst.orig_val,
1361 &c->dst.val,
1362 c->dst.bytes,
1363 ctxt->vcpu);
1364 else
1365 rc = ops->write_emulated(
1366 (unsigned long)c->dst.ptr,
1367 &c->dst.val,
1368 c->dst.bytes,
1369 ctxt->vcpu);
1370 if (rc != 0)
1371 return rc;
1372 break;
1373 case OP_NONE:
1374 /* no writeback */
1375 break;
1376 default:
1377 break;
1378 }
1379 return 0;
1380 }
1381
1382 static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
1383 {
1384 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask);
1385 /*
1386 * an sti; sti; sequence only disable interrupts for the first
1387 * instruction. So, if the last instruction, be it emulated or
1388 * not, left the system with the INT_STI flag enabled, it
1389 * means that the last instruction is an sti. We should not
1390 * leave the flag on in this case. The same goes for mov ss
1391 */
1392 if (!(int_shadow & mask))
1393 ctxt->interruptibility = mask;
1394 }
1395
1396 int
1397 x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1398 {
1399 unsigned long memop = 0;
1400 u64 msr_data;
1401 unsigned long saved_eip = 0;
1402 struct decode_cache *c = &ctxt->decode;
1403 unsigned int port;
1404 int io_dir_in;
1405 int rc = 0;
1406
1407 ctxt->interruptibility = 0;
1408
1409 /* Shadow copy of register state. Committed on successful emulation.
1410 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1411 * modify them.
1412 */
1413
1414 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
1415 saved_eip = c->eip;
1416
1417 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
1418 memop = c->modrm_ea;
1419
1420 if (c->rep_prefix && (c->d & String)) {
1421 /* All REP prefixes have the same first termination condition */
1422 if (c->regs[VCPU_REGS_RCX] == 0) {
1423 kvm_rip_write(ctxt->vcpu, c->eip);
1424 goto done;
1425 }
1426 /* The second termination condition only applies for REPE
1427 * and REPNE. Test if the repeat string operation prefix is
1428 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1429 * corresponding termination condition according to:
1430 * - if REPE/REPZ and ZF = 0 then done
1431 * - if REPNE/REPNZ and ZF = 1 then done
1432 */
1433 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1434 (c->b == 0xae) || (c->b == 0xaf)) {
1435 if ((c->rep_prefix == REPE_PREFIX) &&
1436 ((ctxt->eflags & EFLG_ZF) == 0)) {
1437 kvm_rip_write(ctxt->vcpu, c->eip);
1438 goto done;
1439 }
1440 if ((c->rep_prefix == REPNE_PREFIX) &&
1441 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
1442 kvm_rip_write(ctxt->vcpu, c->eip);
1443 goto done;
1444 }
1445 }
1446 c->regs[VCPU_REGS_RCX]--;
1447 c->eip = kvm_rip_read(ctxt->vcpu);
1448 }
1449
1450 if (c->src.type == OP_MEM) {
1451 c->src.ptr = (unsigned long *)memop;
1452 c->src.val = 0;
1453 rc = ops->read_emulated((unsigned long)c->src.ptr,
1454 &c->src.val,
1455 c->src.bytes,
1456 ctxt->vcpu);
1457 if (rc != 0)
1458 goto done;
1459 c->src.orig_val = c->src.val;
1460 }
1461
1462 if ((c->d & DstMask) == ImplicitOps)
1463 goto special_insn;
1464
1465
1466 if (c->dst.type == OP_MEM) {
1467 c->dst.ptr = (unsigned long *)memop;
1468 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1469 c->dst.val = 0;
1470 if (c->d & BitOp) {
1471 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1472
1473 c->dst.ptr = (void *)c->dst.ptr +
1474 (c->src.val & mask) / 8;
1475 }
1476 if (!(c->d & Mov) &&
1477 /* optimisation - avoid slow emulated read */
1478 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1479 &c->dst.val,
1480 c->dst.bytes, ctxt->vcpu)) != 0))
1481 goto done;
1482 }
1483 c->dst.orig_val = c->dst.val;
1484
1485 special_insn:
1486
1487 if (c->twobyte)
1488 goto twobyte_insn;
1489
1490 switch (c->b) {
1491 case 0x00 ... 0x05:
1492 add: /* add */
1493 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
1494 break;
1495 case 0x08 ... 0x0d:
1496 or: /* or */
1497 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
1498 break;
1499 case 0x10 ... 0x15:
1500 adc: /* adc */
1501 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
1502 break;
1503 case 0x18 ... 0x1d:
1504 sbb: /* sbb */
1505 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
1506 break;
1507 case 0x20 ... 0x25:
1508 and: /* and */
1509 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
1510 break;
1511 case 0x28 ... 0x2d:
1512 sub: /* sub */
1513 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
1514 break;
1515 case 0x30 ... 0x35:
1516 xor: /* xor */
1517 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
1518 break;
1519 case 0x38 ... 0x3d:
1520 cmp: /* cmp */
1521 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1522 break;
1523 case 0x40 ... 0x47: /* inc r16/r32 */
1524 emulate_1op("inc", c->dst, ctxt->eflags);
1525 break;
1526 case 0x48 ... 0x4f: /* dec r16/r32 */
1527 emulate_1op("dec", c->dst, ctxt->eflags);
1528 break;
1529 case 0x50 ... 0x57: /* push reg */
1530 emulate_push(ctxt);
1531 break;
1532 case 0x58 ... 0x5f: /* pop reg */
1533 pop_instruction:
1534 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1535 if (rc != 0)
1536 goto done;
1537 break;
1538 case 0x63: /* movsxd */
1539 if (ctxt->mode != X86EMUL_MODE_PROT64)
1540 goto cannot_emulate;
1541 c->dst.val = (s32) c->src.val;
1542 break;
1543 case 0x68: /* push imm */
1544 case 0x6a: /* push imm8 */
1545 emulate_push(ctxt);
1546 break;
1547 case 0x6c: /* insb */
1548 case 0x6d: /* insw/insd */
1549 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1550 1,
1551 (c->d & ByteOp) ? 1 : c->op_bytes,
1552 c->rep_prefix ?
1553 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1554 (ctxt->eflags & EFLG_DF),
1555 register_address(c, es_base(ctxt),
1556 c->regs[VCPU_REGS_RDI]),
1557 c->rep_prefix,
1558 c->regs[VCPU_REGS_RDX]) == 0) {
1559 c->eip = saved_eip;
1560 return -1;
1561 }
1562 return 0;
1563 case 0x6e: /* outsb */
1564 case 0x6f: /* outsw/outsd */
1565 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1566 0,
1567 (c->d & ByteOp) ? 1 : c->op_bytes,
1568 c->rep_prefix ?
1569 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1570 (ctxt->eflags & EFLG_DF),
1571 register_address(c,
1572 seg_override_base(ctxt, c),
1573 c->regs[VCPU_REGS_RSI]),
1574 c->rep_prefix,
1575 c->regs[VCPU_REGS_RDX]) == 0) {
1576 c->eip = saved_eip;
1577 return -1;
1578 }
1579 return 0;
1580 case 0x70 ... 0x7f: /* jcc (short) */
1581 if (test_cc(c->b, ctxt->eflags))
1582 jmp_rel(c, c->src.val);
1583 break;
1584 case 0x80 ... 0x83: /* Grp1 */
1585 switch (c->modrm_reg) {
1586 case 0:
1587 goto add;
1588 case 1:
1589 goto or;
1590 case 2:
1591 goto adc;
1592 case 3:
1593 goto sbb;
1594 case 4:
1595 goto and;
1596 case 5:
1597 goto sub;
1598 case 6:
1599 goto xor;
1600 case 7:
1601 goto cmp;
1602 }
1603 break;
1604 case 0x84 ... 0x85:
1605 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1606 break;
1607 case 0x86 ... 0x87: /* xchg */
1608 xchg:
1609 /* Write back the register source. */
1610 switch (c->dst.bytes) {
1611 case 1:
1612 *(u8 *) c->src.ptr = (u8) c->dst.val;
1613 break;
1614 case 2:
1615 *(u16 *) c->src.ptr = (u16) c->dst.val;
1616 break;
1617 case 4:
1618 *c->src.ptr = (u32) c->dst.val;
1619 break; /* 64b reg: zero-extend */
1620 case 8:
1621 *c->src.ptr = c->dst.val;
1622 break;
1623 }
1624 /*
1625 * Write back the memory destination with implicit LOCK
1626 * prefix.
1627 */
1628 c->dst.val = c->src.val;
1629 c->lock_prefix = 1;
1630 break;
1631 case 0x88 ... 0x8b: /* mov */
1632 goto mov;
1633 case 0x8c: { /* mov r/m, sreg */
1634 struct kvm_segment segreg;
1635
1636 if (c->modrm_reg <= 5)
1637 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1638 else {
1639 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1640 c->modrm);
1641 goto cannot_emulate;
1642 }
1643 c->dst.val = segreg.selector;
1644 break;
1645 }
1646 case 0x8d: /* lea r16/r32, m */
1647 c->dst.val = c->modrm_ea;
1648 break;
1649 case 0x8e: { /* mov seg, r/m16 */
1650 uint16_t sel;
1651 int type_bits;
1652 int err;
1653
1654 sel = c->src.val;
1655 if (c->modrm_reg == VCPU_SREG_SS)
1656 toggle_interruptibility(ctxt, X86_SHADOW_INT_MOV_SS);
1657
1658 if (c->modrm_reg <= 5) {
1659 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1660 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1661 type_bits, c->modrm_reg);
1662 } else {
1663 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1664 c->modrm);
1665 goto cannot_emulate;
1666 }
1667
1668 if (err < 0)
1669 goto cannot_emulate;
1670
1671 c->dst.type = OP_NONE; /* Disable writeback. */
1672 break;
1673 }
1674 case 0x8f: /* pop (sole member of Grp1a) */
1675 rc = emulate_grp1a(ctxt, ops);
1676 if (rc != 0)
1677 goto done;
1678 break;
1679 case 0x90: /* nop / xchg r8,rax */
1680 if (!(c->rex_prefix & 1)) { /* nop */
1681 c->dst.type = OP_NONE;
1682 break;
1683 }
1684 case 0x91 ... 0x97: /* xchg reg,rax */
1685 c->src.type = c->dst.type = OP_REG;
1686 c->src.bytes = c->dst.bytes = c->op_bytes;
1687 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1688 c->src.val = *(c->src.ptr);
1689 goto xchg;
1690 case 0x9c: /* pushf */
1691 c->src.val = (unsigned long) ctxt->eflags;
1692 emulate_push(ctxt);
1693 break;
1694 case 0x9d: /* popf */
1695 c->dst.type = OP_REG;
1696 c->dst.ptr = (unsigned long *) &ctxt->eflags;
1697 c->dst.bytes = c->op_bytes;
1698 goto pop_instruction;
1699 case 0xa0 ... 0xa1: /* mov */
1700 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1701 c->dst.val = c->src.val;
1702 break;
1703 case 0xa2 ... 0xa3: /* mov */
1704 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1705 break;
1706 case 0xa4 ... 0xa5: /* movs */
1707 c->dst.type = OP_MEM;
1708 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1709 c->dst.ptr = (unsigned long *)register_address(c,
1710 es_base(ctxt),
1711 c->regs[VCPU_REGS_RDI]);
1712 if ((rc = ops->read_emulated(register_address(c,
1713 seg_override_base(ctxt, c),
1714 c->regs[VCPU_REGS_RSI]),
1715 &c->dst.val,
1716 c->dst.bytes, ctxt->vcpu)) != 0)
1717 goto done;
1718 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1719 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1720 : c->dst.bytes);
1721 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1722 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1723 : c->dst.bytes);
1724 break;
1725 case 0xa6 ... 0xa7: /* cmps */
1726 c->src.type = OP_NONE; /* Disable writeback. */
1727 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1728 c->src.ptr = (unsigned long *)register_address(c,
1729 seg_override_base(ctxt, c),
1730 c->regs[VCPU_REGS_RSI]);
1731 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1732 &c->src.val,
1733 c->src.bytes,
1734 ctxt->vcpu)) != 0)
1735 goto done;
1736
1737 c->dst.type = OP_NONE; /* Disable writeback. */
1738 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1739 c->dst.ptr = (unsigned long *)register_address(c,
1740 es_base(ctxt),
1741 c->regs[VCPU_REGS_RDI]);
1742 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1743 &c->dst.val,
1744 c->dst.bytes,
1745 ctxt->vcpu)) != 0)
1746 goto done;
1747
1748 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1749
1750 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1751
1752 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1753 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1754 : c->src.bytes);
1755 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1756 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1757 : c->dst.bytes);
1758
1759 break;
1760 case 0xaa ... 0xab: /* stos */
1761 c->dst.type = OP_MEM;
1762 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1763 c->dst.ptr = (unsigned long *)register_address(c,
1764 es_base(ctxt),
1765 c->regs[VCPU_REGS_RDI]);
1766 c->dst.val = c->regs[VCPU_REGS_RAX];
1767 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1768 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1769 : c->dst.bytes);
1770 break;
1771 case 0xac ... 0xad: /* lods */
1772 c->dst.type = OP_REG;
1773 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1774 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1775 if ((rc = ops->read_emulated(register_address(c,
1776 seg_override_base(ctxt, c),
1777 c->regs[VCPU_REGS_RSI]),
1778 &c->dst.val,
1779 c->dst.bytes,
1780 ctxt->vcpu)) != 0)
1781 goto done;
1782 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1783 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1784 : c->dst.bytes);
1785 break;
1786 case 0xae ... 0xaf: /* scas */
1787 DPRINTF("Urk! I don't handle SCAS.\n");
1788 goto cannot_emulate;
1789 case 0xb0 ... 0xbf: /* mov r, imm */
1790 goto mov;
1791 case 0xc0 ... 0xc1:
1792 emulate_grp2(ctxt);
1793 break;
1794 case 0xc3: /* ret */
1795 c->dst.type = OP_REG;
1796 c->dst.ptr = &c->eip;
1797 c->dst.bytes = c->op_bytes;
1798 goto pop_instruction;
1799 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1800 mov:
1801 c->dst.val = c->src.val;
1802 break;
1803 case 0xcb: /* ret far */
1804 rc = emulate_ret_far(ctxt, ops);
1805 if (rc)
1806 goto done;
1807 break;
1808 case 0xd0 ... 0xd1: /* Grp2 */
1809 c->src.val = 1;
1810 emulate_grp2(ctxt);
1811 break;
1812 case 0xd2 ... 0xd3: /* Grp2 */
1813 c->src.val = c->regs[VCPU_REGS_RCX];
1814 emulate_grp2(ctxt);
1815 break;
1816 case 0xe4: /* inb */
1817 case 0xe5: /* in */
1818 port = c->src.val;
1819 io_dir_in = 1;
1820 goto do_io;
1821 case 0xe6: /* outb */
1822 case 0xe7: /* out */
1823 port = c->src.val;
1824 io_dir_in = 0;
1825 goto do_io;
1826 case 0xe8: /* call (near) */ {
1827 long int rel = c->src.val;
1828 c->src.val = (unsigned long) c->eip;
1829 jmp_rel(c, rel);
1830 emulate_push(ctxt);
1831 break;
1832 }
1833 case 0xe9: /* jmp rel */
1834 goto jmp;
1835 case 0xea: /* jmp far */
1836 if (kvm_load_segment_descriptor(ctxt->vcpu, c->src2.val, 9,
1837 VCPU_SREG_CS) < 0) {
1838 DPRINTF("jmp far: Failed to load CS descriptor\n");
1839 goto cannot_emulate;
1840 }
1841
1842 c->eip = c->src.val;
1843 break;
1844 case 0xeb:
1845 jmp: /* jmp rel short */
1846 jmp_rel(c, c->src.val);
1847 c->dst.type = OP_NONE; /* Disable writeback. */
1848 break;
1849 case 0xec: /* in al,dx */
1850 case 0xed: /* in (e/r)ax,dx */
1851 port = c->regs[VCPU_REGS_RDX];
1852 io_dir_in = 1;
1853 goto do_io;
1854 case 0xee: /* out al,dx */
1855 case 0xef: /* out (e/r)ax,dx */
1856 port = c->regs[VCPU_REGS_RDX];
1857 io_dir_in = 0;
1858 do_io: if (kvm_emulate_pio(ctxt->vcpu, NULL, io_dir_in,
1859 (c->d & ByteOp) ? 1 : c->op_bytes,
1860 port) != 0) {
1861 c->eip = saved_eip;
1862 goto cannot_emulate;
1863 }
1864 break;
1865 case 0xf4: /* hlt */
1866 ctxt->vcpu->arch.halt_request = 1;
1867 break;
1868 case 0xf5: /* cmc */
1869 /* complement carry flag from eflags reg */
1870 ctxt->eflags ^= EFLG_CF;
1871 c->dst.type = OP_NONE; /* Disable writeback. */
1872 break;
1873 case 0xf6 ... 0xf7: /* Grp3 */
1874 rc = emulate_grp3(ctxt, ops);
1875 if (rc != 0)
1876 goto done;
1877 break;
1878 case 0xf8: /* clc */
1879 ctxt->eflags &= ~EFLG_CF;
1880 c->dst.type = OP_NONE; /* Disable writeback. */
1881 break;
1882 case 0xfa: /* cli */
1883 ctxt->eflags &= ~X86_EFLAGS_IF;
1884 c->dst.type = OP_NONE; /* Disable writeback. */
1885 break;
1886 case 0xfb: /* sti */
1887 toggle_interruptibility(ctxt, X86_SHADOW_INT_STI);
1888 ctxt->eflags |= X86_EFLAGS_IF;
1889 c->dst.type = OP_NONE; /* Disable writeback. */
1890 break;
1891 case 0xfc: /* cld */
1892 ctxt->eflags &= ~EFLG_DF;
1893 c->dst.type = OP_NONE; /* Disable writeback. */
1894 break;
1895 case 0xfd: /* std */
1896 ctxt->eflags |= EFLG_DF;
1897 c->dst.type = OP_NONE; /* Disable writeback. */
1898 break;
1899 case 0xfe ... 0xff: /* Grp4/Grp5 */
1900 rc = emulate_grp45(ctxt, ops);
1901 if (rc != 0)
1902 goto done;
1903 break;
1904 }
1905
1906 writeback:
1907 rc = writeback(ctxt, ops);
1908 if (rc != 0)
1909 goto done;
1910
1911 /* Commit shadow register state. */
1912 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
1913 kvm_rip_write(ctxt->vcpu, c->eip);
1914
1915 done:
1916 if (rc == X86EMUL_UNHANDLEABLE) {
1917 c->eip = saved_eip;
1918 return -1;
1919 }
1920 return 0;
1921
1922 twobyte_insn:
1923 switch (c->b) {
1924 case 0x01: /* lgdt, lidt, lmsw */
1925 switch (c->modrm_reg) {
1926 u16 size;
1927 unsigned long address;
1928
1929 case 0: /* vmcall */
1930 if (c->modrm_mod != 3 || c->modrm_rm != 1)
1931 goto cannot_emulate;
1932
1933 rc = kvm_fix_hypercall(ctxt->vcpu);
1934 if (rc)
1935 goto done;
1936
1937 /* Let the processor re-execute the fixed hypercall */
1938 c->eip = kvm_rip_read(ctxt->vcpu);
1939 /* Disable writeback. */
1940 c->dst.type = OP_NONE;
1941 break;
1942 case 2: /* lgdt */
1943 rc = read_descriptor(ctxt, ops, c->src.ptr,
1944 &size, &address, c->op_bytes);
1945 if (rc)
1946 goto done;
1947 realmode_lgdt(ctxt->vcpu, size, address);
1948 /* Disable writeback. */
1949 c->dst.type = OP_NONE;
1950 break;
1951 case 3: /* lidt/vmmcall */
1952 if (c->modrm_mod == 3) {
1953 switch (c->modrm_rm) {
1954 case 1:
1955 rc = kvm_fix_hypercall(ctxt->vcpu);
1956 if (rc)
1957 goto done;
1958 break;
1959 default:
1960 goto cannot_emulate;
1961 }
1962 } else {
1963 rc = read_descriptor(ctxt, ops, c->src.ptr,
1964 &size, &address,
1965 c->op_bytes);
1966 if (rc)
1967 goto done;
1968 realmode_lidt(ctxt->vcpu, size, address);
1969 }
1970 /* Disable writeback. */
1971 c->dst.type = OP_NONE;
1972 break;
1973 case 4: /* smsw */
1974 c->dst.bytes = 2;
1975 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
1976 break;
1977 case 6: /* lmsw */
1978 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1979 &ctxt->eflags);
1980 c->dst.type = OP_NONE;
1981 break;
1982 case 7: /* invlpg*/
1983 emulate_invlpg(ctxt->vcpu, memop);
1984 /* Disable writeback. */
1985 c->dst.type = OP_NONE;
1986 break;
1987 default:
1988 goto cannot_emulate;
1989 }
1990 break;
1991 case 0x06:
1992 emulate_clts(ctxt->vcpu);
1993 c->dst.type = OP_NONE;
1994 break;
1995 case 0x08: /* invd */
1996 case 0x09: /* wbinvd */
1997 case 0x0d: /* GrpP (prefetch) */
1998 case 0x18: /* Grp16 (prefetch/nop) */
1999 c->dst.type = OP_NONE;
2000 break;
2001 case 0x20: /* mov cr, reg */
2002 if (c->modrm_mod != 3)
2003 goto cannot_emulate;
2004 c->regs[c->modrm_rm] =
2005 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
2006 c->dst.type = OP_NONE; /* no writeback */
2007 break;
2008 case 0x21: /* mov from dr to reg */
2009 if (c->modrm_mod != 3)
2010 goto cannot_emulate;
2011 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
2012 if (rc)
2013 goto cannot_emulate;
2014 c->dst.type = OP_NONE; /* no writeback */
2015 break;
2016 case 0x22: /* mov reg, cr */
2017 if (c->modrm_mod != 3)
2018 goto cannot_emulate;
2019 realmode_set_cr(ctxt->vcpu,
2020 c->modrm_reg, c->modrm_val, &ctxt->eflags);
2021 c->dst.type = OP_NONE;
2022 break;
2023 case 0x23: /* mov from reg to dr */
2024 if (c->modrm_mod != 3)
2025 goto cannot_emulate;
2026 rc = emulator_set_dr(ctxt, c->modrm_reg,
2027 c->regs[c->modrm_rm]);
2028 if (rc)
2029 goto cannot_emulate;
2030 c->dst.type = OP_NONE; /* no writeback */
2031 break;
2032 case 0x30:
2033 /* wrmsr */
2034 msr_data = (u32)c->regs[VCPU_REGS_RAX]
2035 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
2036 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
2037 if (rc) {
2038 kvm_inject_gp(ctxt->vcpu, 0);
2039 c->eip = kvm_rip_read(ctxt->vcpu);
2040 }
2041 rc = X86EMUL_CONTINUE;
2042 c->dst.type = OP_NONE;
2043 break;
2044 case 0x32:
2045 /* rdmsr */
2046 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
2047 if (rc) {
2048 kvm_inject_gp(ctxt->vcpu, 0);
2049 c->eip = kvm_rip_read(ctxt->vcpu);
2050 } else {
2051 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
2052 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
2053 }
2054 rc = X86EMUL_CONTINUE;
2055 c->dst.type = OP_NONE;
2056 break;
2057 case 0x40 ... 0x4f: /* cmov */
2058 c->dst.val = c->dst.orig_val = c->src.val;
2059 if (!test_cc(c->b, ctxt->eflags))
2060 c->dst.type = OP_NONE; /* no writeback */
2061 break;
2062 case 0x80 ... 0x8f: /* jnz rel, etc*/
2063 if (test_cc(c->b, ctxt->eflags))
2064 jmp_rel(c, c->src.val);
2065 c->dst.type = OP_NONE;
2066 break;
2067 case 0xa3:
2068 bt: /* bt */
2069 c->dst.type = OP_NONE;
2070 /* only subword offset */
2071 c->src.val &= (c->dst.bytes << 3) - 1;
2072 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
2073 break;
2074 case 0xa4: /* shld imm8, r, r/m */
2075 case 0xa5: /* shld cl, r, r/m */
2076 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
2077 break;
2078 case 0xab:
2079 bts: /* bts */
2080 /* only subword offset */
2081 c->src.val &= (c->dst.bytes << 3) - 1;
2082 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
2083 break;
2084 case 0xac: /* shrd imm8, r, r/m */
2085 case 0xad: /* shrd cl, r, r/m */
2086 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
2087 break;
2088 case 0xae: /* clflush */
2089 break;
2090 case 0xb0 ... 0xb1: /* cmpxchg */
2091 /*
2092 * Save real source value, then compare EAX against
2093 * destination.
2094 */
2095 c->src.orig_val = c->src.val;
2096 c->src.val = c->regs[VCPU_REGS_RAX];
2097 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2098 if (ctxt->eflags & EFLG_ZF) {
2099 /* Success: write back to memory. */
2100 c->dst.val = c->src.orig_val;
2101 } else {
2102 /* Failure: write the value we saw to EAX. */
2103 c->dst.type = OP_REG;
2104 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2105 }
2106 break;
2107 case 0xb3:
2108 btr: /* btr */
2109 /* only subword offset */
2110 c->src.val &= (c->dst.bytes << 3) - 1;
2111 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
2112 break;
2113 case 0xb6 ... 0xb7: /* movzx */
2114 c->dst.bytes = c->op_bytes;
2115 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2116 : (u16) c->src.val;
2117 break;
2118 case 0xba: /* Grp8 */
2119 switch (c->modrm_reg & 3) {
2120 case 0:
2121 goto bt;
2122 case 1:
2123 goto bts;
2124 case 2:
2125 goto btr;
2126 case 3:
2127 goto btc;
2128 }
2129 break;
2130 case 0xbb:
2131 btc: /* btc */
2132 /* only subword offset */
2133 c->src.val &= (c->dst.bytes << 3) - 1;
2134 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
2135 break;
2136 case 0xbe ... 0xbf: /* movsx */
2137 c->dst.bytes = c->op_bytes;
2138 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2139 (s16) c->src.val;
2140 break;
2141 case 0xc3: /* movnti */
2142 c->dst.bytes = c->op_bytes;
2143 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2144 (u64) c->src.val;
2145 break;
2146 case 0xc7: /* Grp9 (cmpxchg8b) */
2147 rc = emulate_grp9(ctxt, ops, memop);
2148 if (rc != 0)
2149 goto done;
2150 c->dst.type = OP_NONE;
2151 break;
2152 }
2153 goto writeback;
2154
2155 cannot_emulate:
2156 DPRINTF("Cannot emulate %02x\n", c->b);
2157 c->eip = saved_eip;
2158 return -1;
2159 }
2160
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