1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "mmu.h"
20
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include "kvm_cache_regs.h"
29 #include "x86.h"
30
31 #include <asm/io.h>
32 #include <asm/desc.h>
33 #include <asm/vmx.h>
34 #include <asm/virtext.h>
35 #include <asm/mce.h>
36
37 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38
39 MODULE_AUTHOR("Qumranet");
40 MODULE_LICENSE("GPL");
41
42 static int __read_mostly bypass_guest_pf = 1;
43 module_param(bypass_guest_pf, bool, S_IRUGO);
44
45 static int __read_mostly enable_vpid = 1;
46 module_param_named(vpid, enable_vpid, bool, 0444);
47
48 static int __read_mostly flexpriority_enabled = 1;
49 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
50
51 static int __read_mostly enable_ept = 1;
52 module_param_named(ept, enable_ept, bool, S_IRUGO);
53
54 static int __read_mostly emulate_invalid_guest_state = 0;
55 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
56
57 struct vmcs {
58 u32 revision_id;
59 u32 abort;
60 char data[0];
61 };
62
63 struct vcpu_vmx {
64 struct kvm_vcpu vcpu;
65 struct list_head local_vcpus_link;
66 unsigned long host_rsp;
67 int launched;
68 u8 fail;
69 u32 idt_vectoring_info;
70 struct kvm_msr_entry *guest_msrs;
71 struct kvm_msr_entry *host_msrs;
72 int nmsrs;
73 int save_nmsrs;
74 int msr_offset_efer;
75 #ifdef CONFIG_X86_64
76 int msr_offset_kernel_gs_base;
77 #endif
78 struct vmcs *vmcs;
79 struct {
80 int loaded;
81 u16 fs_sel, gs_sel, ldt_sel;
82 int gs_ldt_reload_needed;
83 int fs_reload_needed;
84 int guest_efer_loaded;
85 } host_state;
86 struct {
87 struct {
88 bool pending;
89 u8 vector;
90 unsigned rip;
91 } irq;
92 } rmode;
93 int vpid;
94 bool emulation_required;
95 enum emulation_result invalid_state_emulation_result;
96
97 /* Support for vnmi-less CPUs */
98 int soft_vnmi_blocked;
99 ktime_t entry_time;
100 s64 vnmi_blocked_time;
101 u32 exit_reason;
102 };
103
104 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
105 {
106 return container_of(vcpu, struct vcpu_vmx, vcpu);
107 }
108
109 static int init_rmode(struct kvm *kvm);
110 static u64 construct_eptp(unsigned long root_hpa);
111
112 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
113 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
114 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
115
116 static unsigned long *vmx_io_bitmap_a;
117 static unsigned long *vmx_io_bitmap_b;
118 static unsigned long *vmx_msr_bitmap_legacy;
119 static unsigned long *vmx_msr_bitmap_longmode;
120
121 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
122 static DEFINE_SPINLOCK(vmx_vpid_lock);
123
124 static struct vmcs_config {
125 int size;
126 int order;
127 u32 revision_id;
128 u32 pin_based_exec_ctrl;
129 u32 cpu_based_exec_ctrl;
130 u32 cpu_based_2nd_exec_ctrl;
131 u32 vmexit_ctrl;
132 u32 vmentry_ctrl;
133 } vmcs_config;
134
135 static struct vmx_capability {
136 u32 ept;
137 u32 vpid;
138 } vmx_capability;
139
140 #define VMX_SEGMENT_FIELD(seg) \
141 [VCPU_SREG_##seg] = { \
142 .selector = GUEST_##seg##_SELECTOR, \
143 .base = GUEST_##seg##_BASE, \
144 .limit = GUEST_##seg##_LIMIT, \
145 .ar_bytes = GUEST_##seg##_AR_BYTES, \
146 }
147
148 static struct kvm_vmx_segment_field {
149 unsigned selector;
150 unsigned base;
151 unsigned limit;
152 unsigned ar_bytes;
153 } kvm_vmx_segment_fields[] = {
154 VMX_SEGMENT_FIELD(CS),
155 VMX_SEGMENT_FIELD(DS),
156 VMX_SEGMENT_FIELD(ES),
157 VMX_SEGMENT_FIELD(FS),
158 VMX_SEGMENT_FIELD(GS),
159 VMX_SEGMENT_FIELD(SS),
160 VMX_SEGMENT_FIELD(TR),
161 VMX_SEGMENT_FIELD(LDTR),
162 };
163
164 /*
165 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
166 * away by decrementing the array size.
167 */
168 static const u32 vmx_msr_index[] = {
169 #ifdef CONFIG_X86_64
170 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
171 #endif
172 MSR_EFER, MSR_K6_STAR,
173 };
174 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
175
176 static void load_msrs(struct kvm_msr_entry *e, int n)
177 {
178 int i;
179
180 for (i = 0; i < n; ++i)
181 wrmsrl(e[i].index, e[i].data);
182 }
183
184 static void save_msrs(struct kvm_msr_entry *e, int n)
185 {
186 int i;
187
188 for (i = 0; i < n; ++i)
189 rdmsrl(e[i].index, e[i].data);
190 }
191
192 static inline int is_page_fault(u32 intr_info)
193 {
194 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
195 INTR_INFO_VALID_MASK)) ==
196 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
197 }
198
199 static inline int is_no_device(u32 intr_info)
200 {
201 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
202 INTR_INFO_VALID_MASK)) ==
203 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
204 }
205
206 static inline int is_invalid_opcode(u32 intr_info)
207 {
208 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
209 INTR_INFO_VALID_MASK)) ==
210 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
211 }
212
213 static inline int is_external_interrupt(u32 intr_info)
214 {
215 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
216 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
217 }
218
219 static inline int is_machine_check(u32 intr_info)
220 {
221 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
222 INTR_INFO_VALID_MASK)) ==
223 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
224 }
225
226 static inline int cpu_has_vmx_msr_bitmap(void)
227 {
228 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
229 }
230
231 static inline int cpu_has_vmx_tpr_shadow(void)
232 {
233 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
234 }
235
236 static inline int vm_need_tpr_shadow(struct kvm *kvm)
237 {
238 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
239 }
240
241 static inline int cpu_has_secondary_exec_ctrls(void)
242 {
243 return vmcs_config.cpu_based_exec_ctrl &
244 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
245 }
246
247 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
248 {
249 return vmcs_config.cpu_based_2nd_exec_ctrl &
250 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
251 }
252
253 static inline bool cpu_has_vmx_flexpriority(void)
254 {
255 return cpu_has_vmx_tpr_shadow() &&
256 cpu_has_vmx_virtualize_apic_accesses();
257 }
258
259 static inline int cpu_has_vmx_invept_individual_addr(void)
260 {
261 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
262 }
263
264 static inline int cpu_has_vmx_invept_context(void)
265 {
266 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
267 }
268
269 static inline int cpu_has_vmx_invept_global(void)
270 {
271 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
272 }
273
274 static inline int cpu_has_vmx_ept(void)
275 {
276 return vmcs_config.cpu_based_2nd_exec_ctrl &
277 SECONDARY_EXEC_ENABLE_EPT;
278 }
279
280 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
281 {
282 return flexpriority_enabled &&
283 (cpu_has_vmx_virtualize_apic_accesses()) &&
284 (irqchip_in_kernel(kvm));
285 }
286
287 static inline int cpu_has_vmx_vpid(void)
288 {
289 return vmcs_config.cpu_based_2nd_exec_ctrl &
290 SECONDARY_EXEC_ENABLE_VPID;
291 }
292
293 static inline int cpu_has_virtual_nmis(void)
294 {
295 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
296 }
297
298 static inline bool report_flexpriority(void)
299 {
300 return flexpriority_enabled;
301 }
302
303 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
304 {
305 int i;
306
307 for (i = 0; i < vmx->nmsrs; ++i)
308 if (vmx->guest_msrs[i].index == msr)
309 return i;
310 return -1;
311 }
312
313 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
314 {
315 struct {
316 u64 vpid : 16;
317 u64 rsvd : 48;
318 u64 gva;
319 } operand = { vpid, 0, gva };
320
321 asm volatile (__ex(ASM_VMX_INVVPID)
322 /* CF==1 or ZF==1 --> rc = -1 */
323 "; ja 1f ; ud2 ; 1:"
324 : : "a"(&operand), "c"(ext) : "cc", "memory");
325 }
326
327 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
328 {
329 struct {
330 u64 eptp, gpa;
331 } operand = {eptp, gpa};
332
333 asm volatile (__ex(ASM_VMX_INVEPT)
334 /* CF==1 or ZF==1 --> rc = -1 */
335 "; ja 1f ; ud2 ; 1:\n"
336 : : "a" (&operand), "c" (ext) : "cc", "memory");
337 }
338
339 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
340 {
341 int i;
342
343 i = __find_msr_index(vmx, msr);
344 if (i >= 0)
345 return &vmx->guest_msrs[i];
346 return NULL;
347 }
348
349 static void vmcs_clear(struct vmcs *vmcs)
350 {
351 u64 phys_addr = __pa(vmcs);
352 u8 error;
353
354 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
355 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
356 : "cc", "memory");
357 if (error)
358 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
359 vmcs, phys_addr);
360 }
361
362 static void __vcpu_clear(void *arg)
363 {
364 struct vcpu_vmx *vmx = arg;
365 int cpu = raw_smp_processor_id();
366
367 if (vmx->vcpu.cpu == cpu)
368 vmcs_clear(vmx->vmcs);
369 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
370 per_cpu(current_vmcs, cpu) = NULL;
371 rdtscll(vmx->vcpu.arch.host_tsc);
372 list_del(&vmx->local_vcpus_link);
373 vmx->vcpu.cpu = -1;
374 vmx->launched = 0;
375 }
376
377 static void vcpu_clear(struct vcpu_vmx *vmx)
378 {
379 if (vmx->vcpu.cpu == -1)
380 return;
381 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
382 }
383
384 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
385 {
386 if (vmx->vpid == 0)
387 return;
388
389 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
390 }
391
392 static inline void ept_sync_global(void)
393 {
394 if (cpu_has_vmx_invept_global())
395 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
396 }
397
398 static inline void ept_sync_context(u64 eptp)
399 {
400 if (enable_ept) {
401 if (cpu_has_vmx_invept_context())
402 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
403 else
404 ept_sync_global();
405 }
406 }
407
408 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
409 {
410 if (enable_ept) {
411 if (cpu_has_vmx_invept_individual_addr())
412 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
413 eptp, gpa);
414 else
415 ept_sync_context(eptp);
416 }
417 }
418
419 static unsigned long vmcs_readl(unsigned long field)
420 {
421 unsigned long value;
422
423 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
424 : "=a"(value) : "d"(field) : "cc");
425 return value;
426 }
427
428 static u16 vmcs_read16(unsigned long field)
429 {
430 return vmcs_readl(field);
431 }
432
433 static u32 vmcs_read32(unsigned long field)
434 {
435 return vmcs_readl(field);
436 }
437
438 static u64 vmcs_read64(unsigned long field)
439 {
440 #ifdef CONFIG_X86_64
441 return vmcs_readl(field);
442 #else
443 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
444 #endif
445 }
446
447 static noinline void vmwrite_error(unsigned long field, unsigned long value)
448 {
449 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
450 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
451 dump_stack();
452 }
453
454 static void vmcs_writel(unsigned long field, unsigned long value)
455 {
456 u8 error;
457
458 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
459 : "=q"(error) : "a"(value), "d"(field) : "cc");
460 if (unlikely(error))
461 vmwrite_error(field, value);
462 }
463
464 static void vmcs_write16(unsigned long field, u16 value)
465 {
466 vmcs_writel(field, value);
467 }
468
469 static void vmcs_write32(unsigned long field, u32 value)
470 {
471 vmcs_writel(field, value);
472 }
473
474 static void vmcs_write64(unsigned long field, u64 value)
475 {
476 vmcs_writel(field, value);
477 #ifndef CONFIG_X86_64
478 asm volatile ("");
479 vmcs_writel(field+1, value >> 32);
480 #endif
481 }
482
483 static void vmcs_clear_bits(unsigned long field, u32 mask)
484 {
485 vmcs_writel(field, vmcs_readl(field) & ~mask);
486 }
487
488 static void vmcs_set_bits(unsigned long field, u32 mask)
489 {
490 vmcs_writel(field, vmcs_readl(field) | mask);
491 }
492
493 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
494 {
495 u32 eb;
496
497 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
498 if (!vcpu->fpu_active)
499 eb |= 1u << NM_VECTOR;
500 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
501 if (vcpu->guest_debug &
502 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
503 eb |= 1u << DB_VECTOR;
504 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
505 eb |= 1u << BP_VECTOR;
506 }
507 if (vcpu->arch.rmode.vm86_active)
508 eb = ~0;
509 if (enable_ept)
510 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
511 vmcs_write32(EXCEPTION_BITMAP, eb);
512 }
513
514 static void reload_tss(void)
515 {
516 /*
517 * VT restores TR but not its size. Useless.
518 */
519 struct descriptor_table gdt;
520 struct desc_struct *descs;
521
522 kvm_get_gdt(&gdt);
523 descs = (void *)gdt.base;
524 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
525 load_TR_desc();
526 }
527
528 static void load_transition_efer(struct vcpu_vmx *vmx)
529 {
530 int efer_offset = vmx->msr_offset_efer;
531 u64 host_efer = vmx->host_msrs[efer_offset].data;
532 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
533 u64 ignore_bits;
534
535 if (efer_offset < 0)
536 return;
537 /*
538 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
539 * outside long mode
540 */
541 ignore_bits = EFER_NX | EFER_SCE;
542 #ifdef CONFIG_X86_64
543 ignore_bits |= EFER_LMA | EFER_LME;
544 /* SCE is meaningful only in long mode on Intel */
545 if (guest_efer & EFER_LMA)
546 ignore_bits &= ~(u64)EFER_SCE;
547 #endif
548 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
549 return;
550
551 vmx->host_state.guest_efer_loaded = 1;
552 guest_efer &= ~ignore_bits;
553 guest_efer |= host_efer & ignore_bits;
554 wrmsrl(MSR_EFER, guest_efer);
555 vmx->vcpu.stat.efer_reload++;
556 }
557
558 static void reload_host_efer(struct vcpu_vmx *vmx)
559 {
560 if (vmx->host_state.guest_efer_loaded) {
561 vmx->host_state.guest_efer_loaded = 0;
562 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
563 }
564 }
565
566 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
567 {
568 struct vcpu_vmx *vmx = to_vmx(vcpu);
569
570 if (vmx->host_state.loaded)
571 return;
572
573 vmx->host_state.loaded = 1;
574 /*
575 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
576 * allow segment selectors with cpl > 0 or ti == 1.
577 */
578 vmx->host_state.ldt_sel = kvm_read_ldt();
579 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
580 vmx->host_state.fs_sel = kvm_read_fs();
581 if (!(vmx->host_state.fs_sel & 7)) {
582 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
583 vmx->host_state.fs_reload_needed = 0;
584 } else {
585 vmcs_write16(HOST_FS_SELECTOR, 0);
586 vmx->host_state.fs_reload_needed = 1;
587 }
588 vmx->host_state.gs_sel = kvm_read_gs();
589 if (!(vmx->host_state.gs_sel & 7))
590 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
591 else {
592 vmcs_write16(HOST_GS_SELECTOR, 0);
593 vmx->host_state.gs_ldt_reload_needed = 1;
594 }
595
596 #ifdef CONFIG_X86_64
597 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
598 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
599 #else
600 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
601 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
602 #endif
603
604 #ifdef CONFIG_X86_64
605 if (is_long_mode(&vmx->vcpu))
606 save_msrs(vmx->host_msrs +
607 vmx->msr_offset_kernel_gs_base, 1);
608
609 #endif
610 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
611 load_transition_efer(vmx);
612 }
613
614 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
615 {
616 unsigned long flags;
617
618 if (!vmx->host_state.loaded)
619 return;
620
621 ++vmx->vcpu.stat.host_state_reload;
622 vmx->host_state.loaded = 0;
623 if (vmx->host_state.fs_reload_needed)
624 kvm_load_fs(vmx->host_state.fs_sel);
625 if (vmx->host_state.gs_ldt_reload_needed) {
626 kvm_load_ldt(vmx->host_state.ldt_sel);
627 /*
628 * If we have to reload gs, we must take care to
629 * preserve our gs base.
630 */
631 local_irq_save(flags);
632 kvm_load_gs(vmx->host_state.gs_sel);
633 #ifdef CONFIG_X86_64
634 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
635 #endif
636 local_irq_restore(flags);
637 }
638 reload_tss();
639 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
640 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
641 reload_host_efer(vmx);
642 }
643
644 static void vmx_load_host_state(struct vcpu_vmx *vmx)
645 {
646 preempt_disable();
647 __vmx_load_host_state(vmx);
648 preempt_enable();
649 }
650
651 /*
652 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
653 * vcpu mutex is already taken.
654 */
655 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
656 {
657 struct vcpu_vmx *vmx = to_vmx(vcpu);
658 u64 phys_addr = __pa(vmx->vmcs);
659 u64 tsc_this, delta, new_offset;
660
661 if (vcpu->cpu != cpu) {
662 vcpu_clear(vmx);
663 kvm_migrate_timers(vcpu);
664 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
665 local_irq_disable();
666 list_add(&vmx->local_vcpus_link,
667 &per_cpu(vcpus_on_cpu, cpu));
668 local_irq_enable();
669 }
670
671 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
672 u8 error;
673
674 per_cpu(current_vmcs, cpu) = vmx->vmcs;
675 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
676 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
677 : "cc");
678 if (error)
679 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
680 vmx->vmcs, phys_addr);
681 }
682
683 if (vcpu->cpu != cpu) {
684 struct descriptor_table dt;
685 unsigned long sysenter_esp;
686
687 vcpu->cpu = cpu;
688 /*
689 * Linux uses per-cpu TSS and GDT, so set these when switching
690 * processors.
691 */
692 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
693 kvm_get_gdt(&dt);
694 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
695
696 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
697 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
698
699 /*
700 * Make sure the time stamp counter is monotonous.
701 */
702 rdtscll(tsc_this);
703 if (tsc_this < vcpu->arch.host_tsc) {
704 delta = vcpu->arch.host_tsc - tsc_this;
705 new_offset = vmcs_read64(TSC_OFFSET) + delta;
706 vmcs_write64(TSC_OFFSET, new_offset);
707 }
708 }
709 }
710
711 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
712 {
713 __vmx_load_host_state(to_vmx(vcpu));
714 }
715
716 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
717 {
718 if (vcpu->fpu_active)
719 return;
720 vcpu->fpu_active = 1;
721 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
722 if (vcpu->arch.cr0 & X86_CR0_TS)
723 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
724 update_exception_bitmap(vcpu);
725 }
726
727 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
728 {
729 if (!vcpu->fpu_active)
730 return;
731 vcpu->fpu_active = 0;
732 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
733 update_exception_bitmap(vcpu);
734 }
735
736 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
737 {
738 return vmcs_readl(GUEST_RFLAGS);
739 }
740
741 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
742 {
743 if (vcpu->arch.rmode.vm86_active)
744 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
745 vmcs_writel(GUEST_RFLAGS, rflags);
746 }
747
748 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
749 {
750 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
751 int ret = 0;
752
753 if (interruptibility & GUEST_INTR_STATE_STI)
754 ret |= X86_SHADOW_INT_STI;
755 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
756 ret |= X86_SHADOW_INT_MOV_SS;
757
758 return ret & mask;
759 }
760
761 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
762 {
763 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
764 u32 interruptibility = interruptibility_old;
765
766 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
767
768 if (mask & X86_SHADOW_INT_MOV_SS)
769 interruptibility |= GUEST_INTR_STATE_MOV_SS;
770 if (mask & X86_SHADOW_INT_STI)
771 interruptibility |= GUEST_INTR_STATE_STI;
772
773 if ((interruptibility != interruptibility_old))
774 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
775 }
776
777 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
778 {
779 unsigned long rip;
780
781 rip = kvm_rip_read(vcpu);
782 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
783 kvm_rip_write(vcpu, rip);
784
785 /* skipping an emulated instruction also counts */
786 vmx_set_interrupt_shadow(vcpu, 0);
787 }
788
789 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
790 bool has_error_code, u32 error_code)
791 {
792 struct vcpu_vmx *vmx = to_vmx(vcpu);
793 u32 intr_info = nr | INTR_INFO_VALID_MASK;
794
795 if (has_error_code) {
796 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
797 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
798 }
799
800 if (vcpu->arch.rmode.vm86_active) {
801 vmx->rmode.irq.pending = true;
802 vmx->rmode.irq.vector = nr;
803 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
804 if (nr == BP_VECTOR || nr == OF_VECTOR)
805 vmx->rmode.irq.rip++;
806 intr_info |= INTR_TYPE_SOFT_INTR;
807 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
808 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
809 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
810 return;
811 }
812
813 if (kvm_exception_is_soft(nr)) {
814 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
815 vmx->vcpu.arch.event_exit_inst_len);
816 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
817 } else
818 intr_info |= INTR_TYPE_HARD_EXCEPTION;
819
820 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
821 }
822
823 /*
824 * Swap MSR entry in host/guest MSR entry array.
825 */
826 #ifdef CONFIG_X86_64
827 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
828 {
829 struct kvm_msr_entry tmp;
830
831 tmp = vmx->guest_msrs[to];
832 vmx->guest_msrs[to] = vmx->guest_msrs[from];
833 vmx->guest_msrs[from] = tmp;
834 tmp = vmx->host_msrs[to];
835 vmx->host_msrs[to] = vmx->host_msrs[from];
836 vmx->host_msrs[from] = tmp;
837 }
838 #endif
839
840 /*
841 * Set up the vmcs to automatically save and restore system
842 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
843 * mode, as fiddling with msrs is very expensive.
844 */
845 static void setup_msrs(struct vcpu_vmx *vmx)
846 {
847 int save_nmsrs;
848 unsigned long *msr_bitmap;
849
850 vmx_load_host_state(vmx);
851 save_nmsrs = 0;
852 #ifdef CONFIG_X86_64
853 if (is_long_mode(&vmx->vcpu)) {
854 int index;
855
856 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
857 if (index >= 0)
858 move_msr_up(vmx, index, save_nmsrs++);
859 index = __find_msr_index(vmx, MSR_LSTAR);
860 if (index >= 0)
861 move_msr_up(vmx, index, save_nmsrs++);
862 index = __find_msr_index(vmx, MSR_CSTAR);
863 if (index >= 0)
864 move_msr_up(vmx, index, save_nmsrs++);
865 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
866 if (index >= 0)
867 move_msr_up(vmx, index, save_nmsrs++);
868 /*
869 * MSR_K6_STAR is only needed on long mode guests, and only
870 * if efer.sce is enabled.
871 */
872 index = __find_msr_index(vmx, MSR_K6_STAR);
873 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
874 move_msr_up(vmx, index, save_nmsrs++);
875 }
876 #endif
877 vmx->save_nmsrs = save_nmsrs;
878
879 #ifdef CONFIG_X86_64
880 vmx->msr_offset_kernel_gs_base =
881 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
882 #endif
883 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
884
885 if (cpu_has_vmx_msr_bitmap()) {
886 if (is_long_mode(&vmx->vcpu))
887 msr_bitmap = vmx_msr_bitmap_longmode;
888 else
889 msr_bitmap = vmx_msr_bitmap_legacy;
890
891 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
892 }
893 }
894
895 /*
896 * reads and returns guest's timestamp counter "register"
897 * guest_tsc = host_tsc + tsc_offset -- 21.3
898 */
899 static u64 guest_read_tsc(void)
900 {
901 u64 host_tsc, tsc_offset;
902
903 rdtscll(host_tsc);
904 tsc_offset = vmcs_read64(TSC_OFFSET);
905 return host_tsc + tsc_offset;
906 }
907
908 /*
909 * writes 'guest_tsc' into guest's timestamp counter "register"
910 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
911 */
912 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
913 {
914 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
915 }
916
917 /*
918 * Reads an msr value (of 'msr_index') into 'pdata'.
919 * Returns 0 on success, non-0 otherwise.
920 * Assumes vcpu_load() was already called.
921 */
922 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
923 {
924 u64 data;
925 struct kvm_msr_entry *msr;
926
927 if (!pdata) {
928 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
929 return -EINVAL;
930 }
931
932 switch (msr_index) {
933 #ifdef CONFIG_X86_64
934 case MSR_FS_BASE:
935 data = vmcs_readl(GUEST_FS_BASE);
936 break;
937 case MSR_GS_BASE:
938 data = vmcs_readl(GUEST_GS_BASE);
939 break;
940 case MSR_EFER:
941 return kvm_get_msr_common(vcpu, msr_index, pdata);
942 #endif
943 case MSR_IA32_TIME_STAMP_COUNTER:
944 data = guest_read_tsc();
945 break;
946 case MSR_IA32_SYSENTER_CS:
947 data = vmcs_read32(GUEST_SYSENTER_CS);
948 break;
949 case MSR_IA32_SYSENTER_EIP:
950 data = vmcs_readl(GUEST_SYSENTER_EIP);
951 break;
952 case MSR_IA32_SYSENTER_ESP:
953 data = vmcs_readl(GUEST_SYSENTER_ESP);
954 break;
955 default:
956 vmx_load_host_state(to_vmx(vcpu));
957 msr = find_msr_entry(to_vmx(vcpu), msr_index);
958 if (msr) {
959 data = msr->data;
960 break;
961 }
962 return kvm_get_msr_common(vcpu, msr_index, pdata);
963 }
964
965 *pdata = data;
966 return 0;
967 }
968
969 /*
970 * Writes msr value into into the appropriate "register".
971 * Returns 0 on success, non-0 otherwise.
972 * Assumes vcpu_load() was already called.
973 */
974 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
975 {
976 struct vcpu_vmx *vmx = to_vmx(vcpu);
977 struct kvm_msr_entry *msr;
978 u64 host_tsc;
979 int ret = 0;
980
981 switch (msr_index) {
982 case MSR_EFER:
983 vmx_load_host_state(vmx);
984 ret = kvm_set_msr_common(vcpu, msr_index, data);
985 break;
986 #ifdef CONFIG_X86_64
987 case MSR_FS_BASE:
988 vmcs_writel(GUEST_FS_BASE, data);
989 break;
990 case MSR_GS_BASE:
991 vmcs_writel(GUEST_GS_BASE, data);
992 break;
993 #endif
994 case MSR_IA32_SYSENTER_CS:
995 vmcs_write32(GUEST_SYSENTER_CS, data);
996 break;
997 case MSR_IA32_SYSENTER_EIP:
998 vmcs_writel(GUEST_SYSENTER_EIP, data);
999 break;
1000 case MSR_IA32_SYSENTER_ESP:
1001 vmcs_writel(GUEST_SYSENTER_ESP, data);
1002 break;
1003 case MSR_IA32_TIME_STAMP_COUNTER:
1004 rdtscll(host_tsc);
1005 guest_write_tsc(data, host_tsc);
1006 break;
1007 case MSR_P6_PERFCTR0:
1008 case MSR_P6_PERFCTR1:
1009 case MSR_P6_EVNTSEL0:
1010 case MSR_P6_EVNTSEL1:
1011 /*
1012 * Just discard all writes to the performance counters; this
1013 * should keep both older linux and windows 64-bit guests
1014 * happy
1015 */
1016 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
1017
1018 break;
1019 case MSR_IA32_CR_PAT:
1020 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1021 vmcs_write64(GUEST_IA32_PAT, data);
1022 vcpu->arch.pat = data;
1023 break;
1024 }
1025 /* Otherwise falls through to kvm_set_msr_common */
1026 default:
1027 vmx_load_host_state(vmx);
1028 msr = find_msr_entry(vmx, msr_index);
1029 if (msr) {
1030 msr->data = data;
1031 break;
1032 }
1033 ret = kvm_set_msr_common(vcpu, msr_index, data);
1034 }
1035
1036 return ret;
1037 }
1038
1039 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1040 {
1041 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1042 switch (reg) {
1043 case VCPU_REGS_RSP:
1044 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1045 break;
1046 case VCPU_REGS_RIP:
1047 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1048 break;
1049 default:
1050 break;
1051 }
1052 }
1053
1054 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1055 {
1056 int old_debug = vcpu->guest_debug;
1057 unsigned long flags;
1058
1059 vcpu->guest_debug = dbg->control;
1060 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1061 vcpu->guest_debug = 0;
1062
1063 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1064 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1065 else
1066 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1067
1068 flags = vmcs_readl(GUEST_RFLAGS);
1069 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1070 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1071 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1072 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1073 vmcs_writel(GUEST_RFLAGS, flags);
1074
1075 update_exception_bitmap(vcpu);
1076
1077 return 0;
1078 }
1079
1080 static __init int cpu_has_kvm_support(void)
1081 {
1082 return cpu_has_vmx();
1083 }
1084
1085 static __init int vmx_disabled_by_bios(void)
1086 {
1087 u64 msr;
1088
1089 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1090 return (msr & (FEATURE_CONTROL_LOCKED |
1091 FEATURE_CONTROL_VMXON_ENABLED))
1092 == FEATURE_CONTROL_LOCKED;
1093 /* locked but not enabled */
1094 }
1095
1096 static void hardware_enable(void *garbage)
1097 {
1098 int cpu = raw_smp_processor_id();
1099 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1100 u64 old;
1101
1102 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1103 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1104 if ((old & (FEATURE_CONTROL_LOCKED |
1105 FEATURE_CONTROL_VMXON_ENABLED))
1106 != (FEATURE_CONTROL_LOCKED |
1107 FEATURE_CONTROL_VMXON_ENABLED))
1108 /* enable and lock */
1109 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1110 FEATURE_CONTROL_LOCKED |
1111 FEATURE_CONTROL_VMXON_ENABLED);
1112 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1113 asm volatile (ASM_VMX_VMXON_RAX
1114 : : "a"(&phys_addr), "m"(phys_addr)
1115 : "memory", "cc");
1116 }
1117
1118 static void vmclear_local_vcpus(void)
1119 {
1120 int cpu = raw_smp_processor_id();
1121 struct vcpu_vmx *vmx, *n;
1122
1123 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1124 local_vcpus_link)
1125 __vcpu_clear(vmx);
1126 }
1127
1128
1129 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1130 * tricks.
1131 */
1132 static void kvm_cpu_vmxoff(void)
1133 {
1134 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1135 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1136 }
1137
1138 static void hardware_disable(void *garbage)
1139 {
1140 vmclear_local_vcpus();
1141 kvm_cpu_vmxoff();
1142 }
1143
1144 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1145 u32 msr, u32 *result)
1146 {
1147 u32 vmx_msr_low, vmx_msr_high;
1148 u32 ctl = ctl_min | ctl_opt;
1149
1150 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1151
1152 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1153 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1154
1155 /* Ensure minimum (required) set of control bits are supported. */
1156 if (ctl_min & ~ctl)
1157 return -EIO;
1158
1159 *result = ctl;
1160 return 0;
1161 }
1162
1163 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1164 {
1165 u32 vmx_msr_low, vmx_msr_high;
1166 u32 min, opt, min2, opt2;
1167 u32 _pin_based_exec_control = 0;
1168 u32 _cpu_based_exec_control = 0;
1169 u32 _cpu_based_2nd_exec_control = 0;
1170 u32 _vmexit_control = 0;
1171 u32 _vmentry_control = 0;
1172
1173 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1174 opt = PIN_BASED_VIRTUAL_NMIS;
1175 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1176 &_pin_based_exec_control) < 0)
1177 return -EIO;
1178
1179 min = CPU_BASED_HLT_EXITING |
1180 #ifdef CONFIG_X86_64
1181 CPU_BASED_CR8_LOAD_EXITING |
1182 CPU_BASED_CR8_STORE_EXITING |
1183 #endif
1184 CPU_BASED_CR3_LOAD_EXITING |
1185 CPU_BASED_CR3_STORE_EXITING |
1186 CPU_BASED_USE_IO_BITMAPS |
1187 CPU_BASED_MOV_DR_EXITING |
1188 CPU_BASED_USE_TSC_OFFSETING |
1189 CPU_BASED_INVLPG_EXITING;
1190 opt = CPU_BASED_TPR_SHADOW |
1191 CPU_BASED_USE_MSR_BITMAPS |
1192 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1193 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1194 &_cpu_based_exec_control) < 0)
1195 return -EIO;
1196 #ifdef CONFIG_X86_64
1197 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1198 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1199 ~CPU_BASED_CR8_STORE_EXITING;
1200 #endif
1201 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1202 min2 = 0;
1203 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1204 SECONDARY_EXEC_WBINVD_EXITING |
1205 SECONDARY_EXEC_ENABLE_VPID |
1206 SECONDARY_EXEC_ENABLE_EPT;
1207 if (adjust_vmx_controls(min2, opt2,
1208 MSR_IA32_VMX_PROCBASED_CTLS2,
1209 &_cpu_based_2nd_exec_control) < 0)
1210 return -EIO;
1211 }
1212 #ifndef CONFIG_X86_64
1213 if (!(_cpu_based_2nd_exec_control &
1214 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1215 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1216 #endif
1217 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1218 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1219 enabled */
1220 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1221 CPU_BASED_CR3_STORE_EXITING |
1222 CPU_BASED_INVLPG_EXITING);
1223 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1224 vmx_capability.ept, vmx_capability.vpid);
1225 }
1226
1227 min = 0;
1228 #ifdef CONFIG_X86_64
1229 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1230 #endif
1231 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1232 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1233 &_vmexit_control) < 0)
1234 return -EIO;
1235
1236 min = 0;
1237 opt = VM_ENTRY_LOAD_IA32_PAT;
1238 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1239 &_vmentry_control) < 0)
1240 return -EIO;
1241
1242 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1243
1244 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1245 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1246 return -EIO;
1247
1248 #ifdef CONFIG_X86_64
1249 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1250 if (vmx_msr_high & (1u<<16))
1251 return -EIO;
1252 #endif
1253
1254 /* Require Write-Back (WB) memory type for VMCS accesses. */
1255 if (((vmx_msr_high >> 18) & 15) != 6)
1256 return -EIO;
1257
1258 vmcs_conf->size = vmx_msr_high & 0x1fff;
1259 vmcs_conf->order = get_order(vmcs_config.size);
1260 vmcs_conf->revision_id = vmx_msr_low;
1261
1262 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1263 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1264 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1265 vmcs_conf->vmexit_ctrl = _vmexit_control;
1266 vmcs_conf->vmentry_ctrl = _vmentry_control;
1267
1268 return 0;
1269 }
1270
1271 static struct vmcs *alloc_vmcs_cpu(int cpu)
1272 {
1273 int node = cpu_to_node(cpu);
1274 struct page *pages;
1275 struct vmcs *vmcs;
1276
1277 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1278 if (!pages)
1279 return NULL;
1280 vmcs = page_address(pages);
1281 memset(vmcs, 0, vmcs_config.size);
1282 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1283 return vmcs;
1284 }
1285
1286 static struct vmcs *alloc_vmcs(void)
1287 {
1288 return alloc_vmcs_cpu(raw_smp_processor_id());
1289 }
1290
1291 static void free_vmcs(struct vmcs *vmcs)
1292 {
1293 free_pages((unsigned long)vmcs, vmcs_config.order);
1294 }
1295
1296 static void free_kvm_area(void)
1297 {
1298 int cpu;
1299
1300 for_each_online_cpu(cpu)
1301 free_vmcs(per_cpu(vmxarea, cpu));
1302 }
1303
1304 static __init int alloc_kvm_area(void)
1305 {
1306 int cpu;
1307
1308 for_each_online_cpu(cpu) {
1309 struct vmcs *vmcs;
1310
1311 vmcs = alloc_vmcs_cpu(cpu);
1312 if (!vmcs) {
1313 free_kvm_area();
1314 return -ENOMEM;
1315 }
1316
1317 per_cpu(vmxarea, cpu) = vmcs;
1318 }
1319 return 0;
1320 }
1321
1322 static __init int hardware_setup(void)
1323 {
1324 if (setup_vmcs_config(&vmcs_config) < 0)
1325 return -EIO;
1326
1327 if (boot_cpu_has(X86_FEATURE_NX))
1328 kvm_enable_efer_bits(EFER_NX);
1329
1330 if (!cpu_has_vmx_vpid())
1331 enable_vpid = 0;
1332
1333 if (!cpu_has_vmx_ept())
1334 enable_ept = 0;
1335
1336 if (!cpu_has_vmx_flexpriority())
1337 flexpriority_enabled = 0;
1338
1339 if (!cpu_has_vmx_tpr_shadow())
1340 kvm_x86_ops->update_cr8_intercept = NULL;
1341
1342 return alloc_kvm_area();
1343 }
1344
1345 static __exit void hardware_unsetup(void)
1346 {
1347 free_kvm_area();
1348 }
1349
1350 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1351 {
1352 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1353
1354 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1355 vmcs_write16(sf->selector, save->selector);
1356 vmcs_writel(sf->base, save->base);
1357 vmcs_write32(sf->limit, save->limit);
1358 vmcs_write32(sf->ar_bytes, save->ar);
1359 } else {
1360 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1361 << AR_DPL_SHIFT;
1362 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1363 }
1364 }
1365
1366 static void enter_pmode(struct kvm_vcpu *vcpu)
1367 {
1368 unsigned long flags;
1369 struct vcpu_vmx *vmx = to_vmx(vcpu);
1370
1371 vmx->emulation_required = 1;
1372 vcpu->arch.rmode.vm86_active = 0;
1373
1374 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1375 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1376 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1377
1378 flags = vmcs_readl(GUEST_RFLAGS);
1379 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1380 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1381 vmcs_writel(GUEST_RFLAGS, flags);
1382
1383 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1384 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1385
1386 update_exception_bitmap(vcpu);
1387
1388 if (emulate_invalid_guest_state)
1389 return;
1390
1391 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1392 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1393 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1394 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1395
1396 vmcs_write16(GUEST_SS_SELECTOR, 0);
1397 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1398
1399 vmcs_write16(GUEST_CS_SELECTOR,
1400 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1401 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1402 }
1403
1404 static gva_t rmode_tss_base(struct kvm *kvm)
1405 {
1406 if (!kvm->arch.tss_addr) {
1407 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1408 kvm->memslots[0].npages - 3;
1409 return base_gfn << PAGE_SHIFT;
1410 }
1411 return kvm->arch.tss_addr;
1412 }
1413
1414 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1415 {
1416 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1417
1418 save->selector = vmcs_read16(sf->selector);
1419 save->base = vmcs_readl(sf->base);
1420 save->limit = vmcs_read32(sf->limit);
1421 save->ar = vmcs_read32(sf->ar_bytes);
1422 vmcs_write16(sf->selector, save->base >> 4);
1423 vmcs_write32(sf->base, save->base & 0xfffff);
1424 vmcs_write32(sf->limit, 0xffff);
1425 vmcs_write32(sf->ar_bytes, 0xf3);
1426 }
1427
1428 static void enter_rmode(struct kvm_vcpu *vcpu)
1429 {
1430 unsigned long flags;
1431 struct vcpu_vmx *vmx = to_vmx(vcpu);
1432
1433 vmx->emulation_required = 1;
1434 vcpu->arch.rmode.vm86_active = 1;
1435
1436 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1437 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1438
1439 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1440 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1441
1442 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1443 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1444
1445 flags = vmcs_readl(GUEST_RFLAGS);
1446 vcpu->arch.rmode.save_iopl
1447 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1448
1449 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1450
1451 vmcs_writel(GUEST_RFLAGS, flags);
1452 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1453 update_exception_bitmap(vcpu);
1454
1455 if (emulate_invalid_guest_state)
1456 goto continue_rmode;
1457
1458 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1459 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1460 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1461
1462 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1463 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1464 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1465 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1466 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1467
1468 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1469 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1470 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1471 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1472
1473 continue_rmode:
1474 kvm_mmu_reset_context(vcpu);
1475 init_rmode(vcpu->kvm);
1476 }
1477
1478 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1479 {
1480 struct vcpu_vmx *vmx = to_vmx(vcpu);
1481 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1482
1483 vcpu->arch.shadow_efer = efer;
1484 if (!msr)
1485 return;
1486 if (efer & EFER_LMA) {
1487 vmcs_write32(VM_ENTRY_CONTROLS,
1488 vmcs_read32(VM_ENTRY_CONTROLS) |
1489 VM_ENTRY_IA32E_MODE);
1490 msr->data = efer;
1491 } else {
1492 vmcs_write32(VM_ENTRY_CONTROLS,
1493 vmcs_read32(VM_ENTRY_CONTROLS) &
1494 ~VM_ENTRY_IA32E_MODE);
1495
1496 msr->data = efer & ~EFER_LME;
1497 }
1498 setup_msrs(vmx);
1499 }
1500
1501 #ifdef CONFIG_X86_64
1502
1503 static void enter_lmode(struct kvm_vcpu *vcpu)
1504 {
1505 u32 guest_tr_ar;
1506
1507 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1508 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1509 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1510 __func__);
1511 vmcs_write32(GUEST_TR_AR_BYTES,
1512 (guest_tr_ar & ~AR_TYPE_MASK)
1513 | AR_TYPE_BUSY_64_TSS);
1514 }
1515 vcpu->arch.shadow_efer |= EFER_LMA;
1516 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1517 }
1518
1519 static void exit_lmode(struct kvm_vcpu *vcpu)
1520 {
1521 vcpu->arch.shadow_efer &= ~EFER_LMA;
1522
1523 vmcs_write32(VM_ENTRY_CONTROLS,
1524 vmcs_read32(VM_ENTRY_CONTROLS)
1525 & ~VM_ENTRY_IA32E_MODE);
1526 }
1527
1528 #endif
1529
1530 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1531 {
1532 vpid_sync_vcpu_all(to_vmx(vcpu));
1533 if (enable_ept)
1534 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1535 }
1536
1537 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1538 {
1539 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1540 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1541 }
1542
1543 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1544 {
1545 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1546 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1547 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1548 return;
1549 }
1550 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1551 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1552 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1553 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1554 }
1555 }
1556
1557 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1558
1559 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1560 unsigned long cr0,
1561 struct kvm_vcpu *vcpu)
1562 {
1563 if (!(cr0 & X86_CR0_PG)) {
1564 /* From paging/starting to nonpaging */
1565 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1566 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1567 (CPU_BASED_CR3_LOAD_EXITING |
1568 CPU_BASED_CR3_STORE_EXITING));
1569 vcpu->arch.cr0 = cr0;
1570 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1571 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1572 } else if (!is_paging(vcpu)) {
1573 /* From nonpaging to paging */
1574 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1575 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1576 ~(CPU_BASED_CR3_LOAD_EXITING |
1577 CPU_BASED_CR3_STORE_EXITING));
1578 vcpu->arch.cr0 = cr0;
1579 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1580 }
1581
1582 if (!(cr0 & X86_CR0_WP))
1583 *hw_cr0 &= ~X86_CR0_WP;
1584 }
1585
1586 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1587 struct kvm_vcpu *vcpu)
1588 {
1589 if (!is_paging(vcpu)) {
1590 *hw_cr4 &= ~X86_CR4_PAE;
1591 *hw_cr4 |= X86_CR4_PSE;
1592 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1593 *hw_cr4 &= ~X86_CR4_PAE;
1594 }
1595
1596 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1597 {
1598 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1599 KVM_VM_CR0_ALWAYS_ON;
1600
1601 vmx_fpu_deactivate(vcpu);
1602
1603 if (vcpu->arch.rmode.vm86_active && (cr0 & X86_CR0_PE))
1604 enter_pmode(vcpu);
1605
1606 if (!vcpu->arch.rmode.vm86_active && !(cr0 & X86_CR0_PE))
1607 enter_rmode(vcpu);
1608
1609 #ifdef CONFIG_X86_64
1610 if (vcpu->arch.shadow_efer & EFER_LME) {
1611 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1612 enter_lmode(vcpu);
1613 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1614 exit_lmode(vcpu);
1615 }
1616 #endif
1617
1618 if (enable_ept)
1619 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1620
1621 vmcs_writel(CR0_READ_SHADOW, cr0);
1622 vmcs_writel(GUEST_CR0, hw_cr0);
1623 vcpu->arch.cr0 = cr0;
1624
1625 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1626 vmx_fpu_activate(vcpu);
1627 }
1628
1629 static u64 construct_eptp(unsigned long root_hpa)
1630 {
1631 u64 eptp;
1632
1633 /* TODO write the value reading from MSR */
1634 eptp = VMX_EPT_DEFAULT_MT |
1635 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1636 eptp |= (root_hpa & PAGE_MASK);
1637
1638 return eptp;
1639 }
1640
1641 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1642 {
1643 unsigned long guest_cr3;
1644 u64 eptp;
1645
1646 guest_cr3 = cr3;
1647 if (enable_ept) {
1648 eptp = construct_eptp(cr3);
1649 vmcs_write64(EPT_POINTER, eptp);
1650 ept_sync_context(eptp);
1651 ept_load_pdptrs(vcpu);
1652 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1653 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1654 }
1655
1656 vmx_flush_tlb(vcpu);
1657 vmcs_writel(GUEST_CR3, guest_cr3);
1658 if (vcpu->arch.cr0 & X86_CR0_PE)
1659 vmx_fpu_deactivate(vcpu);
1660 }
1661
1662 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1663 {
1664 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.vm86_active ?
1665 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1666
1667 vcpu->arch.cr4 = cr4;
1668 if (enable_ept)
1669 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1670
1671 vmcs_writel(CR4_READ_SHADOW, cr4);
1672 vmcs_writel(GUEST_CR4, hw_cr4);
1673 }
1674
1675 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1676 {
1677 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1678
1679 return vmcs_readl(sf->base);
1680 }
1681
1682 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1683 struct kvm_segment *var, int seg)
1684 {
1685 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1686 u32 ar;
1687
1688 var->base = vmcs_readl(sf->base);
1689 var->limit = vmcs_read32(sf->limit);
1690 var->selector = vmcs_read16(sf->selector);
1691 ar = vmcs_read32(sf->ar_bytes);
1692 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1693 ar = 0;
1694 var->type = ar & 15;
1695 var->s = (ar >> 4) & 1;
1696 var->dpl = (ar >> 5) & 3;
1697 var->present = (ar >> 7) & 1;
1698 var->avl = (ar >> 12) & 1;
1699 var->l = (ar >> 13) & 1;
1700 var->db = (ar >> 14) & 1;
1701 var->g = (ar >> 15) & 1;
1702 var->unusable = (ar >> 16) & 1;
1703 }
1704
1705 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1706 {
1707 struct kvm_segment kvm_seg;
1708
1709 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1710 return 0;
1711
1712 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1713 return 3;
1714
1715 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1716 return kvm_seg.selector & 3;
1717 }
1718
1719 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1720 {
1721 u32 ar;
1722
1723 if (var->unusable)
1724 ar = 1 << 16;
1725 else {
1726 ar = var->type & 15;
1727 ar |= (var->s & 1) << 4;
1728 ar |= (var->dpl & 3) << 5;
1729 ar |= (var->present & 1) << 7;
1730 ar |= (var->avl & 1) << 12;
1731 ar |= (var->l & 1) << 13;
1732 ar |= (var->db & 1) << 14;
1733 ar |= (var->g & 1) << 15;
1734 }
1735 if (ar == 0) /* a 0 value means unusable */
1736 ar = AR_UNUSABLE_MASK;
1737
1738 return ar;
1739 }
1740
1741 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1742 struct kvm_segment *var, int seg)
1743 {
1744 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1745 u32 ar;
1746
1747 if (vcpu->arch.rmode.vm86_active && seg == VCPU_SREG_TR) {
1748 vcpu->arch.rmode.tr.selector = var->selector;
1749 vcpu->arch.rmode.tr.base = var->base;
1750 vcpu->arch.rmode.tr.limit = var->limit;
1751 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1752 return;
1753 }
1754 vmcs_writel(sf->base, var->base);
1755 vmcs_write32(sf->limit, var->limit);
1756 vmcs_write16(sf->selector, var->selector);
1757 if (vcpu->arch.rmode.vm86_active && var->s) {
1758 /*
1759 * Hack real-mode segments into vm86 compatibility.
1760 */
1761 if (var->base == 0xffff0000 && var->selector == 0xf000)
1762 vmcs_writel(sf->base, 0xf0000);
1763 ar = 0xf3;
1764 } else
1765 ar = vmx_segment_access_rights(var);
1766 vmcs_write32(sf->ar_bytes, ar);
1767 }
1768
1769 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1770 {
1771 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1772
1773 *db = (ar >> 14) & 1;
1774 *l = (ar >> 13) & 1;
1775 }
1776
1777 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1778 {
1779 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1780 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1781 }
1782
1783 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1784 {
1785 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1786 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1787 }
1788
1789 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1790 {
1791 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1792 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1793 }
1794
1795 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1796 {
1797 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1798 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1799 }
1800
1801 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1802 {
1803 struct kvm_segment var;
1804 u32 ar;
1805
1806 vmx_get_segment(vcpu, &var, seg);
1807 ar = vmx_segment_access_rights(&var);
1808
1809 if (var.base != (var.selector << 4))
1810 return false;
1811 if (var.limit != 0xffff)
1812 return false;
1813 if (ar != 0xf3)
1814 return false;
1815
1816 return true;
1817 }
1818
1819 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1820 {
1821 struct kvm_segment cs;
1822 unsigned int cs_rpl;
1823
1824 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1825 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1826
1827 if (cs.unusable)
1828 return false;
1829 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1830 return false;
1831 if (!cs.s)
1832 return false;
1833 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1834 if (cs.dpl > cs_rpl)
1835 return false;
1836 } else {
1837 if (cs.dpl != cs_rpl)
1838 return false;
1839 }
1840 if (!cs.present)
1841 return false;
1842
1843 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1844 return true;
1845 }
1846
1847 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1848 {
1849 struct kvm_segment ss;
1850 unsigned int ss_rpl;
1851
1852 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1853 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1854
1855 if (ss.unusable)
1856 return true;
1857 if (ss.type != 3 && ss.type != 7)
1858 return false;
1859 if (!ss.s)
1860 return false;
1861 if (ss.dpl != ss_rpl) /* DPL != RPL */
1862 return false;
1863 if (!ss.present)
1864 return false;
1865
1866 return true;
1867 }
1868
1869 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1870 {
1871 struct kvm_segment var;
1872 unsigned int rpl;
1873
1874 vmx_get_segment(vcpu, &var, seg);
1875 rpl = var.selector & SELECTOR_RPL_MASK;
1876
1877 if (var.unusable)
1878 return true;
1879 if (!var.s)
1880 return false;
1881 if (!var.present)
1882 return false;
1883 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1884 if (var.dpl < rpl) /* DPL < RPL */
1885 return false;
1886 }
1887
1888 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1889 * rights flags
1890 */
1891 return true;
1892 }
1893
1894 static bool tr_valid(struct kvm_vcpu *vcpu)
1895 {
1896 struct kvm_segment tr;
1897
1898 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1899
1900 if (tr.unusable)
1901 return false;
1902 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1903 return false;
1904 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1905 return false;
1906 if (!tr.present)
1907 return false;
1908
1909 return true;
1910 }
1911
1912 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1913 {
1914 struct kvm_segment ldtr;
1915
1916 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1917
1918 if (ldtr.unusable)
1919 return true;
1920 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1921 return false;
1922 if (ldtr.type != 2)
1923 return false;
1924 if (!ldtr.present)
1925 return false;
1926
1927 return true;
1928 }
1929
1930 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1931 {
1932 struct kvm_segment cs, ss;
1933
1934 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1935 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1936
1937 return ((cs.selector & SELECTOR_RPL_MASK) ==
1938 (ss.selector & SELECTOR_RPL_MASK));
1939 }
1940
1941 /*
1942 * Check if guest state is valid. Returns true if valid, false if
1943 * not.
1944 * We assume that registers are always usable
1945 */
1946 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1947 {
1948 /* real mode guest state checks */
1949 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1950 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1951 return false;
1952 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1953 return false;
1954 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1955 return false;
1956 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1957 return false;
1958 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1959 return false;
1960 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1961 return false;
1962 } else {
1963 /* protected mode guest state checks */
1964 if (!cs_ss_rpl_check(vcpu))
1965 return false;
1966 if (!code_segment_valid(vcpu))
1967 return false;
1968 if (!stack_segment_valid(vcpu))
1969 return false;
1970 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1971 return false;
1972 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1973 return false;
1974 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1975 return false;
1976 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1977 return false;
1978 if (!tr_valid(vcpu))
1979 return false;
1980 if (!ldtr_valid(vcpu))
1981 return false;
1982 }
1983 /* TODO:
1984 * - Add checks on RIP
1985 * - Add checks on RFLAGS
1986 */
1987
1988 return true;
1989 }
1990
1991 static int init_rmode_tss(struct kvm *kvm)
1992 {
1993 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1994 u16 data = 0;
1995 int ret = 0;
1996 int r;
1997
1998 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1999 if (r < 0)
2000 goto out;
2001 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2002 r = kvm_write_guest_page(kvm, fn++, &data,
2003 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2004 if (r < 0)
2005 goto out;
2006 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2007 if (r < 0)
2008 goto out;
2009 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2010 if (r < 0)
2011 goto out;
2012 data = ~0;
2013 r = kvm_write_guest_page(kvm, fn, &data,
2014 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2015 sizeof(u8));
2016 if (r < 0)
2017 goto out;
2018
2019 ret = 1;
2020 out:
2021 return ret;
2022 }
2023
2024 static int init_rmode_identity_map(struct kvm *kvm)
2025 {
2026 int i, r, ret;
2027 pfn_t identity_map_pfn;
2028 u32 tmp;
2029
2030 if (!enable_ept)
2031 return 1;
2032 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2033 printk(KERN_ERR "EPT: identity-mapping pagetable "
2034 "haven't been allocated!\n");
2035 return 0;
2036 }
2037 if (likely(kvm->arch.ept_identity_pagetable_done))
2038 return 1;
2039 ret = 0;
2040 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2041 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2042 if (r < 0)
2043 goto out;
2044 /* Set up identity-mapping pagetable for EPT in real mode */
2045 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2046 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2047 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2048 r = kvm_write_guest_page(kvm, identity_map_pfn,
2049 &tmp, i * sizeof(tmp), sizeof(tmp));
2050 if (r < 0)
2051 goto out;
2052 }
2053 kvm->arch.ept_identity_pagetable_done = true;
2054 ret = 1;
2055 out:
2056 return ret;
2057 }
2058
2059 static void seg_setup(int seg)
2060 {
2061 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2062
2063 vmcs_write16(sf->selector, 0);
2064 vmcs_writel(sf->base, 0);
2065 vmcs_write32(sf->limit, 0xffff);
2066 vmcs_write32(sf->ar_bytes, 0xf3);
2067 }
2068
2069 static int alloc_apic_access_page(struct kvm *kvm)
2070 {
2071 struct kvm_userspace_memory_region kvm_userspace_mem;
2072 int r = 0;
2073
2074 down_write(&kvm->slots_lock);
2075 if (kvm->arch.apic_access_page)
2076 goto out;
2077 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2078 kvm_userspace_mem.flags = 0;
2079 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2080 kvm_userspace_mem.memory_size = PAGE_SIZE;
2081 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2082 if (r)
2083 goto out;
2084
2085 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2086 out:
2087 up_write(&kvm->slots_lock);
2088 return r;
2089 }
2090
2091 static int alloc_identity_pagetable(struct kvm *kvm)
2092 {
2093 struct kvm_userspace_memory_region kvm_userspace_mem;
2094 int r = 0;
2095
2096 down_write(&kvm->slots_lock);
2097 if (kvm->arch.ept_identity_pagetable)
2098 goto out;
2099 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2100 kvm_userspace_mem.flags = 0;
2101 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2102 kvm_userspace_mem.memory_size = PAGE_SIZE;
2103 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2104 if (r)
2105 goto out;
2106
2107 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2108 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2109 out:
2110 up_write(&kvm->slots_lock);
2111 return r;
2112 }
2113
2114 static void allocate_vpid(struct vcpu_vmx *vmx)
2115 {
2116 int vpid;
2117
2118 vmx->vpid = 0;
2119 if (!enable_vpid)
2120 return;
2121 spin_lock(&vmx_vpid_lock);
2122 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2123 if (vpid < VMX_NR_VPIDS) {
2124 vmx->vpid = vpid;
2125 __set_bit(vpid, vmx_vpid_bitmap);
2126 }
2127 spin_unlock(&vmx_vpid_lock);
2128 }
2129
2130 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2131 {
2132 int f = sizeof(unsigned long);
2133
2134 if (!cpu_has_vmx_msr_bitmap())
2135 return;
2136
2137 /*
2138 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2139 * have the write-low and read-high bitmap offsets the wrong way round.
2140 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2141 */
2142 if (msr <= 0x1fff) {
2143 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2144 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2145 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2146 msr &= 0x1fff;
2147 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2148 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2149 }
2150 }
2151
2152 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2153 {
2154 if (!longmode_only)
2155 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2156 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2157 }
2158
2159 /*
2160 * Sets up the vmcs for emulated real mode.
2161 */
2162 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2163 {
2164 u32 host_sysenter_cs, msr_low, msr_high;
2165 u32 junk;
2166 u64 host_pat, tsc_this, tsc_base;
2167 unsigned long a;
2168 struct descriptor_table dt;
2169 int i;
2170 unsigned long kvm_vmx_return;
2171 u32 exec_control;
2172
2173 /* I/O */
2174 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2175 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2176
2177 if (cpu_has_vmx_msr_bitmap())
2178 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2179
2180 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2181
2182 /* Control */
2183 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2184 vmcs_config.pin_based_exec_ctrl);
2185
2186 exec_control = vmcs_config.cpu_based_exec_ctrl;
2187 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2188 exec_control &= ~CPU_BASED_TPR_SHADOW;
2189 #ifdef CONFIG_X86_64
2190 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2191 CPU_BASED_CR8_LOAD_EXITING;
2192 #endif
2193 }
2194 if (!enable_ept)
2195 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2196 CPU_BASED_CR3_LOAD_EXITING |
2197 CPU_BASED_INVLPG_EXITING;
2198 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2199
2200 if (cpu_has_secondary_exec_ctrls()) {
2201 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2202 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2203 exec_control &=
2204 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2205 if (vmx->vpid == 0)
2206 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2207 if (!enable_ept)
2208 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2209 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2210 }
2211
2212 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2213 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2214 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2215
2216 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2217 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2218 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2219
2220 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2221 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2222 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2223 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2224 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2225 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2226 #ifdef CONFIG_X86_64
2227 rdmsrl(MSR_FS_BASE, a);
2228 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2229 rdmsrl(MSR_GS_BASE, a);
2230 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2231 #else
2232 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2233 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2234 #endif
2235
2236 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2237
2238 kvm_get_idt(&dt);
2239 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2240
2241 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2242 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2243 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2244 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2245 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2246
2247 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2248 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2249 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2250 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2251 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2252 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2253
2254 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2255 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2256 host_pat = msr_low | ((u64) msr_high << 32);
2257 vmcs_write64(HOST_IA32_PAT, host_pat);
2258 }
2259 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2260 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2261 host_pat = msr_low | ((u64) msr_high << 32);
2262 /* Write the default value follow host pat */
2263 vmcs_write64(GUEST_IA32_PAT, host_pat);
2264 /* Keep arch.pat sync with GUEST_IA32_PAT */
2265 vmx->vcpu.arch.pat = host_pat;
2266 }
2267
2268 for (i = 0; i < NR_VMX_MSR; ++i) {
2269 u32 index = vmx_msr_index[i];
2270 u32 data_low, data_high;
2271 u64 data;
2272 int j = vmx->nmsrs;
2273
2274 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2275 continue;
2276 if (wrmsr_safe(index, data_low, data_high) < 0)
2277 continue;
2278 data = data_low | ((u64)data_high << 32);
2279 vmx->host_msrs[j].index = index;
2280 vmx->host_msrs[j].reserved = 0;
2281 vmx->host_msrs[j].data = data;
2282 vmx->guest_msrs[j] = vmx->host_msrs[j];
2283 ++vmx->nmsrs;
2284 }
2285
2286 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2287
2288 /* 22.2.1, 20.8.1 */
2289 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2290
2291 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2292 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2293
2294 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2295 rdtscll(tsc_this);
2296 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2297 tsc_base = tsc_this;
2298
2299 guest_write_tsc(0, tsc_base);
2300
2301 return 0;
2302 }
2303
2304 static int init_rmode(struct kvm *kvm)
2305 {
2306 if (!init_rmode_tss(kvm))
2307 return 0;
2308 if (!init_rmode_identity_map(kvm))
2309 return 0;
2310 return 1;
2311 }
2312
2313 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2314 {
2315 struct vcpu_vmx *vmx = to_vmx(vcpu);
2316 u64 msr;
2317 int ret;
2318
2319 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2320 down_read(&vcpu->kvm->slots_lock);
2321 if (!init_rmode(vmx->vcpu.kvm)) {
2322 ret = -ENOMEM;
2323 goto out;
2324 }
2325
2326 vmx->vcpu.arch.rmode.vm86_active = 0;
2327
2328 vmx->soft_vnmi_blocked = 0;
2329
2330 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2331 kvm_set_cr8(&vmx->vcpu, 0);
2332 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2333 if (vmx->vcpu.vcpu_id == 0)
2334 msr |= MSR_IA32_APICBASE_BSP;
2335 kvm_set_apic_base(&vmx->vcpu, msr);
2336
2337 fx_init(&vmx->vcpu);
2338
2339 seg_setup(VCPU_SREG_CS);
2340 /*
2341 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2342 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2343 */
2344 if (vmx->vcpu.vcpu_id == 0) {
2345 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2346 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2347 } else {
2348 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2349 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2350 }
2351
2352 seg_setup(VCPU_SREG_DS);
2353 seg_setup(VCPU_SREG_ES);
2354 seg_setup(VCPU_SREG_FS);
2355 seg_setup(VCPU_SREG_GS);
2356 seg_setup(VCPU_SREG_SS);
2357
2358 vmcs_write16(GUEST_TR_SELECTOR, 0);
2359 vmcs_writel(GUEST_TR_BASE, 0);
2360 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2361 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2362
2363 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2364 vmcs_writel(GUEST_LDTR_BASE, 0);
2365 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2366 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2367
2368 vmcs_write32(GUEST_SYSENTER_CS, 0);
2369 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2370 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2371
2372 vmcs_writel(GUEST_RFLAGS, 0x02);
2373 if (vmx->vcpu.vcpu_id == 0)
2374 kvm_rip_write(vcpu, 0xfff0);
2375 else
2376 kvm_rip_write(vcpu, 0);
2377 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2378
2379 vmcs_writel(GUEST_DR7, 0x400);
2380
2381 vmcs_writel(GUEST_GDTR_BASE, 0);
2382 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2383
2384 vmcs_writel(GUEST_IDTR_BASE, 0);
2385 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2386
2387 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2388 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2389 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2390
2391 /* Special registers */
2392 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2393
2394 setup_msrs(vmx);
2395
2396 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2397
2398 if (cpu_has_vmx_tpr_shadow()) {
2399 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2400 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2401 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2402 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2403 vmcs_write32(TPR_THRESHOLD, 0);
2404 }
2405
2406 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2407 vmcs_write64(APIC_ACCESS_ADDR,
2408 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2409
2410 if (vmx->vpid != 0)
2411 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2412
2413 vmx->vcpu.arch.cr0 = 0x60000010;
2414 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2415 vmx_set_cr4(&vmx->vcpu, 0);
2416 vmx_set_efer(&vmx->vcpu, 0);
2417 vmx_fpu_activate(&vmx->vcpu);
2418 update_exception_bitmap(&vmx->vcpu);
2419
2420 vpid_sync_vcpu_all(vmx);
2421
2422 ret = 0;
2423
2424 /* HACK: Don't enable emulation on guest boot/reset */
2425 vmx->emulation_required = 0;
2426
2427 out:
2428 up_read(&vcpu->kvm->slots_lock);
2429 return ret;
2430 }
2431
2432 static void enable_irq_window(struct kvm_vcpu *vcpu)
2433 {
2434 u32 cpu_based_vm_exec_control;
2435
2436 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2437 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2438 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2439 }
2440
2441 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2442 {
2443 u32 cpu_based_vm_exec_control;
2444
2445 if (!cpu_has_virtual_nmis()) {
2446 enable_irq_window(vcpu);
2447 return;
2448 }
2449
2450 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2451 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2452 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2453 }
2454
2455 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2456 {
2457 struct vcpu_vmx *vmx = to_vmx(vcpu);
2458 uint32_t intr;
2459 int irq = vcpu->arch.interrupt.nr;
2460
2461 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2462
2463 ++vcpu->stat.irq_injections;
2464 if (vcpu->arch.rmode.vm86_active) {
2465 vmx->rmode.irq.pending = true;
2466 vmx->rmode.irq.vector = irq;
2467 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2468 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2469 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2470 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2471 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2472 return;
2473 }
2474 intr = irq | INTR_INFO_VALID_MASK;
2475 if (vcpu->arch.interrupt.soft) {
2476 intr |= INTR_TYPE_SOFT_INTR;
2477 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2478 vmx->vcpu.arch.event_exit_inst_len);
2479 } else
2480 intr |= INTR_TYPE_EXT_INTR;
2481 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2482 }
2483
2484 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2485 {
2486 struct vcpu_vmx *vmx = to_vmx(vcpu);
2487
2488 if (!cpu_has_virtual_nmis()) {
2489 /*
2490 * Tracking the NMI-blocked state in software is built upon
2491 * finding the next open IRQ window. This, in turn, depends on
2492 * well-behaving guests: They have to keep IRQs disabled at
2493 * least as long as the NMI handler runs. Otherwise we may
2494 * cause NMI nesting, maybe breaking the guest. But as this is
2495 * highly unlikely, we can live with the residual risk.
2496 */
2497 vmx->soft_vnmi_blocked = 1;
2498 vmx->vnmi_blocked_time = 0;
2499 }
2500
2501 ++vcpu->stat.nmi_injections;
2502 if (vcpu->arch.rmode.vm86_active) {
2503 vmx->rmode.irq.pending = true;
2504 vmx->rmode.irq.vector = NMI_VECTOR;
2505 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2506 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2507 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2508 INTR_INFO_VALID_MASK);
2509 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2510 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2511 return;
2512 }
2513 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2514 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2515 }
2516
2517 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2518 {
2519 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2520 return 0;
2521
2522 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2523 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2524 GUEST_INTR_STATE_NMI));
2525 }
2526
2527 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2528 {
2529 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2530 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2531 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2532 }
2533
2534 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2535 {
2536 int ret;
2537 struct kvm_userspace_memory_region tss_mem = {
2538 .slot = TSS_PRIVATE_MEMSLOT,
2539 .guest_phys_addr = addr,
2540 .memory_size = PAGE_SIZE * 3,
2541 .flags = 0,
2542 };
2543
2544 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2545 if (ret)
2546 return ret;
2547 kvm->arch.tss_addr = addr;
2548 return 0;
2549 }
2550
2551 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2552 int vec, u32 err_code)
2553 {
2554 /*
2555 * Instruction with address size override prefix opcode 0x67
2556 * Cause the #SS fault with 0 error code in VM86 mode.
2557 */
2558 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2559 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2560 return 1;
2561 /*
2562 * Forward all other exceptions that are valid in real mode.
2563 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2564 * the required debugging infrastructure rework.
2565 */
2566 switch (vec) {
2567 case DB_VECTOR:
2568 if (vcpu->guest_debug &
2569 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2570 return 0;
2571 kvm_queue_exception(vcpu, vec);
2572 return 1;
2573 case BP_VECTOR:
2574 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2575 return 0;
2576 /* fall through */
2577 case DE_VECTOR:
2578 case OF_VECTOR:
2579 case BR_VECTOR:
2580 case UD_VECTOR:
2581 case DF_VECTOR:
2582 case SS_VECTOR:
2583 case GP_VECTOR:
2584 case MF_VECTOR:
2585 kvm_queue_exception(vcpu, vec);
2586 return 1;
2587 }
2588 return 0;
2589 }
2590
2591 /*
2592 * Trigger machine check on the host. We assume all the MSRs are already set up
2593 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2594 * We pass a fake environment to the machine check handler because we want
2595 * the guest to be always treated like user space, no matter what context
2596 * it used internally.
2597 */
2598 static void kvm_machine_check(void)
2599 {
2600 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2601 struct pt_regs regs = {
2602 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2603 .flags = X86_EFLAGS_IF,
2604 };
2605
2606 do_machine_check(®s, 0);
2607 #endif
2608 }
2609
2610 static int handle_machine_check(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2611 {
2612 /* already handled by vcpu_run */
2613 return 1;
2614 }
2615
2616 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2617 {
2618 struct vcpu_vmx *vmx = to_vmx(vcpu);
2619 u32 intr_info, ex_no, error_code;
2620 unsigned long cr2, rip, dr6;
2621 u32 vect_info;
2622 enum emulation_result er;
2623
2624 vect_info = vmx->idt_vectoring_info;
2625 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2626
2627 if (is_machine_check(intr_info))
2628 return handle_machine_check(vcpu, kvm_run);
2629
2630 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2631 !is_page_fault(intr_info))
2632 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2633 "intr info 0x%x\n", __func__, vect_info, intr_info);
2634
2635 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2636 return 1; /* already handled by vmx_vcpu_run() */
2637
2638 if (is_no_device(intr_info)) {
2639 vmx_fpu_activate(vcpu);
2640 return 1;
2641 }
2642
2643 if (is_invalid_opcode(intr_info)) {
2644 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2645 if (er != EMULATE_DONE)
2646 kvm_queue_exception(vcpu, UD_VECTOR);
2647 return 1;
2648 }
2649
2650 error_code = 0;
2651 rip = kvm_rip_read(vcpu);
2652 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2653 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2654 if (is_page_fault(intr_info)) {
2655 /* EPT won't cause page fault directly */
2656 if (enable_ept)
2657 BUG();
2658 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2659 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2660 (u32)((u64)cr2 >> 32), handler);
2661 if (kvm_event_needs_reinjection(vcpu))
2662 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2663 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2664 }
2665
2666 if (vcpu->arch.rmode.vm86_active &&
2667 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2668 error_code)) {
2669 if (vcpu->arch.halt_request) {
2670 vcpu->arch.halt_request = 0;
2671 return kvm_emulate_halt(vcpu);
2672 }
2673 return 1;
2674 }
2675
2676 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2677 switch (ex_no) {
2678 case DB_VECTOR:
2679 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2680 if (!(vcpu->guest_debug &
2681 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2682 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2683 kvm_queue_exception(vcpu, DB_VECTOR);
2684 return 1;
2685 }
2686 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2687 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2688 /* fall through */
2689 case BP_VECTOR:
2690 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2691 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2692 kvm_run->debug.arch.exception = ex_no;
2693 break;
2694 default:
2695 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2696 kvm_run->ex.exception = ex_no;
2697 kvm_run->ex.error_code = error_code;
2698 break;
2699 }
2700 return 0;
2701 }
2702
2703 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2704 struct kvm_run *kvm_run)
2705 {
2706 ++vcpu->stat.irq_exits;
2707 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2708 return 1;
2709 }
2710
2711 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2712 {
2713 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2714 return 0;
2715 }
2716
2717 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2718 {
2719 unsigned long exit_qualification;
2720 int size, in, string;
2721 unsigned port;
2722
2723 ++vcpu->stat.io_exits;
2724 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2725 string = (exit_qualification & 16) != 0;
2726
2727 if (string) {
2728 if (emulate_instruction(vcpu,
2729 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2730 return 0;
2731 return 1;
2732 }
2733
2734 size = (exit_qualification & 7) + 1;
2735 in = (exit_qualification & 8) != 0;
2736 port = exit_qualification >> 16;
2737
2738 skip_emulated_instruction(vcpu);
2739 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2740 }
2741
2742 static void
2743 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2744 {
2745 /*
2746 * Patch in the VMCALL instruction:
2747 */
2748 hypercall[0] = 0x0f;
2749 hypercall[1] = 0x01;
2750 hypercall[2] = 0xc1;
2751 }
2752
2753 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2754 {
2755 unsigned long exit_qualification;
2756 int cr;
2757 int reg;
2758
2759 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2760 cr = exit_qualification & 15;
2761 reg = (exit_qualification >> 8) & 15;
2762 switch ((exit_qualification >> 4) & 3) {
2763 case 0: /* mov to cr */
2764 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2765 (u32)kvm_register_read(vcpu, reg),
2766 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2767 handler);
2768 switch (cr) {
2769 case 0:
2770 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2771 skip_emulated_instruction(vcpu);
2772 return 1;
2773 case 3:
2774 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2775 skip_emulated_instruction(vcpu);
2776 return 1;
2777 case 4:
2778 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2779 skip_emulated_instruction(vcpu);
2780 return 1;
2781 case 8: {
2782 u8 cr8_prev = kvm_get_cr8(vcpu);
2783 u8 cr8 = kvm_register_read(vcpu, reg);
2784 kvm_set_cr8(vcpu, cr8);
2785 skip_emulated_instruction(vcpu);
2786 if (irqchip_in_kernel(vcpu->kvm))
2787 return 1;
2788 if (cr8_prev <= cr8)
2789 return 1;
2790 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2791 return 0;
2792 }
2793 };
2794 break;
2795 case 2: /* clts */
2796 vmx_fpu_deactivate(vcpu);
2797 vcpu->arch.cr0 &= ~X86_CR0_TS;
2798 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2799 vmx_fpu_activate(vcpu);
2800 KVMTRACE_0D(CLTS, vcpu, handler);
2801 skip_emulated_instruction(vcpu);
2802 return 1;
2803 case 1: /*mov from cr*/
2804 switch (cr) {
2805 case 3:
2806 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2807 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2808 (u32)kvm_register_read(vcpu, reg),
2809 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2810 handler);
2811 skip_emulated_instruction(vcpu);
2812 return 1;
2813 case 8:
2814 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2815 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2816 (u32)kvm_register_read(vcpu, reg), handler);
2817 skip_emulated_instruction(vcpu);
2818 return 1;
2819 }
2820 break;
2821 case 3: /* lmsw */
2822 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2823
2824 skip_emulated_instruction(vcpu);
2825 return 1;
2826 default:
2827 break;
2828 }
2829 kvm_run->exit_reason = 0;
2830 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2831 (int)(exit_qualification >> 4) & 3, cr);
2832 return 0;
2833 }
2834
2835 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2836 {
2837 unsigned long exit_qualification;
2838 unsigned long val;
2839 int dr, reg;
2840
2841 if (!kvm_require_cpl(vcpu, 0))
2842 return 1;
2843 dr = vmcs_readl(GUEST_DR7);
2844 if (dr & DR7_GD) {
2845 /*
2846 * As the vm-exit takes precedence over the debug trap, we
2847 * need to emulate the latter, either for the host or the
2848 * guest debugging itself.
2849 */
2850 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2851 kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2852 kvm_run->debug.arch.dr7 = dr;
2853 kvm_run->debug.arch.pc =
2854 vmcs_readl(GUEST_CS_BASE) +
2855 vmcs_readl(GUEST_RIP);
2856 kvm_run->debug.arch.exception = DB_VECTOR;
2857 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2858 return 0;
2859 } else {
2860 vcpu->arch.dr7 &= ~DR7_GD;
2861 vcpu->arch.dr6 |= DR6_BD;
2862 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2863 kvm_queue_exception(vcpu, DB_VECTOR);
2864 return 1;
2865 }
2866 }
2867
2868 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2869 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2870 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2871 if (exit_qualification & TYPE_MOV_FROM_DR) {
2872 switch (dr) {
2873 case 0 ... 3:
2874 val = vcpu->arch.db[dr];
2875 break;
2876 case 6:
2877 val = vcpu->arch.dr6;
2878 break;
2879 case 7:
2880 val = vcpu->arch.dr7;
2881 break;
2882 default:
2883 val = 0;
2884 }
2885 kvm_register_write(vcpu, reg, val);
2886 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2887 } else {
2888 val = vcpu->arch.regs[reg];
2889 switch (dr) {
2890 case 0 ... 3:
2891 vcpu->arch.db[dr] = val;
2892 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2893 vcpu->arch.eff_db[dr] = val;
2894 break;
2895 case 4 ... 5:
2896 if (vcpu->arch.cr4 & X86_CR4_DE)
2897 kvm_queue_exception(vcpu, UD_VECTOR);
2898 break;
2899 case 6:
2900 if (val & 0xffffffff00000000ULL) {
2901 kvm_queue_exception(vcpu, GP_VECTOR);
2902 break;
2903 }
2904 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2905 break;
2906 case 7:
2907 if (val & 0xffffffff00000000ULL) {
2908 kvm_queue_exception(vcpu, GP_VECTOR);
2909 break;
2910 }
2911 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2912 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2913 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2914 vcpu->arch.switch_db_regs =
2915 (val & DR7_BP_EN_MASK);
2916 }
2917 break;
2918 }
2919 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
2920 }
2921 skip_emulated_instruction(vcpu);
2922 return 1;
2923 }
2924
2925 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2926 {
2927 kvm_emulate_cpuid(vcpu);
2928 return 1;
2929 }
2930
2931 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2932 {
2933 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2934 u64 data;
2935
2936 if (vmx_get_msr(vcpu, ecx, &data)) {
2937 kvm_inject_gp(vcpu, 0);
2938 return 1;
2939 }
2940
2941 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2942 handler);
2943
2944 /* FIXME: handling of bits 32:63 of rax, rdx */
2945 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2946 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2947 skip_emulated_instruction(vcpu);
2948 return 1;
2949 }
2950
2951 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2952 {
2953 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2954 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2955 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2956
2957 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2958 handler);
2959
2960 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2961 kvm_inject_gp(vcpu, 0);
2962 return 1;
2963 }
2964
2965 skip_emulated_instruction(vcpu);
2966 return 1;
2967 }
2968
2969 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2970 struct kvm_run *kvm_run)
2971 {
2972 return 1;
2973 }
2974
2975 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2976 struct kvm_run *kvm_run)
2977 {
2978 u32 cpu_based_vm_exec_control;
2979
2980 /* clear pending irq */
2981 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2982 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2983 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2984
2985 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2986 ++vcpu->stat.irq_window_exits;
2987
2988 /*
2989 * If the user space waits to inject interrupts, exit as soon as
2990 * possible
2991 */
2992 if (!irqchip_in_kernel(vcpu->kvm) &&
2993 kvm_run->request_interrupt_window &&
2994 !kvm_cpu_has_interrupt(vcpu)) {
2995 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2996 return 0;
2997 }
2998 return 1;
2999 }
3000
3001 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3002 {
3003 skip_emulated_instruction(vcpu);
3004 return kvm_emulate_halt(vcpu);
3005 }
3006
3007 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3008 {
3009 skip_emulated_instruction(vcpu);
3010 kvm_emulate_hypercall(vcpu);
3011 return 1;
3012 }
3013
3014 static int handle_vmx_insn(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3015 {
3016 kvm_queue_exception(vcpu, UD_VECTOR);
3017 return 1;
3018 }
3019
3020 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3021 {
3022 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3023
3024 kvm_mmu_invlpg(vcpu, exit_qualification);
3025 skip_emulated_instruction(vcpu);
3026 return 1;
3027 }
3028
3029 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3030 {
3031 skip_emulated_instruction(vcpu);
3032 /* TODO: Add support for VT-d/pass-through device */
3033 return 1;
3034 }
3035
3036 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3037 {
3038 unsigned long exit_qualification;
3039 enum emulation_result er;
3040 unsigned long offset;
3041
3042 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3043 offset = exit_qualification & 0xffful;
3044
3045 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3046
3047 if (er != EMULATE_DONE) {
3048 printk(KERN_ERR
3049 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3050 offset);
3051 return -ENOTSUPP;
3052 }
3053 return 1;
3054 }
3055
3056 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3057 {
3058 struct vcpu_vmx *vmx = to_vmx(vcpu);
3059 unsigned long exit_qualification;
3060 u16 tss_selector;
3061 int reason, type, idt_v;
3062
3063 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3064 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3065
3066 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3067
3068 reason = (u32)exit_qualification >> 30;
3069 if (reason == TASK_SWITCH_GATE && idt_v) {
3070 switch (type) {
3071 case INTR_TYPE_NMI_INTR:
3072 vcpu->arch.nmi_injected = false;
3073 if (cpu_has_virtual_nmis())
3074 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3075 GUEST_INTR_STATE_NMI);
3076 break;
3077 case INTR_TYPE_EXT_INTR:
3078 case INTR_TYPE_SOFT_INTR:
3079 kvm_clear_interrupt_queue(vcpu);
3080 break;
3081 case INTR_TYPE_HARD_EXCEPTION:
3082 case INTR_TYPE_SOFT_EXCEPTION:
3083 kvm_clear_exception_queue(vcpu);
3084 break;
3085 default:
3086 break;
3087 }
3088 }
3089 tss_selector = exit_qualification;
3090
3091 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3092 type != INTR_TYPE_EXT_INTR &&
3093 type != INTR_TYPE_NMI_INTR))
3094 skip_emulated_instruction(vcpu);
3095
3096 if (!kvm_task_switch(vcpu, tss_selector, reason))
3097 return 0;
3098
3099 /* clear all local breakpoint enable flags */
3100 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3101
3102 /*
3103 * TODO: What about debug traps on tss switch?
3104 * Are we supposed to inject them and update dr6?
3105 */
3106
3107 return 1;
3108 }
3109
3110 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3111 {
3112 unsigned long exit_qualification;
3113 gpa_t gpa;
3114 int gla_validity;
3115
3116 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3117
3118 if (exit_qualification & (1 << 6)) {
3119 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3120 return -ENOTSUPP;
3121 }
3122
3123 gla_validity = (exit_qualification >> 7) & 0x3;
3124 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3125 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3126 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3127 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3128 vmcs_readl(GUEST_LINEAR_ADDRESS));
3129 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3130 (long unsigned int)exit_qualification);
3131 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3132 kvm_run->hw.hardware_exit_reason = 0;
3133 return -ENOTSUPP;
3134 }
3135
3136 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3137 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3138 }
3139
3140 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3141 {
3142 u32 cpu_based_vm_exec_control;
3143
3144 /* clear pending NMI */
3145 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3146 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3147 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3148 ++vcpu->stat.nmi_window_exits;
3149
3150 return 1;
3151 }
3152
3153 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3154 struct kvm_run *kvm_run)
3155 {
3156 struct vcpu_vmx *vmx = to_vmx(vcpu);
3157 enum emulation_result err = EMULATE_DONE;
3158
3159 local_irq_enable();
3160 preempt_enable();
3161
3162 while (!guest_state_valid(vcpu)) {
3163 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3164
3165 if (err == EMULATE_DO_MMIO)
3166 break;
3167
3168 if (err != EMULATE_DONE) {
3169 kvm_report_emulation_failure(vcpu, "emulation failure");
3170 break;
3171 }
3172
3173 if (signal_pending(current))
3174 break;
3175 if (need_resched())
3176 schedule();
3177 }
3178
3179 preempt_disable();
3180 local_irq_disable();
3181
3182 vmx->invalid_state_emulation_result = err;
3183 }
3184
3185 /*
3186 * The exit handlers return 1 if the exit was handled fully and guest execution
3187 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3188 * to be done to userspace and return 0.
3189 */
3190 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3191 struct kvm_run *kvm_run) = {
3192 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3193 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3194 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3195 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3196 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3197 [EXIT_REASON_CR_ACCESS] = handle_cr,
3198 [EXIT_REASON_DR_ACCESS] = handle_dr,
3199 [EXIT_REASON_CPUID] = handle_cpuid,
3200 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3201 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3202 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3203 [EXIT_REASON_HLT] = handle_halt,
3204 [EXIT_REASON_INVLPG] = handle_invlpg,
3205 [EXIT_REASON_VMCALL] = handle_vmcall,
3206 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3207 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3208 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3209 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3210 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3211 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3212 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3213 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3214 [EXIT_REASON_VMON] = handle_vmx_insn,
3215 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3216 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3217 [EXIT_REASON_WBINVD] = handle_wbinvd,
3218 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3219 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3220 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3221 };
3222
3223 static const int kvm_vmx_max_exit_handlers =
3224 ARRAY_SIZE(kvm_vmx_exit_handlers);
3225
3226 /*
3227 * The guest has exited. See if we can fix it or if we need userspace
3228 * assistance.
3229 */
3230 static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3231 {
3232 struct vcpu_vmx *vmx = to_vmx(vcpu);
3233 u32 exit_reason = vmx->exit_reason;
3234 u32 vectoring_info = vmx->idt_vectoring_info;
3235
3236 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3237 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3238
3239 /* If we need to emulate an MMIO from handle_invalid_guest_state
3240 * we just return 0 */
3241 if (vmx->emulation_required && emulate_invalid_guest_state) {
3242 if (guest_state_valid(vcpu))
3243 vmx->emulation_required = 0;
3244 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
3245 }
3246
3247 /* Access CR3 don't cause VMExit in paging mode, so we need
3248 * to sync with guest real CR3. */
3249 if (enable_ept && is_paging(vcpu)) {
3250 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3251 ept_load_pdptrs(vcpu);
3252 }
3253
3254 if (unlikely(vmx->fail)) {
3255 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3256 kvm_run->fail_entry.hardware_entry_failure_reason
3257 = vmcs_read32(VM_INSTRUCTION_ERROR);
3258 return 0;
3259 }
3260
3261 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3262 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3263 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3264 exit_reason != EXIT_REASON_TASK_SWITCH))
3265 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3266 "(0x%x) and exit reason is 0x%x\n",
3267 __func__, vectoring_info, exit_reason);
3268
3269 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3270 if (vmx_interrupt_allowed(vcpu)) {
3271 vmx->soft_vnmi_blocked = 0;
3272 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3273 vcpu->arch.nmi_pending) {
3274 /*
3275 * This CPU don't support us in finding the end of an
3276 * NMI-blocked window if the guest runs with IRQs
3277 * disabled. So we pull the trigger after 1 s of
3278 * futile waiting, but inform the user about this.
3279 */
3280 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3281 "state on VCPU %d after 1 s timeout\n",
3282 __func__, vcpu->vcpu_id);
3283 vmx->soft_vnmi_blocked = 0;
3284 }
3285 }
3286
3287 if (exit_reason < kvm_vmx_max_exit_handlers
3288 && kvm_vmx_exit_handlers[exit_reason])
3289 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3290 else {
3291 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3292 kvm_run->hw.hardware_exit_reason = exit_reason;
3293 }
3294 return 0;
3295 }
3296
3297 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3298 {
3299 if (irr == -1 || tpr < irr) {
3300 vmcs_write32(TPR_THRESHOLD, 0);
3301 return;
3302 }
3303
3304 vmcs_write32(TPR_THRESHOLD, irr);
3305 }
3306
3307 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3308 {
3309 u32 exit_intr_info;
3310 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3311 bool unblock_nmi;
3312 u8 vector;
3313 int type;
3314 bool idtv_info_valid;
3315
3316 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3317
3318 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3319
3320 /* Handle machine checks before interrupts are enabled */
3321 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3322 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3323 && is_machine_check(exit_intr_info)))
3324 kvm_machine_check();
3325
3326 /* We need to handle NMIs before interrupts are enabled */
3327 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3328 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3329 KVMTRACE_0D(NMI, &vmx->vcpu, handler);
3330 asm("int $2");
3331 }
3332
3333 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3334
3335 if (cpu_has_virtual_nmis()) {
3336 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3337 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3338 /*
3339 * SDM 3: 27.7.1.2 (September 2008)
3340 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3341 * a guest IRET fault.
3342 * SDM 3: 23.2.2 (September 2008)
3343 * Bit 12 is undefined in any of the following cases:
3344 * If the VM exit sets the valid bit in the IDT-vectoring
3345 * information field.
3346 * If the VM exit is due to a double fault.
3347 */
3348 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3349 vector != DF_VECTOR && !idtv_info_valid)
3350 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3351 GUEST_INTR_STATE_NMI);
3352 } else if (unlikely(vmx->soft_vnmi_blocked))
3353 vmx->vnmi_blocked_time +=
3354 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3355
3356 vmx->vcpu.arch.nmi_injected = false;
3357 kvm_clear_exception_queue(&vmx->vcpu);
3358 kvm_clear_interrupt_queue(&vmx->vcpu);
3359
3360 if (!idtv_info_valid)
3361 return;
3362
3363 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3364 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3365
3366 switch (type) {
3367 case INTR_TYPE_NMI_INTR:
3368 vmx->vcpu.arch.nmi_injected = true;
3369 /*
3370 * SDM 3: 27.7.1.2 (September 2008)
3371 * Clear bit "block by NMI" before VM entry if a NMI
3372 * delivery faulted.
3373 */
3374 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3375 GUEST_INTR_STATE_NMI);
3376 break;
3377 case INTR_TYPE_SOFT_EXCEPTION:
3378 vmx->vcpu.arch.event_exit_inst_len =
3379 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3380 /* fall through */
3381 case INTR_TYPE_HARD_EXCEPTION:
3382 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3383 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3384 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3385 } else
3386 kvm_queue_exception(&vmx->vcpu, vector);
3387 break;
3388 case INTR_TYPE_SOFT_INTR:
3389 vmx->vcpu.arch.event_exit_inst_len =
3390 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3391 /* fall through */
3392 case INTR_TYPE_EXT_INTR:
3393 kvm_queue_interrupt(&vmx->vcpu, vector,
3394 type == INTR_TYPE_SOFT_INTR);
3395 break;
3396 default:
3397 break;
3398 }
3399 }
3400
3401 /*
3402 * Failure to inject an interrupt should give us the information
3403 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3404 * when fetching the interrupt redirection bitmap in the real-mode
3405 * tss, this doesn't happen. So we do it ourselves.
3406 */
3407 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3408 {
3409 vmx->rmode.irq.pending = 0;
3410 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3411 return;
3412 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3413 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3414 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3415 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3416 return;
3417 }
3418 vmx->idt_vectoring_info =
3419 VECTORING_INFO_VALID_MASK
3420 | INTR_TYPE_EXT_INTR
3421 | vmx->rmode.irq.vector;
3422 }
3423
3424 #ifdef CONFIG_X86_64
3425 #define R "r"
3426 #define Q "q"
3427 #else
3428 #define R "e"
3429 #define Q "l"
3430 #endif
3431
3432 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3433 {
3434 struct vcpu_vmx *vmx = to_vmx(vcpu);
3435
3436 /* Record the guest's net vcpu time for enforced NMI injections. */
3437 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3438 vmx->entry_time = ktime_get();
3439
3440 /* Handle invalid guest state instead of entering VMX */
3441 if (vmx->emulation_required && emulate_invalid_guest_state) {
3442 handle_invalid_guest_state(vcpu, kvm_run);
3443 return;
3444 }
3445
3446 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3447 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3448 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3449 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3450
3451 /*
3452 * Loading guest fpu may have cleared host cr0.ts
3453 */
3454 vmcs_writel(HOST_CR0, read_cr0());
3455
3456 set_debugreg(vcpu->arch.dr6, 6);
3457
3458 asm(
3459 /* Store host registers */
3460 "push %%"R"dx; push %%"R"bp;"
3461 "push %%"R"cx \n\t"
3462 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3463 "je 1f \n\t"
3464 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3465 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3466 "1: \n\t"
3467 /* Check if vmlaunch of vmresume is needed */
3468 "cmpl $0, %c[launched](%0) \n\t"
3469 /* Load guest registers. Don't clobber flags. */
3470 "mov %c[cr2](%0), %%"R"ax \n\t"
3471 "mov %%"R"ax, %%cr2 \n\t"
3472 "mov %c[rax](%0), %%"R"ax \n\t"
3473 "mov %c[rbx](%0), %%"R"bx \n\t"
3474 "mov %c[rdx](%0), %%"R"dx \n\t"
3475 "mov %c[rsi](%0), %%"R"si \n\t"
3476 "mov %c[rdi](%0), %%"R"di \n\t"
3477 "mov %c[rbp](%0), %%"R"bp \n\t"
3478 #ifdef CONFIG_X86_64
3479 "mov %c[r8](%0), %%r8 \n\t"
3480 "mov %c[r9](%0), %%r9 \n\t"
3481 "mov %c[r10](%0), %%r10 \n\t"
3482 "mov %c[r11](%0), %%r11 \n\t"
3483 "mov %c[r12](%0), %%r12 \n\t"
3484 "mov %c[r13](%0), %%r13 \n\t"
3485 "mov %c[r14](%0), %%r14 \n\t"
3486 "mov %c[r15](%0), %%r15 \n\t"
3487 #endif
3488 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3489
3490 /* Enter guest mode */
3491 "jne .Llaunched \n\t"
3492 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3493 "jmp .Lkvm_vmx_return \n\t"
3494 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3495 ".Lkvm_vmx_return: "
3496 /* Save guest registers, load host registers, keep flags */
3497 "xchg %0, (%%"R"sp) \n\t"
3498 "mov %%"R"ax, %c[rax](%0) \n\t"
3499 "mov %%"R"bx, %c[rbx](%0) \n\t"
3500 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3501 "mov %%"R"dx, %c[rdx](%0) \n\t"
3502 "mov %%"R"si, %c[rsi](%0) \n\t"
3503 "mov %%"R"di, %c[rdi](%0) \n\t"
3504 "mov %%"R"bp, %c[rbp](%0) \n\t"
3505 #ifdef CONFIG_X86_64
3506 "mov %%r8, %c[r8](%0) \n\t"
3507 "mov %%r9, %c[r9](%0) \n\t"
3508 "mov %%r10, %c[r10](%0) \n\t"
3509 "mov %%r11, %c[r11](%0) \n\t"
3510 "mov %%r12, %c[r12](%0) \n\t"
3511 "mov %%r13, %c[r13](%0) \n\t"
3512 "mov %%r14, %c[r14](%0) \n\t"
3513 "mov %%r15, %c[r15](%0) \n\t"
3514 #endif
3515 "mov %%cr2, %%"R"ax \n\t"
3516 "mov %%"R"ax, %c[cr2](%0) \n\t"
3517
3518 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3519 "setbe %c[fail](%0) \n\t"
3520 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3521 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3522 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3523 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3524 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3525 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3526 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3527 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3528 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3529 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3530 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3531 #ifdef CONFIG_X86_64
3532 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3533 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3534 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3535 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3536 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3537 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3538 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3539 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3540 #endif
3541 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3542 : "cc", "memory"
3543 , R"bx", R"di", R"si"
3544 #ifdef CONFIG_X86_64
3545 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3546 #endif
3547 );
3548
3549 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3550 vcpu->arch.regs_dirty = 0;
3551
3552 get_debugreg(vcpu->arch.dr6, 6);
3553
3554 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3555 if (vmx->rmode.irq.pending)
3556 fixup_rmode_irq(vmx);
3557
3558 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3559 vmx->launched = 1;
3560
3561 vmx_complete_interrupts(vmx);
3562 }
3563
3564 #undef R
3565 #undef Q
3566
3567 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3568 {
3569 struct vcpu_vmx *vmx = to_vmx(vcpu);
3570
3571 if (vmx->vmcs) {
3572 vcpu_clear(vmx);
3573 free_vmcs(vmx->vmcs);
3574 vmx->vmcs = NULL;
3575 }
3576 }
3577
3578 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3579 {
3580 struct vcpu_vmx *vmx = to_vmx(vcpu);
3581
3582 spin_lock(&vmx_vpid_lock);
3583 if (vmx->vpid != 0)
3584 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3585 spin_unlock(&vmx_vpid_lock);
3586 vmx_free_vmcs(vcpu);
3587 kfree(vmx->host_msrs);
3588 kfree(vmx->guest_msrs);
3589 kvm_vcpu_uninit(vcpu);
3590 kmem_cache_free(kvm_vcpu_cache, vmx);
3591 }
3592
3593 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3594 {
3595 int err;
3596 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3597 int cpu;
3598
3599 if (!vmx)
3600 return ERR_PTR(-ENOMEM);
3601
3602 allocate_vpid(vmx);
3603
3604 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3605 if (err)
3606 goto free_vcpu;
3607
3608 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3609 if (!vmx->guest_msrs) {
3610 err = -ENOMEM;
3611 goto uninit_vcpu;
3612 }
3613
3614 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3615 if (!vmx->host_msrs)
3616 goto free_guest_msrs;
3617
3618 vmx->vmcs = alloc_vmcs();
3619 if (!vmx->vmcs)
3620 goto free_msrs;
3621
3622 vmcs_clear(vmx->vmcs);
3623
3624 cpu = get_cpu();
3625 vmx_vcpu_load(&vmx->vcpu, cpu);
3626 err = vmx_vcpu_setup(vmx);
3627 vmx_vcpu_put(&vmx->vcpu);
3628 put_cpu();
3629 if (err)
3630 goto free_vmcs;
3631 if (vm_need_virtualize_apic_accesses(kvm))
3632 if (alloc_apic_access_page(kvm) != 0)
3633 goto free_vmcs;
3634
3635 if (enable_ept)
3636 if (alloc_identity_pagetable(kvm) != 0)
3637 goto free_vmcs;
3638
3639 return &vmx->vcpu;
3640
3641 free_vmcs:
3642 free_vmcs(vmx->vmcs);
3643 free_msrs:
3644 kfree(vmx->host_msrs);
3645 free_guest_msrs:
3646 kfree(vmx->guest_msrs);
3647 uninit_vcpu:
3648 kvm_vcpu_uninit(&vmx->vcpu);
3649 free_vcpu:
3650 kmem_cache_free(kvm_vcpu_cache, vmx);
3651 return ERR_PTR(err);
3652 }
3653
3654 static void __init vmx_check_processor_compat(void *rtn)
3655 {
3656 struct vmcs_config vmcs_conf;
3657
3658 *(int *)rtn = 0;
3659 if (setup_vmcs_config(&vmcs_conf) < 0)
3660 *(int *)rtn = -EIO;
3661 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3662 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3663 smp_processor_id());
3664 *(int *)rtn = -EIO;
3665 }
3666 }
3667
3668 static int get_ept_level(void)
3669 {
3670 return VMX_EPT_DEFAULT_GAW + 1;
3671 }
3672
3673 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3674 {
3675 u64 ret;
3676
3677 /* For VT-d and EPT combination
3678 * 1. MMIO: always map as UC
3679 * 2. EPT with VT-d:
3680 * a. VT-d without snooping control feature: can't guarantee the
3681 * result, try to trust guest.
3682 * b. VT-d with snooping control feature: snooping control feature of
3683 * VT-d engine can guarantee the cache correctness. Just set it
3684 * to WB to keep consistent with host. So the same as item 3.
3685 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3686 * consistent with host MTRR
3687 */
3688 if (is_mmio)
3689 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3690 else if (vcpu->kvm->arch.iommu_domain &&
3691 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3692 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3693 VMX_EPT_MT_EPTE_SHIFT;
3694 else
3695 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3696 | VMX_EPT_IGMT_BIT;
3697
3698 return ret;
3699 }
3700
3701 static struct kvm_x86_ops vmx_x86_ops = {
3702 .cpu_has_kvm_support = cpu_has_kvm_support,
3703 .disabled_by_bios = vmx_disabled_by_bios,
3704 .hardware_setup = hardware_setup,
3705 .hardware_unsetup = hardware_unsetup,
3706 .check_processor_compatibility = vmx_check_processor_compat,
3707 .hardware_enable = hardware_enable,
3708 .hardware_disable = hardware_disable,
3709 .cpu_has_accelerated_tpr = report_flexpriority,
3710
3711 .vcpu_create = vmx_create_vcpu,
3712 .vcpu_free = vmx_free_vcpu,
3713 .vcpu_reset = vmx_vcpu_reset,
3714
3715 .prepare_guest_switch = vmx_save_host_state,
3716 .vcpu_load = vmx_vcpu_load,
3717 .vcpu_put = vmx_vcpu_put,
3718
3719 .set_guest_debug = set_guest_debug,
3720 .get_msr = vmx_get_msr,
3721 .set_msr = vmx_set_msr,
3722 .get_segment_base = vmx_get_segment_base,
3723 .get_segment = vmx_get_segment,
3724 .set_segment = vmx_set_segment,
3725 .get_cpl = vmx_get_cpl,
3726 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3727 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3728 .set_cr0 = vmx_set_cr0,
3729 .set_cr3 = vmx_set_cr3,
3730 .set_cr4 = vmx_set_cr4,
3731 .set_efer = vmx_set_efer,
3732 .get_idt = vmx_get_idt,
3733 .set_idt = vmx_set_idt,
3734 .get_gdt = vmx_get_gdt,
3735 .set_gdt = vmx_set_gdt,
3736 .cache_reg = vmx_cache_reg,
3737 .get_rflags = vmx_get_rflags,
3738 .set_rflags = vmx_set_rflags,
3739
3740 .tlb_flush = vmx_flush_tlb,
3741
3742 .run = vmx_vcpu_run,
3743 .handle_exit = vmx_handle_exit,
3744 .skip_emulated_instruction = skip_emulated_instruction,
3745 .set_interrupt_shadow = vmx_set_interrupt_shadow,
3746 .get_interrupt_shadow = vmx_get_interrupt_shadow,
3747 .patch_hypercall = vmx_patch_hypercall,
3748 .set_irq = vmx_inject_irq,
3749 .set_nmi = vmx_inject_nmi,
3750 .queue_exception = vmx_queue_exception,
3751 .interrupt_allowed = vmx_interrupt_allowed,
3752 .nmi_allowed = vmx_nmi_allowed,
3753 .enable_nmi_window = enable_nmi_window,
3754 .enable_irq_window = enable_irq_window,
3755 .update_cr8_intercept = update_cr8_intercept,
3756
3757 .set_tss_addr = vmx_set_tss_addr,
3758 .get_tdp_level = get_ept_level,
3759 .get_mt_mask = vmx_get_mt_mask,
3760 };
3761
3762 static int __init vmx_init(void)
3763 {
3764 int r;
3765
3766 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
3767 if (!vmx_io_bitmap_a)
3768 return -ENOMEM;
3769
3770 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
3771 if (!vmx_io_bitmap_b) {
3772 r = -ENOMEM;
3773 goto out;
3774 }
3775
3776 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3777 if (!vmx_msr_bitmap_legacy) {
3778 r = -ENOMEM;
3779 goto out1;
3780 }
3781
3782 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
3783 if (!vmx_msr_bitmap_longmode) {
3784 r = -ENOMEM;
3785 goto out2;
3786 }
3787
3788 /*
3789 * Allow direct access to the PC debug port (it is often used for I/O
3790 * delays, but the vmexits simply slow things down).
3791 */
3792 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
3793 clear_bit(0x80, vmx_io_bitmap_a);
3794
3795 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
3796
3797 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
3798 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3799
3800 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3801
3802 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3803 if (r)
3804 goto out3;
3805
3806 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
3807 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
3808 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
3809 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
3810 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
3811 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
3812
3813 if (enable_ept) {
3814 bypass_guest_pf = 0;
3815 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3816 VMX_EPT_WRITABLE_MASK);
3817 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3818 VMX_EPT_EXECUTABLE_MASK);
3819 kvm_enable_tdp();
3820 } else
3821 kvm_disable_tdp();
3822
3823 if (bypass_guest_pf)
3824 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3825
3826 ept_sync_global();
3827
3828 return 0;
3829
3830 out3:
3831 free_page((unsigned long)vmx_msr_bitmap_longmode);
3832 out2:
3833 free_page((unsigned long)vmx_msr_bitmap_legacy);
3834 out1:
3835 free_page((unsigned long)vmx_io_bitmap_b);
3836 out:
3837 free_page((unsigned long)vmx_io_bitmap_a);
3838 return r;
3839 }
3840
3841 static void __exit vmx_exit(void)
3842 {
3843 free_page((unsigned long)vmx_msr_bitmap_legacy);
3844 free_page((unsigned long)vmx_msr_bitmap_longmode);
3845 free_page((unsigned long)vmx_io_bitmap_b);
3846 free_page((unsigned long)vmx_io_bitmap_a);
3847
3848 kvm_exit();
3849 }
3850
3851 module_init(vmx_init)
3852 module_exit(vmx_exit)
3853
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