1 /*
2 * 8253/8254 interval timer emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2006 Intel Corporation
6 * Copyright (c) 2007 Keir Fraser, XenSource Inc
7 * Copyright (c) 2008 Intel Corporation
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
26 *
27 * Authors:
28 * Sheng Yang <sheng.yang@intel.com>
29 * Based on QEMU and Xen.
30 */
31
32 #include <linux/kvm_host.h>
33
34 #include "irq.h"
35 #include "i8254.h"
36
37 #ifndef CONFIG_X86_64
38 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
39 #else
40 #define mod_64(x, y) ((x) % (y))
41 #endif
42
43 #define RW_STATE_LSB 1
44 #define RW_STATE_MSB 2
45 #define RW_STATE_WORD0 3
46 #define RW_STATE_WORD1 4
47
48 /* Compute with 96 bit intermediate result: (a*b)/c */
49 static u64 muldiv64(u64 a, u32 b, u32 c)
50 {
51 union {
52 u64 ll;
53 struct {
54 u32 low, high;
55 } l;
56 } u, res;
57 u64 rl, rh;
58
59 u.ll = a;
60 rl = (u64)u.l.low * (u64)b;
61 rh = (u64)u.l.high * (u64)b;
62 rh += (rl >> 32);
63 res.l.high = div64_u64(rh, c);
64 res.l.low = div64_u64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c);
65 return res.ll;
66 }
67
68 static void pit_set_gate(struct kvm *kvm, int channel, u32 val)
69 {
70 struct kvm_kpit_channel_state *c =
71 &kvm->arch.vpit->pit_state.channels[channel];
72
73 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
74
75 switch (c->mode) {
76 default:
77 case 0:
78 case 4:
79 /* XXX: just disable/enable counting */
80 break;
81 case 1:
82 case 2:
83 case 3:
84 case 5:
85 /* Restart counting on rising edge. */
86 if (c->gate < val)
87 c->count_load_time = ktime_get();
88 break;
89 }
90
91 c->gate = val;
92 }
93
94 static int pit_get_gate(struct kvm *kvm, int channel)
95 {
96 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
97
98 return kvm->arch.vpit->pit_state.channels[channel].gate;
99 }
100
101 static s64 __kpit_elapsed(struct kvm *kvm)
102 {
103 s64 elapsed;
104 ktime_t remaining;
105 struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;
106
107 if (!ps->pit_timer.period)
108 return 0;
109
110 /*
111 * The Counter does not stop when it reaches zero. In
112 * Modes 0, 1, 4, and 5 the Counter ``wraps around'' to
113 * the highest count, either FFFF hex for binary counting
114 * or 9999 for BCD counting, and continues counting.
115 * Modes 2 and 3 are periodic; the Counter reloads
116 * itself with the initial count and continues counting
117 * from there.
118 */
119 remaining = hrtimer_get_remaining(&ps->pit_timer.timer);
120 elapsed = ps->pit_timer.period - ktime_to_ns(remaining);
121 elapsed = mod_64(elapsed, ps->pit_timer.period);
122
123 return elapsed;
124 }
125
126 static s64 kpit_elapsed(struct kvm *kvm, struct kvm_kpit_channel_state *c,
127 int channel)
128 {
129 if (channel == 0)
130 return __kpit_elapsed(kvm);
131
132 return ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
133 }
134
135 static int pit_get_count(struct kvm *kvm, int channel)
136 {
137 struct kvm_kpit_channel_state *c =
138 &kvm->arch.vpit->pit_state.channels[channel];
139 s64 d, t;
140 int counter;
141
142 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
143
144 t = kpit_elapsed(kvm, c, channel);
145 d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
146
147 switch (c->mode) {
148 case 0:
149 case 1:
150 case 4:
151 case 5:
152 counter = (c->count - d) & 0xffff;
153 break;
154 case 3:
155 /* XXX: may be incorrect for odd counts */
156 counter = c->count - (mod_64((2 * d), c->count));
157 break;
158 default:
159 counter = c->count - mod_64(d, c->count);
160 break;
161 }
162 return counter;
163 }
164
165 static int pit_get_out(struct kvm *kvm, int channel)
166 {
167 struct kvm_kpit_channel_state *c =
168 &kvm->arch.vpit->pit_state.channels[channel];
169 s64 d, t;
170 int out;
171
172 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
173
174 t = kpit_elapsed(kvm, c, channel);
175 d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
176
177 switch (c->mode) {
178 default:
179 case 0:
180 out = (d >= c->count);
181 break;
182 case 1:
183 out = (d < c->count);
184 break;
185 case 2:
186 out = ((mod_64(d, c->count) == 0) && (d != 0));
187 break;
188 case 3:
189 out = (mod_64(d, c->count) < ((c->count + 1) >> 1));
190 break;
191 case 4:
192 case 5:
193 out = (d == c->count);
194 break;
195 }
196
197 return out;
198 }
199
200 static void pit_latch_count(struct kvm *kvm, int channel)
201 {
202 struct kvm_kpit_channel_state *c =
203 &kvm->arch.vpit->pit_state.channels[channel];
204
205 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
206
207 if (!c->count_latched) {
208 c->latched_count = pit_get_count(kvm, channel);
209 c->count_latched = c->rw_mode;
210 }
211 }
212
213 static void pit_latch_status(struct kvm *kvm, int channel)
214 {
215 struct kvm_kpit_channel_state *c =
216 &kvm->arch.vpit->pit_state.channels[channel];
217
218 WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
219
220 if (!c->status_latched) {
221 /* TODO: Return NULL COUNT (bit 6). */
222 c->status = ((pit_get_out(kvm, channel) << 7) |
223 (c->rw_mode << 4) |
224 (c->mode << 1) |
225 c->bcd);
226 c->status_latched = 1;
227 }
228 }
229
230 int pit_has_pending_timer(struct kvm_vcpu *vcpu)
231 {
232 struct kvm_pit *pit = vcpu->kvm->arch.vpit;
233
234 if (pit && vcpu->vcpu_id == 0 && pit->pit_state.irq_ack)
235 return atomic_read(&pit->pit_state.pit_timer.pending);
236 return 0;
237 }
238
239 static void kvm_pit_ack_irq(struct kvm_irq_ack_notifier *kian)
240 {
241 struct kvm_kpit_state *ps = container_of(kian, struct kvm_kpit_state,
242 irq_ack_notifier);
243 spin_lock(&ps->inject_lock);
244 if (atomic_dec_return(&ps->pit_timer.pending) < 0)
245 atomic_inc(&ps->pit_timer.pending);
246 ps->irq_ack = 1;
247 spin_unlock(&ps->inject_lock);
248 }
249
250 void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu)
251 {
252 struct kvm_pit *pit = vcpu->kvm->arch.vpit;
253 struct hrtimer *timer;
254
255 if (vcpu->vcpu_id != 0 || !pit)
256 return;
257
258 timer = &pit->pit_state.pit_timer.timer;
259 if (hrtimer_cancel(timer))
260 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
261 }
262
263 static void destroy_pit_timer(struct kvm_timer *pt)
264 {
265 pr_debug("pit: execute del timer!\n");
266 hrtimer_cancel(&pt->timer);
267 }
268
269 static bool kpit_is_periodic(struct kvm_timer *ktimer)
270 {
271 struct kvm_kpit_state *ps = container_of(ktimer, struct kvm_kpit_state,
272 pit_timer);
273 return ps->is_periodic;
274 }
275
276 static struct kvm_timer_ops kpit_ops = {
277 .is_periodic = kpit_is_periodic,
278 };
279
280 static void create_pit_timer(struct kvm_kpit_state *ps, u32 val, int is_period)
281 {
282 struct kvm_timer *pt = &ps->pit_timer;
283 s64 interval;
284
285 interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ);
286
287 pr_debug("pit: create pit timer, interval is %llu nsec\n", interval);
288
289 /* TODO The new value only affected after the retriggered */
290 hrtimer_cancel(&pt->timer);
291 pt->period = interval;
292 ps->is_periodic = is_period;
293
294 pt->timer.function = kvm_timer_fn;
295 pt->t_ops = &kpit_ops;
296 pt->kvm = ps->pit->kvm;
297 pt->vcpu_id = 0;
298
299 atomic_set(&pt->pending, 0);
300 ps->irq_ack = 1;
301
302 hrtimer_start(&pt->timer, ktime_add_ns(ktime_get(), interval),
303 HRTIMER_MODE_ABS);
304 }
305
306 static void pit_load_count(struct kvm *kvm, int channel, u32 val)
307 {
308 struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;
309
310 WARN_ON(!mutex_is_locked(&ps->lock));
311
312 pr_debug("pit: load_count val is %d, channel is %d\n", val, channel);
313
314 /*
315 * The largest possible initial count is 0; this is equivalent
316 * to 216 for binary counting and 104 for BCD counting.
317 */
318 if (val == 0)
319 val = 0x10000;
320
321 ps->channels[channel].count = val;
322
323 if (channel != 0) {
324 ps->channels[channel].count_load_time = ktime_get();
325 return;
326 }
327
328 /* Two types of timer
329 * mode 1 is one shot, mode 2 is period, otherwise del timer */
330 switch (ps->channels[0].mode) {
331 case 0:
332 case 1:
333 /* FIXME: enhance mode 4 precision */
334 case 4:
335 create_pit_timer(ps, val, 0);
336 break;
337 case 2:
338 case 3:
339 create_pit_timer(ps, val, 1);
340 break;
341 default:
342 destroy_pit_timer(&ps->pit_timer);
343 }
344 }
345
346 void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val)
347 {
348 mutex_lock(&kvm->arch.vpit->pit_state.lock);
349 pit_load_count(kvm, channel, val);
350 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
351 }
352
353 static void pit_ioport_write(struct kvm_io_device *this,
354 gpa_t addr, int len, const void *data)
355 {
356 struct kvm_pit *pit = (struct kvm_pit *)this->private;
357 struct kvm_kpit_state *pit_state = &pit->pit_state;
358 struct kvm *kvm = pit->kvm;
359 int channel, access;
360 struct kvm_kpit_channel_state *s;
361 u32 val = *(u32 *) data;
362
363 val &= 0xff;
364 addr &= KVM_PIT_CHANNEL_MASK;
365
366 mutex_lock(&pit_state->lock);
367
368 if (val != 0)
369 pr_debug("pit: write addr is 0x%x, len is %d, val is 0x%x\n",
370 (unsigned int)addr, len, val);
371
372 if (addr == 3) {
373 channel = val >> 6;
374 if (channel == 3) {
375 /* Read-Back Command. */
376 for (channel = 0; channel < 3; channel++) {
377 s = &pit_state->channels[channel];
378 if (val & (2 << channel)) {
379 if (!(val & 0x20))
380 pit_latch_count(kvm, channel);
381 if (!(val & 0x10))
382 pit_latch_status(kvm, channel);
383 }
384 }
385 } else {
386 /* Select Counter <channel>. */
387 s = &pit_state->channels[channel];
388 access = (val >> 4) & KVM_PIT_CHANNEL_MASK;
389 if (access == 0) {
390 pit_latch_count(kvm, channel);
391 } else {
392 s->rw_mode = access;
393 s->read_state = access;
394 s->write_state = access;
395 s->mode = (val >> 1) & 7;
396 if (s->mode > 5)
397 s->mode -= 4;
398 s->bcd = val & 1;
399 }
400 }
401 } else {
402 /* Write Count. */
403 s = &pit_state->channels[addr];
404 switch (s->write_state) {
405 default:
406 case RW_STATE_LSB:
407 pit_load_count(kvm, addr, val);
408 break;
409 case RW_STATE_MSB:
410 pit_load_count(kvm, addr, val << 8);
411 break;
412 case RW_STATE_WORD0:
413 s->write_latch = val;
414 s->write_state = RW_STATE_WORD1;
415 break;
416 case RW_STATE_WORD1:
417 pit_load_count(kvm, addr, s->write_latch | (val << 8));
418 s->write_state = RW_STATE_WORD0;
419 break;
420 }
421 }
422
423 mutex_unlock(&pit_state->lock);
424 }
425
426 static void pit_ioport_read(struct kvm_io_device *this,
427 gpa_t addr, int len, void *data)
428 {
429 struct kvm_pit *pit = (struct kvm_pit *)this->private;
430 struct kvm_kpit_state *pit_state = &pit->pit_state;
431 struct kvm *kvm = pit->kvm;
432 int ret, count;
433 struct kvm_kpit_channel_state *s;
434
435 addr &= KVM_PIT_CHANNEL_MASK;
436 s = &pit_state->channels[addr];
437
438 mutex_lock(&pit_state->lock);
439
440 if (s->status_latched) {
441 s->status_latched = 0;
442 ret = s->status;
443 } else if (s->count_latched) {
444 switch (s->count_latched) {
445 default:
446 case RW_STATE_LSB:
447 ret = s->latched_count & 0xff;
448 s->count_latched = 0;
449 break;
450 case RW_STATE_MSB:
451 ret = s->latched_count >> 8;
452 s->count_latched = 0;
453 break;
454 case RW_STATE_WORD0:
455 ret = s->latched_count & 0xff;
456 s->count_latched = RW_STATE_MSB;
457 break;
458 }
459 } else {
460 switch (s->read_state) {
461 default:
462 case RW_STATE_LSB:
463 count = pit_get_count(kvm, addr);
464 ret = count & 0xff;
465 break;
466 case RW_STATE_MSB:
467 count = pit_get_count(kvm, addr);
468 ret = (count >> 8) & 0xff;
469 break;
470 case RW_STATE_WORD0:
471 count = pit_get_count(kvm, addr);
472 ret = count & 0xff;
473 s->read_state = RW_STATE_WORD1;
474 break;
475 case RW_STATE_WORD1:
476 count = pit_get_count(kvm, addr);
477 ret = (count >> 8) & 0xff;
478 s->read_state = RW_STATE_WORD0;
479 break;
480 }
481 }
482
483 if (len > sizeof(ret))
484 len = sizeof(ret);
485 memcpy(data, (char *)&ret, len);
486
487 mutex_unlock(&pit_state->lock);
488 }
489
490 static int pit_in_range(struct kvm_io_device *this, gpa_t addr,
491 int len, int is_write)
492 {
493 return ((addr >= KVM_PIT_BASE_ADDRESS) &&
494 (addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH));
495 }
496
497 static void speaker_ioport_write(struct kvm_io_device *this,
498 gpa_t addr, int len, const void *data)
499 {
500 struct kvm_pit *pit = (struct kvm_pit *)this->private;
501 struct kvm_kpit_state *pit_state = &pit->pit_state;
502 struct kvm *kvm = pit->kvm;
503 u32 val = *(u32 *) data;
504
505 mutex_lock(&pit_state->lock);
506 pit_state->speaker_data_on = (val >> 1) & 1;
507 pit_set_gate(kvm, 2, val & 1);
508 mutex_unlock(&pit_state->lock);
509 }
510
511 static void speaker_ioport_read(struct kvm_io_device *this,
512 gpa_t addr, int len, void *data)
513 {
514 struct kvm_pit *pit = (struct kvm_pit *)this->private;
515 struct kvm_kpit_state *pit_state = &pit->pit_state;
516 struct kvm *kvm = pit->kvm;
517 unsigned int refresh_clock;
518 int ret;
519
520 /* Refresh clock toggles at about 15us. We approximate as 2^14ns. */
521 refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1;
522
523 mutex_lock(&pit_state->lock);
524 ret = ((pit_state->speaker_data_on << 1) | pit_get_gate(kvm, 2) |
525 (pit_get_out(kvm, 2) << 5) | (refresh_clock << 4));
526 if (len > sizeof(ret))
527 len = sizeof(ret);
528 memcpy(data, (char *)&ret, len);
529 mutex_unlock(&pit_state->lock);
530 }
531
532 static int speaker_in_range(struct kvm_io_device *this, gpa_t addr,
533 int len, int is_write)
534 {
535 return (addr == KVM_SPEAKER_BASE_ADDRESS);
536 }
537
538 void kvm_pit_reset(struct kvm_pit *pit)
539 {
540 int i;
541 struct kvm_kpit_channel_state *c;
542
543 mutex_lock(&pit->pit_state.lock);
544 for (i = 0; i < 3; i++) {
545 c = &pit->pit_state.channels[i];
546 c->mode = 0xff;
547 c->gate = (i != 2);
548 pit_load_count(pit->kvm, i, 0);
549 }
550 mutex_unlock(&pit->pit_state.lock);
551
552 atomic_set(&pit->pit_state.pit_timer.pending, 0);
553 pit->pit_state.irq_ack = 1;
554 }
555
556 static void pit_mask_notifer(struct kvm_irq_mask_notifier *kimn, bool mask)
557 {
558 struct kvm_pit *pit = container_of(kimn, struct kvm_pit, mask_notifier);
559
560 if (!mask) {
561 atomic_set(&pit->pit_state.pit_timer.pending, 0);
562 pit->pit_state.irq_ack = 1;
563 }
564 }
565
566 struct kvm_pit *kvm_create_pit(struct kvm *kvm)
567 {
568 struct kvm_pit *pit;
569 struct kvm_kpit_state *pit_state;
570
571 pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL);
572 if (!pit)
573 return NULL;
574
575 pit->irq_source_id = kvm_request_irq_source_id(kvm);
576 if (pit->irq_source_id < 0) {
577 kfree(pit);
578 return NULL;
579 }
580
581 mutex_init(&pit->pit_state.lock);
582 mutex_lock(&pit->pit_state.lock);
583 spin_lock_init(&pit->pit_state.inject_lock);
584
585 /* Initialize PIO device */
586 pit->dev.read = pit_ioport_read;
587 pit->dev.write = pit_ioport_write;
588 pit->dev.in_range = pit_in_range;
589 pit->dev.private = pit;
590 kvm_io_bus_register_dev(&kvm->pio_bus, &pit->dev);
591
592 pit->speaker_dev.read = speaker_ioport_read;
593 pit->speaker_dev.write = speaker_ioport_write;
594 pit->speaker_dev.in_range = speaker_in_range;
595 pit->speaker_dev.private = pit;
596 kvm_io_bus_register_dev(&kvm->pio_bus, &pit->speaker_dev);
597
598 kvm->arch.vpit = pit;
599 pit->kvm = kvm;
600
601 pit_state = &pit->pit_state;
602 pit_state->pit = pit;
603 hrtimer_init(&pit_state->pit_timer.timer,
604 CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
605 pit_state->irq_ack_notifier.gsi = 0;
606 pit_state->irq_ack_notifier.irq_acked = kvm_pit_ack_irq;
607 kvm_register_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier);
608 pit_state->pit_timer.reinject = true;
609 mutex_unlock(&pit->pit_state.lock);
610
611 kvm_pit_reset(pit);
612
613 pit->mask_notifier.func = pit_mask_notifer;
614 kvm_register_irq_mask_notifier(kvm, 0, &pit->mask_notifier);
615
616 return pit;
617 }
618
619 void kvm_free_pit(struct kvm *kvm)
620 {
621 struct hrtimer *timer;
622
623 if (kvm->arch.vpit) {
624 kvm_unregister_irq_mask_notifier(kvm, 0,
625 &kvm->arch.vpit->mask_notifier);
626 mutex_lock(&kvm->arch.vpit->pit_state.lock);
627 timer = &kvm->arch.vpit->pit_state.pit_timer.timer;
628 hrtimer_cancel(timer);
629 kvm_free_irq_source_id(kvm, kvm->arch.vpit->irq_source_id);
630 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
631 kfree(kvm->arch.vpit);
632 }
633 }
634
635 static void __inject_pit_timer_intr(struct kvm *kvm)
636 {
637 struct kvm_vcpu *vcpu;
638 int i;
639
640 mutex_lock(&kvm->lock);
641 kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1);
642 kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0);
643 mutex_unlock(&kvm->lock);
644
645 /*
646 * Provides NMI watchdog support via Virtual Wire mode.
647 * The route is: PIT -> PIC -> LVT0 in NMI mode.
648 *
649 * Note: Our Virtual Wire implementation is simplified, only
650 * propagating PIT interrupts to all VCPUs when they have set
651 * LVT0 to NMI delivery. Other PIC interrupts are just sent to
652 * VCPU0, and only if its LVT0 is in EXTINT mode.
653 */
654 if (kvm->arch.vapics_in_nmi_mode > 0)
655 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
656 vcpu = kvm->vcpus[i];
657 if (vcpu)
658 kvm_apic_nmi_wd_deliver(vcpu);
659 }
660 }
661
662 void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
663 {
664 struct kvm_pit *pit = vcpu->kvm->arch.vpit;
665 struct kvm *kvm = vcpu->kvm;
666 struct kvm_kpit_state *ps;
667
668 if (vcpu && pit) {
669 int inject = 0;
670 ps = &pit->pit_state;
671
672 /* Try to inject pending interrupts when
673 * last one has been acked.
674 */
675 spin_lock(&ps->inject_lock);
676 if (atomic_read(&ps->pit_timer.pending) && ps->irq_ack) {
677 ps->irq_ack = 0;
678 inject = 1;
679 }
680 spin_unlock(&ps->inject_lock);
681 if (inject)
682 __inject_pit_timer_intr(kvm);
683 }
684 }
685
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