1 #include <linux/errno.h>
2 #include <linux/kernel.h>
3 #include <linux/mm.h>
4 #include <linux/smp.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
9 #include <linux/pm.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <trace/power.h>
13 #include <asm/system.h>
14 #include <asm/apic.h>
15 #include <asm/syscalls.h>
16 #include <asm/idle.h>
17 #include <asm/uaccess.h>
18 #include <asm/i387.h>
19 #include <asm/ds.h>
20
21 unsigned long idle_halt;
22 EXPORT_SYMBOL(idle_halt);
23 unsigned long idle_nomwait;
24 EXPORT_SYMBOL(idle_nomwait);
25
26 struct kmem_cache *task_xstate_cachep;
27
28 DEFINE_TRACE(power_start);
29 DEFINE_TRACE(power_end);
30
31 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
32 {
33 *dst = *src;
34 if (src->thread.xstate) {
35 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
36 GFP_KERNEL);
37 if (!dst->thread.xstate)
38 return -ENOMEM;
39 WARN_ON((unsigned long)dst->thread.xstate & 15);
40 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
41 }
42 return 0;
43 }
44
45 void free_thread_xstate(struct task_struct *tsk)
46 {
47 if (tsk->thread.xstate) {
48 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
49 tsk->thread.xstate = NULL;
50 }
51
52 WARN(tsk->thread.ds_ctx, "leaking DS context\n");
53 }
54
55 void free_thread_info(struct thread_info *ti)
56 {
57 free_thread_xstate(ti->task);
58 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
59 }
60
61 void arch_task_cache_init(void)
62 {
63 task_xstate_cachep =
64 kmem_cache_create("task_xstate", xstate_size,
65 __alignof__(union thread_xstate),
66 SLAB_PANIC | SLAB_NOTRACK, NULL);
67 }
68
69 /*
70 * Free current thread data structures etc..
71 */
72 void exit_thread(void)
73 {
74 struct task_struct *me = current;
75 struct thread_struct *t = &me->thread;
76 unsigned long *bp = t->io_bitmap_ptr;
77
78 if (bp) {
79 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
80
81 t->io_bitmap_ptr = NULL;
82 clear_thread_flag(TIF_IO_BITMAP);
83 /*
84 * Careful, clear this in the TSS too:
85 */
86 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
87 t->io_bitmap_max = 0;
88 put_cpu();
89 kfree(bp);
90 }
91 }
92
93 void flush_thread(void)
94 {
95 struct task_struct *tsk = current;
96
97 clear_tsk_thread_flag(tsk, TIF_DEBUG);
98
99 tsk->thread.debugreg0 = 0;
100 tsk->thread.debugreg1 = 0;
101 tsk->thread.debugreg2 = 0;
102 tsk->thread.debugreg3 = 0;
103 tsk->thread.debugreg6 = 0;
104 tsk->thread.debugreg7 = 0;
105 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
106 /*
107 * Forget coprocessor state..
108 */
109 tsk->fpu_counter = 0;
110 clear_fpu(tsk);
111 clear_used_math();
112 }
113
114 static void hard_disable_TSC(void)
115 {
116 write_cr4(read_cr4() | X86_CR4_TSD);
117 }
118
119 void disable_TSC(void)
120 {
121 preempt_disable();
122 if (!test_and_set_thread_flag(TIF_NOTSC))
123 /*
124 * Must flip the CPU state synchronously with
125 * TIF_NOTSC in the current running context.
126 */
127 hard_disable_TSC();
128 preempt_enable();
129 }
130
131 static void hard_enable_TSC(void)
132 {
133 write_cr4(read_cr4() & ~X86_CR4_TSD);
134 }
135
136 static void enable_TSC(void)
137 {
138 preempt_disable();
139 if (test_and_clear_thread_flag(TIF_NOTSC))
140 /*
141 * Must flip the CPU state synchronously with
142 * TIF_NOTSC in the current running context.
143 */
144 hard_enable_TSC();
145 preempt_enable();
146 }
147
148 int get_tsc_mode(unsigned long adr)
149 {
150 unsigned int val;
151
152 if (test_thread_flag(TIF_NOTSC))
153 val = PR_TSC_SIGSEGV;
154 else
155 val = PR_TSC_ENABLE;
156
157 return put_user(val, (unsigned int __user *)adr);
158 }
159
160 int set_tsc_mode(unsigned int val)
161 {
162 if (val == PR_TSC_SIGSEGV)
163 disable_TSC();
164 else if (val == PR_TSC_ENABLE)
165 enable_TSC();
166 else
167 return -EINVAL;
168
169 return 0;
170 }
171
172 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
173 struct tss_struct *tss)
174 {
175 struct thread_struct *prev, *next;
176
177 prev = &prev_p->thread;
178 next = &next_p->thread;
179
180 if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
181 test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
182 ds_switch_to(prev_p, next_p);
183 else if (next->debugctlmsr != prev->debugctlmsr)
184 update_debugctlmsr(next->debugctlmsr);
185
186 if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
187 set_debugreg(next->debugreg0, 0);
188 set_debugreg(next->debugreg1, 1);
189 set_debugreg(next->debugreg2, 2);
190 set_debugreg(next->debugreg3, 3);
191 /* no 4 and 5 */
192 set_debugreg(next->debugreg6, 6);
193 set_debugreg(next->debugreg7, 7);
194 }
195
196 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
197 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
198 /* prev and next are different */
199 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
200 hard_disable_TSC();
201 else
202 hard_enable_TSC();
203 }
204
205 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
206 /*
207 * Copy the relevant range of the IO bitmap.
208 * Normally this is 128 bytes or less:
209 */
210 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
211 max(prev->io_bitmap_max, next->io_bitmap_max));
212 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
213 /*
214 * Clear any possible leftover bits:
215 */
216 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
217 }
218 }
219
220 int sys_fork(struct pt_regs *regs)
221 {
222 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
223 }
224
225 /*
226 * This is trivial, and on the face of it looks like it
227 * could equally well be done in user mode.
228 *
229 * Not so, for quite unobvious reasons - register pressure.
230 * In user mode vfork() cannot have a stack frame, and if
231 * done by calling the "clone()" system call directly, you
232 * do not have enough call-clobbered registers to hold all
233 * the information you need.
234 */
235 int sys_vfork(struct pt_regs *regs)
236 {
237 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
238 NULL, NULL);
239 }
240
241
242 /*
243 * Idle related variables and functions
244 */
245 unsigned long boot_option_idle_override = 0;
246 EXPORT_SYMBOL(boot_option_idle_override);
247
248 /*
249 * Powermanagement idle function, if any..
250 */
251 void (*pm_idle)(void);
252 EXPORT_SYMBOL(pm_idle);
253
254 #ifdef CONFIG_X86_32
255 /*
256 * This halt magic was a workaround for ancient floppy DMA
257 * wreckage. It should be safe to remove.
258 */
259 static int hlt_counter;
260 void disable_hlt(void)
261 {
262 hlt_counter++;
263 }
264 EXPORT_SYMBOL(disable_hlt);
265
266 void enable_hlt(void)
267 {
268 hlt_counter--;
269 }
270 EXPORT_SYMBOL(enable_hlt);
271
272 static inline int hlt_use_halt(void)
273 {
274 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
275 }
276 #else
277 static inline int hlt_use_halt(void)
278 {
279 return 1;
280 }
281 #endif
282
283 /*
284 * We use this if we don't have any better
285 * idle routine..
286 */
287 void default_idle(void)
288 {
289 if (hlt_use_halt()) {
290 struct power_trace it;
291
292 trace_power_start(&it, POWER_CSTATE, 1);
293 current_thread_info()->status &= ~TS_POLLING;
294 /*
295 * TS_POLLING-cleared state must be visible before we
296 * test NEED_RESCHED:
297 */
298 smp_mb();
299
300 if (!need_resched())
301 safe_halt(); /* enables interrupts racelessly */
302 else
303 local_irq_enable();
304 current_thread_info()->status |= TS_POLLING;
305 trace_power_end(&it);
306 } else {
307 local_irq_enable();
308 /* loop is done by the caller */
309 cpu_relax();
310 }
311 }
312 #ifdef CONFIG_APM_MODULE
313 EXPORT_SYMBOL(default_idle);
314 #endif
315
316 void stop_this_cpu(void *dummy)
317 {
318 local_irq_disable();
319 /*
320 * Remove this CPU:
321 */
322 set_cpu_online(smp_processor_id(), false);
323 disable_local_APIC();
324
325 for (;;) {
326 if (hlt_works(smp_processor_id()))
327 halt();
328 }
329 }
330
331 static void do_nothing(void *unused)
332 {
333 }
334
335 /*
336 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
337 * pm_idle and update to new pm_idle value. Required while changing pm_idle
338 * handler on SMP systems.
339 *
340 * Caller must have changed pm_idle to the new value before the call. Old
341 * pm_idle value will not be used by any CPU after the return of this function.
342 */
343 void cpu_idle_wait(void)
344 {
345 smp_mb();
346 /* kick all the CPUs so that they exit out of pm_idle */
347 smp_call_function(do_nothing, NULL, 1);
348 }
349 EXPORT_SYMBOL_GPL(cpu_idle_wait);
350
351 /*
352 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
353 * which can obviate IPI to trigger checking of need_resched.
354 * We execute MONITOR against need_resched and enter optimized wait state
355 * through MWAIT. Whenever someone changes need_resched, we would be woken
356 * up from MWAIT (without an IPI).
357 *
358 * New with Core Duo processors, MWAIT can take some hints based on CPU
359 * capability.
360 */
361 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
362 {
363 struct power_trace it;
364
365 trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
366 if (!need_resched()) {
367 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
368 clflush((void *)¤t_thread_info()->flags);
369
370 __monitor((void *)¤t_thread_info()->flags, 0, 0);
371 smp_mb();
372 if (!need_resched())
373 __mwait(ax, cx);
374 }
375 trace_power_end(&it);
376 }
377
378 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
379 static void mwait_idle(void)
380 {
381 struct power_trace it;
382 if (!need_resched()) {
383 trace_power_start(&it, POWER_CSTATE, 1);
384 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
385 clflush((void *)¤t_thread_info()->flags);
386
387 __monitor((void *)¤t_thread_info()->flags, 0, 0);
388 smp_mb();
389 if (!need_resched())
390 __sti_mwait(0, 0);
391 else
392 local_irq_enable();
393 trace_power_end(&it);
394 } else
395 local_irq_enable();
396 }
397
398 /*
399 * On SMP it's slightly faster (but much more power-consuming!)
400 * to poll the ->work.need_resched flag instead of waiting for the
401 * cross-CPU IPI to arrive. Use this option with caution.
402 */
403 static void poll_idle(void)
404 {
405 struct power_trace it;
406
407 trace_power_start(&it, POWER_CSTATE, 0);
408 local_irq_enable();
409 while (!need_resched())
410 cpu_relax();
411 trace_power_end(&it);
412 }
413
414 /*
415 * mwait selection logic:
416 *
417 * It depends on the CPU. For AMD CPUs that support MWAIT this is
418 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
419 * then depend on a clock divisor and current Pstate of the core. If
420 * all cores of a processor are in halt state (C1) the processor can
421 * enter the C1E (C1 enhanced) state. If mwait is used this will never
422 * happen.
423 *
424 * idle=mwait overrides this decision and forces the usage of mwait.
425 */
426 static int __cpuinitdata force_mwait;
427
428 #define MWAIT_INFO 0x05
429 #define MWAIT_ECX_EXTENDED_INFO 0x01
430 #define MWAIT_EDX_C1 0xf0
431
432 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
433 {
434 u32 eax, ebx, ecx, edx;
435
436 if (force_mwait)
437 return 1;
438
439 if (c->cpuid_level < MWAIT_INFO)
440 return 0;
441
442 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
443 /* Check, whether EDX has extended info about MWAIT */
444 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
445 return 1;
446
447 /*
448 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
449 * C1 supports MWAIT
450 */
451 return (edx & MWAIT_EDX_C1);
452 }
453
454 /*
455 * Check for AMD CPUs, which have potentially C1E support
456 */
457 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
458 {
459 if (c->x86_vendor != X86_VENDOR_AMD)
460 return 0;
461
462 if (c->x86 < 0x0F)
463 return 0;
464
465 /* Family 0x0f models < rev F do not have C1E */
466 if (c->x86 == 0x0f && c->x86_model < 0x40)
467 return 0;
468
469 return 1;
470 }
471
472 static cpumask_var_t c1e_mask;
473 static int c1e_detected;
474
475 void c1e_remove_cpu(int cpu)
476 {
477 if (c1e_mask != NULL)
478 cpumask_clear_cpu(cpu, c1e_mask);
479 }
480
481 /*
482 * C1E aware idle routine. We check for C1E active in the interrupt
483 * pending message MSR. If we detect C1E, then we handle it the same
484 * way as C3 power states (local apic timer and TSC stop)
485 */
486 static void c1e_idle(void)
487 {
488 if (need_resched())
489 return;
490
491 if (!c1e_detected) {
492 u32 lo, hi;
493
494 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
495 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
496 c1e_detected = 1;
497 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
498 mark_tsc_unstable("TSC halt in AMD C1E");
499 printk(KERN_INFO "System has AMD C1E enabled\n");
500 set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
501 }
502 }
503
504 if (c1e_detected) {
505 int cpu = smp_processor_id();
506
507 if (!cpumask_test_cpu(cpu, c1e_mask)) {
508 cpumask_set_cpu(cpu, c1e_mask);
509 /*
510 * Force broadcast so ACPI can not interfere.
511 */
512 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
513 &cpu);
514 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
515 cpu);
516 }
517 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
518
519 default_idle();
520
521 /*
522 * The switch back from broadcast mode needs to be
523 * called with interrupts disabled.
524 */
525 local_irq_disable();
526 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
527 local_irq_enable();
528 } else
529 default_idle();
530 }
531
532 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
533 {
534 #ifdef CONFIG_SMP
535 if (pm_idle == poll_idle && smp_num_siblings > 1) {
536 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
537 " performance may degrade.\n");
538 }
539 #endif
540 if (pm_idle)
541 return;
542
543 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
544 /*
545 * One CPU supports mwait => All CPUs supports mwait
546 */
547 printk(KERN_INFO "using mwait in idle threads.\n");
548 pm_idle = mwait_idle;
549 } else if (check_c1e_idle(c)) {
550 printk(KERN_INFO "using C1E aware idle routine\n");
551 pm_idle = c1e_idle;
552 } else
553 pm_idle = default_idle;
554 }
555
556 void __init init_c1e_mask(void)
557 {
558 /* If we're using c1e_idle, we need to allocate c1e_mask. */
559 if (pm_idle == c1e_idle) {
560 alloc_cpumask_var(&c1e_mask, GFP_KERNEL);
561 cpumask_clear(c1e_mask);
562 }
563 }
564
565 static int __init idle_setup(char *str)
566 {
567 if (!str)
568 return -EINVAL;
569
570 if (!strcmp(str, "poll")) {
571 printk("using polling idle threads.\n");
572 pm_idle = poll_idle;
573 } else if (!strcmp(str, "mwait"))
574 force_mwait = 1;
575 else if (!strcmp(str, "halt")) {
576 /*
577 * When the boot option of idle=halt is added, halt is
578 * forced to be used for CPU idle. In such case CPU C2/C3
579 * won't be used again.
580 * To continue to load the CPU idle driver, don't touch
581 * the boot_option_idle_override.
582 */
583 pm_idle = default_idle;
584 idle_halt = 1;
585 return 0;
586 } else if (!strcmp(str, "nomwait")) {
587 /*
588 * If the boot option of "idle=nomwait" is added,
589 * it means that mwait will be disabled for CPU C2/C3
590 * states. In such case it won't touch the variable
591 * of boot_option_idle_override.
592 */
593 idle_nomwait = 1;
594 return 0;
595 } else
596 return -1;
597
598 boot_option_idle_override = 1;
599 return 0;
600 }
601 early_param("idle", idle_setup);
602
603 unsigned long arch_align_stack(unsigned long sp)
604 {
605 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
606 sp -= get_random_int() % 8192;
607 return sp & ~0xf;
608 }
609
610 unsigned long arch_randomize_brk(struct mm_struct *mm)
611 {
612 unsigned long range_end = mm->brk + 0x02000000;
613 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
614 }
615
616
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