1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40
41 #include <asm/idle.h>
42 #include <asm/io.h>
43 #include <asm/smp.h>
44 #include <asm/desc.h>
45 #include <asm/proto.h>
46 #include <asm/mach_apic.h>
47 #include <asm/acpi.h>
48 #include <asm/dma.h>
49 #include <asm/nmi.h>
50 #include <asm/msidef.h>
51 #include <asm/hypertransport.h>
52
53 struct irq_cfg {
54 cpumask_t domain;
55 cpumask_t old_domain;
56 unsigned move_cleanup_count;
57 u8 vector;
58 u8 move_in_progress : 1;
59 };
60
61 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
62 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
63 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
64 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
65 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
66 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
67 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
68 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
69 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
70 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
71 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
72 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
73 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
74 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
75 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
76 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
77 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
78 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
79 };
80
81 static int assign_irq_vector(int irq, cpumask_t mask);
82
83 #define __apicdebuginit __init
84
85 int sis_apic_bug; /* not actually supported, dummy for compile */
86
87 static int no_timer_check;
88
89 static int disable_timer_pin_1 __initdata;
90
91 int timer_over_8254 __initdata = 1;
92
93 /* Where if anywhere is the i8259 connect in external int mode */
94 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
95
96 static DEFINE_RAW_SPINLOCK(ioapic_lock);
97 DEFINE_RAW_SPINLOCK(vector_lock);
98
99 /*
100 * # of IRQ routing registers
101 */
102 int nr_ioapic_registers[MAX_IO_APICS];
103
104 /*
105 * Rough estimation of how many shared IRQs there are, can
106 * be changed anytime.
107 */
108 #define MAX_PLUS_SHARED_IRQS NR_IRQS
109 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
110
111 /*
112 * This is performance-critical, we want to do it O(1)
113 *
114 * the indexing order of this array favors 1:1 mappings
115 * between pins and IRQs.
116 */
117
118 static struct irq_pin_list {
119 short apic, pin, next;
120 } irq_2_pin[PIN_MAP_SIZE];
121
122 struct io_apic {
123 unsigned int index;
124 unsigned int unused[3];
125 unsigned int data;
126 };
127
128 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
129 {
130 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
131 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
132 }
133
134 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
135 {
136 struct io_apic __iomem *io_apic = io_apic_base(apic);
137 writel(reg, &io_apic->index);
138 return readl(&io_apic->data);
139 }
140
141 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
142 {
143 struct io_apic __iomem *io_apic = io_apic_base(apic);
144 writel(reg, &io_apic->index);
145 writel(value, &io_apic->data);
146 }
147
148 /*
149 * Re-write a value: to be used for read-modify-write
150 * cycles where the read already set up the index register.
151 */
152 static inline void io_apic_modify(unsigned int apic, unsigned int value)
153 {
154 struct io_apic __iomem *io_apic = io_apic_base(apic);
155 writel(value, &io_apic->data);
156 }
157
158 static int io_apic_level_ack_pending(unsigned int irq)
159 {
160 struct irq_pin_list *entry;
161 unsigned long flags;
162 int pending = 0;
163
164 spin_lock_irqsave(&ioapic_lock, flags);
165 entry = irq_2_pin + irq;
166 for (;;) {
167 unsigned int reg;
168 int pin;
169
170 pin = entry->pin;
171 if (pin == -1)
172 break;
173 reg = io_apic_read(entry->apic, 0x10 + pin*2);
174 /* Is the remote IRR bit set? */
175 pending |= (reg >> 14) & 1;
176 if (!entry->next)
177 break;
178 entry = irq_2_pin + entry->next;
179 }
180 spin_unlock_irqrestore(&ioapic_lock, flags);
181 return pending;
182 }
183
184 /*
185 * Synchronize the IO-APIC and the CPU by doing
186 * a dummy read from the IO-APIC
187 */
188 static inline void io_apic_sync(unsigned int apic)
189 {
190 struct io_apic __iomem *io_apic = io_apic_base(apic);
191 readl(&io_apic->data);
192 }
193
194 #define __DO_ACTION(R, ACTION, FINAL) \
195 \
196 { \
197 int pin; \
198 struct irq_pin_list *entry = irq_2_pin + irq; \
199 \
200 BUG_ON(irq >= NR_IRQS); \
201 for (;;) { \
202 unsigned int reg; \
203 pin = entry->pin; \
204 if (pin == -1) \
205 break; \
206 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
207 reg ACTION; \
208 io_apic_modify(entry->apic, reg); \
209 FINAL; \
210 /* Force POST flush by reading: */ \
211 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
212 \
213 if (!entry->next) \
214 break; \
215 entry = irq_2_pin + entry->next; \
216 } \
217 }
218
219 union entry_union {
220 struct { u32 w1, w2; };
221 struct IO_APIC_route_entry entry;
222 };
223
224 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
225 {
226 union entry_union eu;
227 unsigned long flags;
228 spin_lock_irqsave(&ioapic_lock, flags);
229 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
230 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
231 spin_unlock_irqrestore(&ioapic_lock, flags);
232 return eu.entry;
233 }
234
235 /*
236 * When we write a new IO APIC routing entry, we need to write the high
237 * word first! If the mask bit in the low word is clear, we will enable
238 * the interrupt, and we need to make sure the entry is fully populated
239 * before that happens.
240 */
241 static void
242 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
243 {
244 union entry_union eu;
245 eu.entry = e;
246 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
247 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
248 }
249
250 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
251 {
252 unsigned long flags;
253 spin_lock_irqsave(&ioapic_lock, flags);
254 __ioapic_write_entry(apic, pin, e);
255 spin_unlock_irqrestore(&ioapic_lock, flags);
256 }
257
258 /*
259 * When we mask an IO APIC routing entry, we need to write the low
260 * word first, in order to set the mask bit before we change the
261 * high bits!
262 */
263 static void ioapic_mask_entry(int apic, int pin)
264 {
265 unsigned long flags;
266 union entry_union eu = { .entry.mask = 1 };
267
268 spin_lock_irqsave(&ioapic_lock, flags);
269 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
270 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
271 spin_unlock_irqrestore(&ioapic_lock, flags);
272 }
273
274 #ifdef CONFIG_SMP
275 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
276 {
277 int apic, pin;
278 struct irq_pin_list *entry = irq_2_pin + irq;
279
280 BUG_ON(irq >= NR_IRQS);
281 for (;;) {
282 unsigned int reg;
283 apic = entry->apic;
284 pin = entry->pin;
285 if (pin == -1)
286 break;
287 io_apic_write(apic, 0x11 + pin*2, dest);
288 reg = io_apic_read(apic, 0x10 + pin*2);
289 reg &= ~0x000000ff;
290 reg |= vector;
291 io_apic_modify(apic, reg);
292 if (!entry->next)
293 break;
294 entry = irq_2_pin + entry->next;
295 }
296 }
297
298 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
299 {
300 struct irq_cfg *cfg = irq_cfg + irq;
301 unsigned long flags;
302 unsigned int dest;
303 cpumask_t tmp;
304
305 cpus_and(tmp, mask, cpu_online_map);
306 if (cpus_empty(tmp))
307 return;
308
309 if (assign_irq_vector(irq, mask))
310 return;
311
312 cpus_and(tmp, cfg->domain, mask);
313 dest = cpu_mask_to_apicid(tmp);
314
315 /*
316 * Only the high 8 bits are valid.
317 */
318 dest = SET_APIC_LOGICAL_ID(dest);
319
320 spin_lock_irqsave(&ioapic_lock, flags);
321 __target_IO_APIC_irq(irq, dest, cfg->vector);
322 irq_desc[irq].affinity = mask;
323 spin_unlock_irqrestore(&ioapic_lock, flags);
324 }
325 #endif
326
327 /*
328 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
329 * shared ISA-space IRQs, so we have to support them. We are super
330 * fast in the common case, and fast for shared ISA-space IRQs.
331 */
332 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
333 {
334 static int first_free_entry = NR_IRQS;
335 struct irq_pin_list *entry = irq_2_pin + irq;
336
337 BUG_ON(irq >= NR_IRQS);
338 while (entry->next)
339 entry = irq_2_pin + entry->next;
340
341 if (entry->pin != -1) {
342 entry->next = first_free_entry;
343 entry = irq_2_pin + entry->next;
344 if (++first_free_entry >= PIN_MAP_SIZE)
345 panic("io_apic.c: ran out of irq_2_pin entries!");
346 }
347 entry->apic = apic;
348 entry->pin = pin;
349 }
350
351
352 #define DO_ACTION(name,R,ACTION, FINAL) \
353 \
354 static void name##_IO_APIC_irq (unsigned int irq) \
355 __DO_ACTION(R, ACTION, FINAL)
356
357 DO_ACTION( __mask, 0, |= 0x00010000, ) /* mask = 1 */
358 DO_ACTION( __unmask, 0, &= 0xfffeffff, ) /* mask = 0 */
359
360 DO_ACTION( __pcix_mask, 0, &= 0xffff7fff, ) /* edge */
361 DO_ACTION( __pcix_unmask, 0, = (reg & 0xfffeffff) | 0x00008000, ) /* level */
362
363 static void mask_IO_APIC_irq (unsigned int irq)
364 {
365 unsigned long flags;
366
367 spin_lock_irqsave(&ioapic_lock, flags);
368 __mask_IO_APIC_irq(irq);
369 spin_unlock_irqrestore(&ioapic_lock, flags);
370 }
371
372 static void unmask_IO_APIC_irq (unsigned int irq)
373 {
374 unsigned long flags;
375
376 spin_lock_irqsave(&ioapic_lock, flags);
377 __unmask_IO_APIC_irq(irq);
378 spin_unlock_irqrestore(&ioapic_lock, flags);
379 }
380 static void pcix_mask_IO_APIC_irq (unsigned int irq)
381 {
382 unsigned long flags;
383
384 spin_lock_irqsave(&ioapic_lock, flags);
385 __pcix_mask_IO_APIC_irq(irq);
386 spin_unlock_irqrestore(&ioapic_lock, flags);
387 }
388
389 static void pcix_unmask_IO_APIC_irq (unsigned int irq)
390 {
391 unsigned long flags;
392
393 spin_lock_irqsave(&ioapic_lock, flags);
394 __pcix_unmask_IO_APIC_irq(irq);
395 spin_unlock_irqrestore(&ioapic_lock, flags);
396 }
397
398 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
399 {
400 struct IO_APIC_route_entry entry;
401
402 /* Check delivery_mode to be sure we're not clearing an SMI pin */
403 entry = ioapic_read_entry(apic, pin);
404 if (entry.delivery_mode == dest_SMI)
405 return;
406 /*
407 * Disable it in the IO-APIC irq-routing table:
408 */
409 ioapic_mask_entry(apic, pin);
410 }
411
412 static void clear_IO_APIC (void)
413 {
414 int apic, pin;
415
416 for (apic = 0; apic < nr_ioapics; apic++)
417 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
418 clear_IO_APIC_pin(apic, pin);
419 }
420
421 int skip_ioapic_setup;
422 int ioapic_force;
423
424 static int __init parse_noapic(char *str)
425 {
426 disable_ioapic_setup();
427 return 0;
428 }
429 early_param("noapic", parse_noapic);
430
431 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
432 static int __init disable_timer_pin_setup(char *arg)
433 {
434 disable_timer_pin_1 = 1;
435 return 1;
436 }
437 __setup("disable_timer_pin_1", disable_timer_pin_setup);
438
439 static int __init setup_disable_8254_timer(char *s)
440 {
441 timer_over_8254 = -1;
442 return 1;
443 }
444 static int __init setup_enable_8254_timer(char *s)
445 {
446 timer_over_8254 = 2;
447 return 1;
448 }
449
450 __setup("disable_8254_timer", setup_disable_8254_timer);
451 __setup("enable_8254_timer", setup_enable_8254_timer);
452
453
454 /*
455 * Find the IRQ entry number of a certain pin.
456 */
457 static int find_irq_entry(int apic, int pin, int type)
458 {
459 int i;
460
461 for (i = 0; i < mp_irq_entries; i++)
462 if (mp_irqs[i].mpc_irqtype == type &&
463 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
464 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
465 mp_irqs[i].mpc_dstirq == pin)
466 return i;
467
468 return -1;
469 }
470
471 /*
472 * Find the pin to which IRQ[irq] (ISA) is connected
473 */
474 static int __init find_isa_irq_pin(int irq, int type)
475 {
476 int i;
477
478 for (i = 0; i < mp_irq_entries; i++) {
479 int lbus = mp_irqs[i].mpc_srcbus;
480
481 if (test_bit(lbus, mp_bus_not_pci) &&
482 (mp_irqs[i].mpc_irqtype == type) &&
483 (mp_irqs[i].mpc_srcbusirq == irq))
484
485 return mp_irqs[i].mpc_dstirq;
486 }
487 return -1;
488 }
489
490 static int __init find_isa_irq_apic(int irq, int type)
491 {
492 int i;
493
494 for (i = 0; i < mp_irq_entries; i++) {
495 int lbus = mp_irqs[i].mpc_srcbus;
496
497 if (test_bit(lbus, mp_bus_not_pci) &&
498 (mp_irqs[i].mpc_irqtype == type) &&
499 (mp_irqs[i].mpc_srcbusirq == irq))
500 break;
501 }
502 if (i < mp_irq_entries) {
503 int apic;
504 for(apic = 0; apic < nr_ioapics; apic++) {
505 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
506 return apic;
507 }
508 }
509
510 return -1;
511 }
512
513 /*
514 * Find a specific PCI IRQ entry.
515 * Not an __init, possibly needed by modules
516 */
517 static int pin_2_irq(int idx, int apic, int pin);
518
519 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
520 {
521 int apic, i, best_guess = -1;
522
523 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
524 bus, slot, pin);
525 if (mp_bus_id_to_pci_bus[bus] == -1) {
526 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
527 return -1;
528 }
529 for (i = 0; i < mp_irq_entries; i++) {
530 int lbus = mp_irqs[i].mpc_srcbus;
531
532 for (apic = 0; apic < nr_ioapics; apic++)
533 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
534 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
535 break;
536
537 if (!test_bit(lbus, mp_bus_not_pci) &&
538 !mp_irqs[i].mpc_irqtype &&
539 (bus == lbus) &&
540 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
541 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
542
543 if (!(apic || IO_APIC_IRQ(irq)))
544 continue;
545
546 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
547 return irq;
548 /*
549 * Use the first all-but-pin matching entry as a
550 * best-guess fuzzy result for broken mptables.
551 */
552 if (best_guess < 0)
553 best_guess = irq;
554 }
555 }
556 BUG_ON(best_guess >= NR_IRQS);
557 return best_guess;
558 }
559
560 /* ISA interrupts are always polarity zero edge triggered,
561 * when listed as conforming in the MP table. */
562
563 #define default_ISA_trigger(idx) (0)
564 #define default_ISA_polarity(idx) (0)
565
566 /* PCI interrupts are always polarity one level triggered,
567 * when listed as conforming in the MP table. */
568
569 #define default_PCI_trigger(idx) (1)
570 #define default_PCI_polarity(idx) (1)
571
572 static int MPBIOS_polarity(int idx)
573 {
574 int bus = mp_irqs[idx].mpc_srcbus;
575 int polarity;
576
577 /*
578 * Determine IRQ line polarity (high active or low active):
579 */
580 switch (mp_irqs[idx].mpc_irqflag & 3)
581 {
582 case 0: /* conforms, ie. bus-type dependent polarity */
583 if (test_bit(bus, mp_bus_not_pci))
584 polarity = default_ISA_polarity(idx);
585 else
586 polarity = default_PCI_polarity(idx);
587 break;
588 case 1: /* high active */
589 {
590 polarity = 0;
591 break;
592 }
593 case 2: /* reserved */
594 {
595 printk(KERN_WARNING "broken BIOS!!\n");
596 polarity = 1;
597 break;
598 }
599 case 3: /* low active */
600 {
601 polarity = 1;
602 break;
603 }
604 default: /* invalid */
605 {
606 printk(KERN_WARNING "broken BIOS!!\n");
607 polarity = 1;
608 break;
609 }
610 }
611 return polarity;
612 }
613
614 static int MPBIOS_trigger(int idx)
615 {
616 int bus = mp_irqs[idx].mpc_srcbus;
617 int trigger;
618
619 /*
620 * Determine IRQ trigger mode (edge or level sensitive):
621 */
622 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
623 {
624 case 0: /* conforms, ie. bus-type dependent */
625 if (test_bit(bus, mp_bus_not_pci))
626 trigger = default_ISA_trigger(idx);
627 else
628 trigger = default_PCI_trigger(idx);
629 break;
630 case 1: /* edge */
631 {
632 trigger = 0;
633 break;
634 }
635 case 2: /* reserved */
636 {
637 printk(KERN_WARNING "broken BIOS!!\n");
638 trigger = 1;
639 break;
640 }
641 case 3: /* level */
642 {
643 trigger = 1;
644 break;
645 }
646 default: /* invalid */
647 {
648 printk(KERN_WARNING "broken BIOS!!\n");
649 trigger = 0;
650 break;
651 }
652 }
653 return trigger;
654 }
655
656 static inline int irq_polarity(int idx)
657 {
658 return MPBIOS_polarity(idx);
659 }
660
661 static inline int irq_trigger(int idx)
662 {
663 return MPBIOS_trigger(idx);
664 }
665
666 static int pin_2_irq(int idx, int apic, int pin)
667 {
668 int irq, i;
669 int bus = mp_irqs[idx].mpc_srcbus;
670
671 /*
672 * Debugging check, we are in big trouble if this message pops up!
673 */
674 if (mp_irqs[idx].mpc_dstirq != pin)
675 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
676
677 if (test_bit(bus, mp_bus_not_pci)) {
678 irq = mp_irqs[idx].mpc_srcbusirq;
679 } else {
680 /*
681 * PCI IRQs are mapped in order
682 */
683 i = irq = 0;
684 while (i < apic)
685 irq += nr_ioapic_registers[i++];
686 irq += pin;
687 }
688 BUG_ON(irq >= NR_IRQS);
689 return irq;
690 }
691
692 static int __assign_irq_vector(int irq, cpumask_t mask)
693 {
694 /*
695 * NOTE! The local APIC isn't very good at handling
696 * multiple interrupts at the same interrupt level.
697 * As the interrupt level is determined by taking the
698 * vector number and shifting that right by 4, we
699 * want to spread these out a bit so that they don't
700 * all fall in the same interrupt level.
701 *
702 * Also, we've got to be careful not to trash gate
703 * 0x80, because int 0x80 is hm, kind of importantish. ;)
704 */
705 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
706 unsigned int old_vector;
707 int cpu;
708 struct irq_cfg *cfg;
709
710 BUG_ON((unsigned)irq >= NR_IRQS);
711 cfg = &irq_cfg[irq];
712
713 /* Only try and allocate irqs on cpus that are present */
714 cpus_and(mask, mask, cpu_online_map);
715
716 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
717 return -EBUSY;
718
719 old_vector = cfg->vector;
720 if (old_vector) {
721 cpumask_t tmp;
722 cpus_and(tmp, cfg->domain, mask);
723 if (!cpus_empty(tmp))
724 return 0;
725 }
726
727 for_each_cpu_mask(cpu, mask) {
728 cpumask_t domain, new_mask;
729 int new_cpu;
730 int vector, offset;
731
732 domain = vector_allocation_domain(cpu);
733 cpus_and(new_mask, domain, cpu_online_map);
734
735 vector = current_vector;
736 offset = current_offset;
737 next:
738 vector += 8;
739 if (vector >= FIRST_SYSTEM_VECTOR) {
740 /* If we run out of vectors on large boxen, must share them. */
741 offset = (offset + 1) % 8;
742 vector = FIRST_DEVICE_VECTOR + offset;
743 }
744 if (unlikely(current_vector == vector))
745 continue;
746 if (vector == IA32_SYSCALL_VECTOR)
747 goto next;
748 for_each_cpu_mask(new_cpu, new_mask)
749 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
750 goto next;
751 /* Found one! */
752 current_vector = vector;
753 current_offset = offset;
754 if (old_vector) {
755 cfg->move_in_progress = 1;
756 cfg->old_domain = cfg->domain;
757 }
758 for_each_cpu_mask(new_cpu, new_mask)
759 per_cpu(vector_irq, new_cpu)[vector] = irq;
760 cfg->vector = vector;
761 cfg->domain = domain;
762 return 0;
763 }
764 return -ENOSPC;
765 }
766
767 static int assign_irq_vector(int irq, cpumask_t mask)
768 {
769 int err;
770 unsigned long flags;
771
772 spin_lock_irqsave(&vector_lock, flags);
773 err = __assign_irq_vector(irq, mask);
774 spin_unlock_irqrestore(&vector_lock, flags);
775 return err;
776 }
777
778 static void __clear_irq_vector(int irq)
779 {
780 struct irq_cfg *cfg;
781 cpumask_t mask;
782 int cpu, vector;
783
784 BUG_ON((unsigned)irq >= NR_IRQS);
785 cfg = &irq_cfg[irq];
786 BUG_ON(!cfg->vector);
787
788 vector = cfg->vector;
789 cpus_and(mask, cfg->domain, cpu_online_map);
790 for_each_cpu_mask(cpu, mask)
791 per_cpu(vector_irq, cpu)[vector] = -1;
792
793 cfg->vector = 0;
794 cfg->domain = CPU_MASK_NONE;
795 }
796
797 void __setup_vector_irq(int cpu)
798 {
799 /* Initialize vector_irq on a new cpu */
800 /* This function must be called with vector_lock held */
801 int irq, vector;
802
803 /* Mark the inuse vectors */
804 for (irq = 0; irq < NR_IRQS; ++irq) {
805 if (!cpu_isset(cpu, irq_cfg[irq].domain))
806 continue;
807 vector = irq_cfg[irq].vector;
808 per_cpu(vector_irq, cpu)[vector] = irq;
809 }
810 /* Mark the free vectors */
811 for (vector = 0; vector < NR_VECTORS; ++vector) {
812 irq = per_cpu(vector_irq, cpu)[vector];
813 if (irq < 0)
814 continue;
815 if (!cpu_isset(cpu, irq_cfg[irq].domain))
816 per_cpu(vector_irq, cpu)[vector] = -1;
817 }
818 }
819
820
821 static struct irq_chip ioapic_chip;
822 static struct irq_chip pcix_ioapic_chip;
823
824 static void ioapic_register_intr(int irq, unsigned long trigger, int pcix)
825 {
826 struct irq_chip *chip = pcix ? &pcix_ioapic_chip : &ioapic_chip;
827
828 if (trigger) {
829 irq_desc[irq].status |= IRQ_LEVEL;
830 set_irq_chip_and_handler_name(irq, chip, handle_fasteoi_irq,
831 pcix ? "pcix-fasteoi" : "fasteoi");
832 } else {
833 irq_desc[irq].status &= ~IRQ_LEVEL;
834 set_irq_chip_and_handler_name(irq, chip, handle_edge_irq,
835 pcix ? "pcix-edge" : "edge");
836 }
837 }
838
839 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
840 int trigger, int polarity)
841 {
842 struct irq_cfg *cfg = irq_cfg + irq;
843 struct IO_APIC_route_entry entry;
844 cpumask_t mask;
845
846 if (!IO_APIC_IRQ(irq))
847 return;
848
849 mask = TARGET_CPUS;
850 if (assign_irq_vector(irq, mask))
851 return;
852
853 cpus_and(mask, cfg->domain, mask);
854
855 apic_printk(APIC_VERBOSE,KERN_DEBUG
856 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
857 "IRQ %d Mode:%i Active:%i)\n",
858 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
859 irq, trigger, polarity);
860
861 /*
862 * add it to the IO-APIC irq-routing table:
863 */
864 memset(&entry,0,sizeof(entry));
865
866 entry.delivery_mode = INT_DELIVERY_MODE;
867 entry.dest_mode = INT_DEST_MODE;
868 entry.dest = cpu_mask_to_apicid(mask);
869 entry.mask = 0; /* enable IRQ */
870 entry.trigger = trigger;
871 entry.polarity = polarity;
872 entry.vector = cfg->vector;
873
874 /* Mask level triggered irqs.
875 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
876 */
877 if (trigger)
878 entry.mask = 1;
879
880 ioapic_register_intr(irq, trigger, apic > 0);
881 if (irq < 16)
882 disable_8259A_irq(irq);
883
884 ioapic_write_entry(apic, pin, entry);
885 }
886
887 static void __init setup_IO_APIC_irqs(void)
888 {
889 int apic, pin, idx, irq, first_notcon = 1;
890
891 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
892
893 for (apic = 0; apic < nr_ioapics; apic++) {
894 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
895
896 idx = find_irq_entry(apic,pin,mp_INT);
897 if (idx == -1) {
898 if (first_notcon) {
899 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
900 first_notcon = 0;
901 } else
902 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
903 continue;
904 }
905 if (!first_notcon) {
906 apic_printk(APIC_VERBOSE, " not connected.\n");
907 first_notcon = 1;
908 }
909
910 irq = pin_2_irq(idx, apic, pin);
911 add_pin_to_irq(irq, apic, pin);
912
913 setup_IO_APIC_irq(apic, pin, irq,
914 irq_trigger(idx), irq_polarity(idx));
915 }
916 }
917
918 if (!first_notcon)
919 apic_printk(APIC_VERBOSE, " not connected.\n");
920 }
921
922 /*
923 * Set up the 8259A-master output pin as broadcast to all
924 * CPUs.
925 */
926 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
927 {
928 struct IO_APIC_route_entry entry;
929 unsigned long flags;
930
931 memset(&entry,0,sizeof(entry));
932
933 disable_8259A_irq(0);
934
935 /* mask LVT0 */
936 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
937
938 /*
939 * We use logical delivery to get the timer IRQ
940 * to the first CPU.
941 */
942 entry.dest_mode = INT_DEST_MODE;
943 entry.mask = 0; /* unmask IRQ now */
944 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
945 entry.delivery_mode = INT_DELIVERY_MODE;
946 entry.polarity = 0;
947 entry.trigger = 0;
948 entry.vector = vector;
949
950 /*
951 * The timer IRQ doesn't have to know that behind the
952 * scene we have a 8259A-master in AEOI mode ...
953 */
954 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
955
956 /*
957 * Add it to the IO-APIC irq-routing table:
958 */
959 spin_lock_irqsave(&ioapic_lock, flags);
960 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
961 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
962 spin_unlock_irqrestore(&ioapic_lock, flags);
963
964 enable_8259A_irq(0);
965 }
966
967 void __apicdebuginit print_IO_APIC(void)
968 {
969 int apic, i;
970 union IO_APIC_reg_00 reg_00;
971 union IO_APIC_reg_01 reg_01;
972 union IO_APIC_reg_02 reg_02;
973 unsigned long flags;
974
975 if (apic_verbosity == APIC_QUIET)
976 return;
977
978 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
979 for (i = 0; i < nr_ioapics; i++)
980 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
981 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
982
983 /*
984 * We are a bit conservative about what we expect. We have to
985 * know about every hardware change ASAP.
986 */
987 printk(KERN_INFO "testing the IO APIC.......................\n");
988
989 for (apic = 0; apic < nr_ioapics; apic++) {
990
991 spin_lock_irqsave(&ioapic_lock, flags);
992 reg_00.raw = io_apic_read(apic, 0);
993 reg_01.raw = io_apic_read(apic, 1);
994 if (reg_01.bits.version >= 0x10)
995 reg_02.raw = io_apic_read(apic, 2);
996 spin_unlock_irqrestore(&ioapic_lock, flags);
997
998 printk("\n");
999 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1000 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1001 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1002
1003 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1004 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1005
1006 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1007 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1008
1009 if (reg_01.bits.version >= 0x10) {
1010 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1011 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1012 }
1013
1014 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1015
1016 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1017 " Stat Dmod Deli Vect: \n");
1018
1019 for (i = 0; i <= reg_01.bits.entries; i++) {
1020 struct IO_APIC_route_entry entry;
1021
1022 entry = ioapic_read_entry(apic, i);
1023
1024 printk(KERN_DEBUG " %02x %03X ",
1025 i,
1026 entry.dest
1027 );
1028
1029 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1030 entry.mask,
1031 entry.trigger,
1032 entry.irr,
1033 entry.polarity,
1034 entry.delivery_status,
1035 entry.dest_mode,
1036 entry.delivery_mode,
1037 entry.vector
1038 );
1039 }
1040 }
1041 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1042 for (i = 0; i < NR_IRQS; i++) {
1043 struct irq_pin_list *entry = irq_2_pin + i;
1044 if (entry->pin < 0)
1045 continue;
1046 printk(KERN_DEBUG "IRQ%d ", i);
1047 for (;;) {
1048 printk("-> %d:%d", entry->apic, entry->pin);
1049 if (!entry->next)
1050 break;
1051 entry = irq_2_pin + entry->next;
1052 }
1053 printk("\n");
1054 }
1055
1056 printk(KERN_INFO ".................................... done.\n");
1057
1058 return;
1059 }
1060
1061 #if 0
1062
1063 static __apicdebuginit void print_APIC_bitfield (int base)
1064 {
1065 unsigned int v;
1066 int i, j;
1067
1068 if (apic_verbosity == APIC_QUIET)
1069 return;
1070
1071 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1072 for (i = 0; i < 8; i++) {
1073 v = apic_read(base + i*0x10);
1074 for (j = 0; j < 32; j++) {
1075 if (v & (1<<j))
1076 printk("1");
1077 else
1078 printk("");
1079 }
1080 printk("\n");
1081 }
1082 }
1083
1084 void __apicdebuginit print_local_APIC(void * dummy)
1085 {
1086 unsigned int v, ver, maxlvt;
1087
1088 if (apic_verbosity == APIC_QUIET)
1089 return;
1090
1091 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1092 smp_processor_id(), hard_smp_processor_id());
1093 v = apic_read(APIC_ID);
1094 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1095 v = apic_read(APIC_LVR);
1096 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1097 ver = GET_APIC_VERSION(v);
1098 maxlvt = lapic_get_maxlvt();
1099
1100 v = apic_read(APIC_TASKPRI);
1101 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1102
1103 v = apic_read(APIC_ARBPRI);
1104 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1105 v & APIC_ARBPRI_MASK);
1106 v = apic_read(APIC_PROCPRI);
1107 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1108
1109 v = apic_read(APIC_EOI);
1110 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1111 v = apic_read(APIC_RRR);
1112 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1113 v = apic_read(APIC_LDR);
1114 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1115 v = apic_read(APIC_DFR);
1116 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1117 v = apic_read(APIC_SPIV);
1118 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1119
1120 printk(KERN_DEBUG "... APIC ISR field:\n");
1121 print_APIC_bitfield(APIC_ISR);
1122 printk(KERN_DEBUG "... APIC TMR field:\n");
1123 print_APIC_bitfield(APIC_TMR);
1124 printk(KERN_DEBUG "... APIC IRR field:\n");
1125 print_APIC_bitfield(APIC_IRR);
1126
1127 v = apic_read(APIC_ESR);
1128 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1129
1130 v = apic_read(APIC_ICR);
1131 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1132 v = apic_read(APIC_ICR2);
1133 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1134
1135 v = apic_read(APIC_LVTT);
1136 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1137
1138 if (maxlvt > 3) { /* PC is LVT#4. */
1139 v = apic_read(APIC_LVTPC);
1140 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1141 }
1142 v = apic_read(APIC_LVT0);
1143 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1144 v = apic_read(APIC_LVT1);
1145 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1146
1147 if (maxlvt > 2) { /* ERR is LVT#3. */
1148 v = apic_read(APIC_LVTERR);
1149 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1150 }
1151
1152 v = apic_read(APIC_TMICT);
1153 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1154 v = apic_read(APIC_TMCCT);
1155 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1156 v = apic_read(APIC_TDCR);
1157 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1158 printk("\n");
1159 }
1160
1161 void print_all_local_APICs (void)
1162 {
1163 on_each_cpu(print_local_APIC, NULL, 1, 1);
1164 }
1165
1166 void __apicdebuginit print_PIC(void)
1167 {
1168 unsigned int v;
1169 unsigned long flags;
1170
1171 if (apic_verbosity == APIC_QUIET)
1172 return;
1173
1174 printk(KERN_DEBUG "\nprinting PIC contents\n");
1175
1176 spin_lock_irqsave(&i8259A_lock, flags);
1177
1178 v = inb(0xa1) << 8 | inb(0x21);
1179 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1180
1181 v = inb(0xa0) << 8 | inb(0x20);
1182 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1183
1184 outb(0x0b,0xa0);
1185 outb(0x0b,0x20);
1186 v = inb(0xa0) << 8 | inb(0x20);
1187 outb(0x0a,0xa0);
1188 outb(0x0a,0x20);
1189
1190 spin_unlock_irqrestore(&i8259A_lock, flags);
1191
1192 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1193
1194 v = inb(0x4d1) << 8 | inb(0x4d0);
1195 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1196 }
1197
1198 #endif /* 0 */
1199
1200 void __init enable_IO_APIC(void)
1201 {
1202 union IO_APIC_reg_01 reg_01;
1203 int i8259_apic, i8259_pin;
1204 int i, apic;
1205 unsigned long flags;
1206
1207 for (i = 0; i < PIN_MAP_SIZE; i++) {
1208 irq_2_pin[i].pin = -1;
1209 irq_2_pin[i].next = 0;
1210 }
1211
1212 /*
1213 * The number of IO-APIC IRQ registers (== #pins):
1214 */
1215 for (apic = 0; apic < nr_ioapics; apic++) {
1216 spin_lock_irqsave(&ioapic_lock, flags);
1217 reg_01.raw = io_apic_read(apic, 1);
1218 spin_unlock_irqrestore(&ioapic_lock, flags);
1219 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1220 }
1221 for(apic = 0; apic < nr_ioapics; apic++) {
1222 int pin;
1223 /* See if any of the pins is in ExtINT mode */
1224 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1225 struct IO_APIC_route_entry entry;
1226 entry = ioapic_read_entry(apic, pin);
1227
1228 /* If the interrupt line is enabled and in ExtInt mode
1229 * I have found the pin where the i8259 is connected.
1230 */
1231 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1232 ioapic_i8259.apic = apic;
1233 ioapic_i8259.pin = pin;
1234 goto found_i8259;
1235 }
1236 }
1237 }
1238 found_i8259:
1239 /* Look to see what if the MP table has reported the ExtINT */
1240 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1241 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1242 /* Trust the MP table if nothing is setup in the hardware */
1243 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1244 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1245 ioapic_i8259.pin = i8259_pin;
1246 ioapic_i8259.apic = i8259_apic;
1247 }
1248 /* Complain if the MP table and the hardware disagree */
1249 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1250 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1251 {
1252 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1253 }
1254
1255 /*
1256 * Do not trust the IO-APIC being empty at bootup
1257 */
1258 clear_IO_APIC();
1259 }
1260
1261 /*
1262 * Not an __init, needed by the reboot code
1263 */
1264 void disable_IO_APIC(void)
1265 {
1266 /*
1267 * Clear the IO-APIC before rebooting:
1268 */
1269 clear_IO_APIC();
1270
1271 /*
1272 * If the i8259 is routed through an IOAPIC
1273 * Put that IOAPIC in virtual wire mode
1274 * so legacy interrupts can be delivered.
1275 */
1276 if (ioapic_i8259.pin != -1) {
1277 struct IO_APIC_route_entry entry;
1278
1279 memset(&entry, 0, sizeof(entry));
1280 entry.mask = 0; /* Enabled */
1281 entry.trigger = 0; /* Edge */
1282 entry.irr = 0;
1283 entry.polarity = 0; /* High */
1284 entry.delivery_status = 0;
1285 entry.dest_mode = 0; /* Physical */
1286 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1287 entry.vector = 0;
1288 entry.dest = GET_APIC_ID(apic_read(APIC_ID));
1289
1290 /*
1291 * Add it to the IO-APIC irq-routing table:
1292 */
1293 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1294 }
1295
1296 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1297 }
1298
1299 /*
1300 * There is a nasty bug in some older SMP boards, their mptable lies
1301 * about the timer IRQ. We do the following to work around the situation:
1302 *
1303 * - timer IRQ defaults to IO-APIC IRQ
1304 * - if this function detects that timer IRQs are defunct, then we fall
1305 * back to ISA timer IRQs
1306 */
1307 static int __init timer_irq_works(void)
1308 {
1309 unsigned long t1 = jiffies;
1310 unsigned long flags;
1311
1312 local_save_flags(flags);
1313 local_irq_enable();
1314 /* Let ten ticks pass... */
1315 mdelay((10 * 1000) / HZ);
1316 local_irq_restore(flags);
1317
1318 /*
1319 * Expect a few ticks at least, to be sure some possible
1320 * glue logic does not lock up after one or two first
1321 * ticks in a non-ExtINT mode. Also the local APIC
1322 * might have cached one ExtINT interrupt. Finally, at
1323 * least one tick may be lost due to delays.
1324 */
1325
1326 /* jiffies wrap? */
1327 if (time_after(jiffies, t1 + 4))
1328 return 1;
1329 return 0;
1330 }
1331
1332 /*
1333 * In the SMP+IOAPIC case it might happen that there are an unspecified
1334 * number of pending IRQ events unhandled. These cases are very rare,
1335 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1336 * better to do it this way as thus we do not have to be aware of
1337 * 'pending' interrupts in the IRQ path, except at this point.
1338 */
1339 /*
1340 * Edge triggered needs to resend any interrupt
1341 * that was delayed but this is now handled in the device
1342 * independent code.
1343 */
1344
1345 /*
1346 * Starting up a edge-triggered IO-APIC interrupt is
1347 * nasty - we need to make sure that we get the edge.
1348 * If it is already asserted for some reason, we need
1349 * return 1 to indicate that is was pending.
1350 *
1351 * This is not complete - we should be able to fake
1352 * an edge even if it isn't on the 8259A...
1353 */
1354
1355 static unsigned int startup_ioapic_irq(unsigned int irq)
1356 {
1357 int was_pending = 0;
1358 unsigned long flags;
1359
1360 spin_lock_irqsave(&ioapic_lock, flags);
1361 if (irq < 16) {
1362 disable_8259A_irq(irq);
1363 if (i8259A_irq_pending(irq))
1364 was_pending = 1;
1365 }
1366 __unmask_IO_APIC_irq(irq);
1367 spin_unlock_irqrestore(&ioapic_lock, flags);
1368
1369 return was_pending;
1370 }
1371
1372 static int ioapic_retrigger_irq(unsigned int irq)
1373 {
1374 struct irq_cfg *cfg = &irq_cfg[irq];
1375 cpumask_t mask;
1376 unsigned long flags;
1377
1378 spin_lock_irqsave(&vector_lock, flags);
1379 cpus_clear(mask);
1380 cpu_set(first_cpu(cfg->domain), mask);
1381
1382 send_IPI_mask(mask, cfg->vector);
1383 spin_unlock_irqrestore(&vector_lock, flags);
1384
1385 return 1;
1386 }
1387
1388 /*
1389 * Level and edge triggered IO-APIC interrupts need different handling,
1390 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1391 * handled with the level-triggered descriptor, but that one has slightly
1392 * more overhead. Level-triggered interrupts cannot be handled with the
1393 * edge-triggered handler, without risking IRQ storms and other ugly
1394 * races.
1395 */
1396
1397 #ifdef CONFIG_SMP
1398 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1399 {
1400 unsigned vector, me;
1401 ack_APIC_irq();
1402 exit_idle();
1403 irq_enter();
1404
1405 me = smp_processor_id();
1406 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1407 unsigned int irq;
1408 struct irq_desc *desc;
1409 struct irq_cfg *cfg;
1410 irq = __get_cpu_var(vector_irq)[vector];
1411 if (irq >= NR_IRQS)
1412 continue;
1413
1414 desc = irq_desc + irq;
1415 cfg = irq_cfg + irq;
1416 spin_lock(&desc->lock);
1417 if (!cfg->move_cleanup_count)
1418 goto unlock;
1419
1420 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1421 goto unlock;
1422
1423 __get_cpu_var(vector_irq)[vector] = -1;
1424 cfg->move_cleanup_count--;
1425 unlock:
1426 spin_unlock(&desc->lock);
1427 }
1428
1429 irq_exit();
1430 }
1431
1432 static void irq_complete_move(unsigned int irq)
1433 {
1434 struct irq_cfg *cfg = irq_cfg + irq;
1435 unsigned vector, me;
1436
1437 if (likely(!cfg->move_in_progress))
1438 return;
1439
1440 vector = ~get_irq_regs()->orig_ax;
1441 me = smp_processor_id();
1442 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1443 cpumask_t cleanup_mask;
1444
1445 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1446 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1447 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1448 cfg->move_in_progress = 0;
1449 }
1450 }
1451 #else
1452 static inline void irq_complete_move(unsigned int irq) {}
1453 #endif
1454
1455 static void ack_apic_edge(unsigned int irq)
1456 {
1457 irq_complete_move(irq);
1458 move_native_irq(irq);
1459 ack_APIC_irq();
1460 }
1461
1462 static void ack_apic_level(unsigned int irq)
1463 {
1464 int do_unmask_irq = 0;
1465
1466 irq_complete_move(irq);
1467 #ifdef CONFIG_GENERIC_PENDING_IRQ
1468 /* If we are moving the irq we need to mask it */
1469 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING) &&
1470 !(irq_desc[irq].status & IRQ_INPROGRESS)) {
1471 do_unmask_irq = 1;
1472 mask_IO_APIC_irq(irq);
1473 }
1474 #endif
1475
1476 /*
1477 * We must acknowledge the irq before we move it or the acknowledge will
1478 * not propagate properly.
1479 */
1480 ack_APIC_irq();
1481
1482 /* Now we can move and renable the irq */
1483 if (unlikely(do_unmask_irq)) {
1484 /* Only migrate the irq if the ack has been received.
1485 *
1486 * On rare occasions the broadcast level triggered ack gets
1487 * delayed going to ioapics, and if we reprogram the
1488 * vector while Remote IRR is still set the irq will never
1489 * fire again.
1490 *
1491 * To prevent this scenario we read the Remote IRR bit
1492 * of the ioapic. This has two effects.
1493 * - On any sane system the read of the ioapic will
1494 * flush writes (and acks) going to the ioapic from
1495 * this cpu.
1496 * - We get to see if the ACK has actually been delivered.
1497 *
1498 * Based on failed experiments of reprogramming the
1499 * ioapic entry from outside of irq context starting
1500 * with masking the ioapic entry and then polling until
1501 * Remote IRR was clear before reprogramming the
1502 * ioapic I don't trust the Remote IRR bit to be
1503 * completey accurate.
1504 *
1505 * However there appears to be no other way to plug
1506 * this race, so if the Remote IRR bit is not
1507 * accurate and is causing problems then it is a hardware bug
1508 * and you can go talk to the chipset vendor about it.
1509 */
1510 if (!io_apic_level_ack_pending(irq))
1511 move_masked_irq(irq);
1512 unmask_IO_APIC_irq(irq);
1513 }
1514 #if (defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)) && \
1515 defined(CONFIG_PREEMPT_HARDIRQS)
1516 /*
1517 * With threaded interrupts, we always have IRQ_INPROGRESS
1518 * when acking.
1519 */
1520 else if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING))
1521 move_masked_irq(irq);
1522 #endif
1523 }
1524
1525 static struct irq_chip ioapic_chip __read_mostly = {
1526 .name = "IO-APIC",
1527 .startup = startup_ioapic_irq,
1528 .mask = mask_IO_APIC_irq,
1529 .unmask = unmask_IO_APIC_irq,
1530 .ack = ack_apic_edge,
1531 .eoi = ack_apic_level,
1532 #ifdef CONFIG_SMP
1533 .set_affinity = set_ioapic_affinity_irq,
1534 #endif
1535 .retrigger = ioapic_retrigger_irq,
1536 };
1537
1538 static struct irq_chip pcix_ioapic_chip __read_mostly = {
1539 .name = "IO-APIC",
1540 .startup = startup_ioapic_irq,
1541 .mask = pcix_mask_IO_APIC_irq,
1542 .unmask = pcix_unmask_IO_APIC_irq,
1543 .ack = ack_apic_edge,
1544 .eoi = ack_apic_level,
1545 #ifdef CONFIG_SMP
1546 .set_affinity = set_ioapic_affinity_irq,
1547 #endif
1548 .retrigger = ioapic_retrigger_irq,
1549 };
1550
1551 static inline void init_IO_APIC_traps(void)
1552 {
1553 int irq;
1554
1555 /*
1556 * NOTE! The local APIC isn't very good at handling
1557 * multiple interrupts at the same interrupt level.
1558 * As the interrupt level is determined by taking the
1559 * vector number and shifting that right by 4, we
1560 * want to spread these out a bit so that they don't
1561 * all fall in the same interrupt level.
1562 *
1563 * Also, we've got to be careful not to trash gate
1564 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1565 */
1566 for (irq = 0; irq < NR_IRQS ; irq++) {
1567 int tmp = irq;
1568 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1569 /*
1570 * Hmm.. We don't have an entry for this,
1571 * so default to an old-fashioned 8259
1572 * interrupt if we can..
1573 */
1574 if (irq < 16)
1575 make_8259A_irq(irq);
1576 else
1577 /* Strange. Oh, well.. */
1578 irq_desc[irq].chip = &no_irq_chip;
1579 }
1580 }
1581 }
1582
1583 static void enable_lapic_irq (unsigned int irq)
1584 {
1585 unsigned long v;
1586
1587 v = apic_read(APIC_LVT0);
1588 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1589 }
1590
1591 static void disable_lapic_irq (unsigned int irq)
1592 {
1593 unsigned long v;
1594
1595 v = apic_read(APIC_LVT0);
1596 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1597 }
1598
1599 static void ack_lapic_irq (unsigned int irq)
1600 {
1601 ack_APIC_irq();
1602 }
1603
1604 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1605
1606 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1607 .name = "local-APIC",
1608 .typename = "local-APIC-edge",
1609 .startup = NULL, /* startup_irq() not used for IRQ0 */
1610 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1611 .enable = enable_lapic_irq,
1612 .disable = disable_lapic_irq,
1613 .ack = ack_lapic_irq,
1614 .end = end_lapic_irq,
1615 };
1616
1617 static void __init setup_nmi(void)
1618 {
1619 /*
1620 * Dirty trick to enable the NMI watchdog ...
1621 * We put the 8259A master into AEOI mode and
1622 * unmask on all local APICs LVT0 as NMI.
1623 *
1624 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1625 * is from Maciej W. Rozycki - so we do not have to EOI from
1626 * the NMI handler or the timer interrupt.
1627 */
1628 printk(KERN_INFO "activating NMI Watchdog ...");
1629
1630 enable_NMI_through_LVT0();
1631
1632 printk(" done.\n");
1633 }
1634
1635 /*
1636 * This looks a bit hackish but it's about the only one way of sending
1637 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1638 * not support the ExtINT mode, unfortunately. We need to send these
1639 * cycles as some i82489DX-based boards have glue logic that keeps the
1640 * 8259A interrupt line asserted until INTA. --macro
1641 */
1642 static inline void unlock_ExtINT_logic(void)
1643 {
1644 int apic, pin, i;
1645 struct IO_APIC_route_entry entry0, entry1;
1646 unsigned char save_control, save_freq_select;
1647 unsigned long flags;
1648
1649 pin = find_isa_irq_pin(8, mp_INT);
1650 apic = find_isa_irq_apic(8, mp_INT);
1651 if (pin == -1)
1652 return;
1653
1654 spin_lock_irqsave(&ioapic_lock, flags);
1655 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1656 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1657 spin_unlock_irqrestore(&ioapic_lock, flags);
1658 clear_IO_APIC_pin(apic, pin);
1659
1660 memset(&entry1, 0, sizeof(entry1));
1661
1662 entry1.dest_mode = 0; /* physical delivery */
1663 entry1.mask = 0; /* unmask IRQ now */
1664 entry1.dest = hard_smp_processor_id();
1665 entry1.delivery_mode = dest_ExtINT;
1666 entry1.polarity = entry0.polarity;
1667 entry1.trigger = 0;
1668 entry1.vector = 0;
1669
1670 spin_lock_irqsave(&ioapic_lock, flags);
1671 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1672 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1673 spin_unlock_irqrestore(&ioapic_lock, flags);
1674
1675 save_control = CMOS_READ(RTC_CONTROL);
1676 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1677 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1678 RTC_FREQ_SELECT);
1679 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1680
1681 i = 100;
1682 while (i-- > 0) {
1683 mdelay(10);
1684 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1685 i -= 10;
1686 }
1687
1688 CMOS_WRITE(save_control, RTC_CONTROL);
1689 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1690 clear_IO_APIC_pin(apic, pin);
1691
1692 spin_lock_irqsave(&ioapic_lock, flags);
1693 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1694 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1695 spin_unlock_irqrestore(&ioapic_lock, flags);
1696 }
1697
1698 /*
1699 * This code may look a bit paranoid, but it's supposed to cooperate with
1700 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1701 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1702 * fanatically on his truly buggy board.
1703 *
1704 * FIXME: really need to revamp this for modern platforms only.
1705 */
1706 static inline void __init check_timer(void)
1707 {
1708 struct irq_cfg *cfg = irq_cfg + 0;
1709 int apic1, pin1, apic2, pin2;
1710 unsigned long flags;
1711
1712 local_irq_save(flags);
1713
1714 /*
1715 * get/set the timer IRQ vector:
1716 */
1717 disable_8259A_irq(0);
1718 assign_irq_vector(0, TARGET_CPUS);
1719
1720 /*
1721 * Subtle, code in do_timer_interrupt() expects an AEOI
1722 * mode for the 8259A whenever interrupts are routed
1723 * through I/O APICs. Also IRQ0 has to be enabled in
1724 * the 8259A which implies the virtual wire has to be
1725 * disabled in the local APIC.
1726 */
1727 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1728 init_8259A(1);
1729 if (timer_over_8254 > 0)
1730 enable_8259A_irq(0);
1731
1732 pin1 = find_isa_irq_pin(0, mp_INT);
1733 apic1 = find_isa_irq_apic(0, mp_INT);
1734 pin2 = ioapic_i8259.pin;
1735 apic2 = ioapic_i8259.apic;
1736
1737 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1738 cfg->vector, apic1, pin1, apic2, pin2);
1739
1740 if (pin1 != -1) {
1741 /*
1742 * Ok, does IRQ0 through the IOAPIC work?
1743 */
1744 unmask_IO_APIC_irq(0);
1745 if (!no_timer_check && timer_irq_works()) {
1746 if (nmi_watchdog == NMI_IO_APIC) {
1747 disable_8259A_irq(0);
1748 setup_nmi();
1749 enable_8259A_irq(0);
1750 }
1751 if (disable_timer_pin_1 > 0)
1752 clear_IO_APIC_pin(0, pin1);
1753 goto out;
1754 }
1755 clear_IO_APIC_pin(apic1, pin1);
1756 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1757 "connected to IO-APIC\n");
1758 }
1759
1760 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1761 "through the 8259A ... ");
1762 if (pin2 != -1) {
1763 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1764 apic2, pin2);
1765 /*
1766 * legacy devices should be connected to IO APIC #0
1767 */
1768 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
1769 if (timer_irq_works()) {
1770 apic_printk(APIC_VERBOSE," works.\n");
1771 if (nmi_watchdog == NMI_IO_APIC) {
1772 setup_nmi();
1773 }
1774 goto out;
1775 }
1776 /*
1777 * Cleanup, just in case ...
1778 */
1779 clear_IO_APIC_pin(apic2, pin2);
1780 }
1781 apic_printk(APIC_VERBOSE," failed.\n");
1782
1783 if (nmi_watchdog == NMI_IO_APIC) {
1784 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1785 nmi_watchdog = 0;
1786 }
1787
1788 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1789
1790 disable_8259A_irq(0);
1791 irq_desc[0].chip = &lapic_irq_type;
1792 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1793 enable_8259A_irq(0);
1794
1795 if (timer_irq_works()) {
1796 apic_printk(APIC_VERBOSE," works.\n");
1797 goto out;
1798 }
1799 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1800 apic_printk(APIC_VERBOSE," failed.\n");
1801
1802 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1803
1804 init_8259A(0);
1805 make_8259A_irq(0);
1806 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1807
1808 unlock_ExtINT_logic();
1809
1810 if (timer_irq_works()) {
1811 apic_printk(APIC_VERBOSE," works.\n");
1812 goto out;
1813 }
1814 apic_printk(APIC_VERBOSE," failed :(.\n");
1815 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1816 out:
1817 local_irq_restore(flags);
1818 }
1819
1820 static int __init notimercheck(char *s)
1821 {
1822 no_timer_check = 1;
1823 return 1;
1824 }
1825 __setup("no_timer_check", notimercheck);
1826
1827 /*
1828 *
1829 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1830 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1831 * Linux doesn't really care, as it's not actually used
1832 * for any interrupt handling anyway.
1833 */
1834 #define PIC_IRQS (1<<2)
1835
1836 void __init setup_IO_APIC(void)
1837 {
1838
1839 /*
1840 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1841 */
1842
1843 if (acpi_ioapic)
1844 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1845 else
1846 io_apic_irqs = ~PIC_IRQS;
1847
1848 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1849
1850 sync_Arb_IDs();
1851 setup_IO_APIC_irqs();
1852 init_IO_APIC_traps();
1853 check_timer();
1854 if (!acpi_ioapic)
1855 print_IO_APIC();
1856 }
1857
1858 struct sysfs_ioapic_data {
1859 struct sys_device dev;
1860 struct IO_APIC_route_entry entry[0];
1861 };
1862 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1863
1864 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1865 {
1866 struct IO_APIC_route_entry *entry;
1867 struct sysfs_ioapic_data *data;
1868 int i;
1869
1870 data = container_of(dev, struct sysfs_ioapic_data, dev);
1871 entry = data->entry;
1872 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1873 *entry = ioapic_read_entry(dev->id, i);
1874
1875 return 0;
1876 }
1877
1878 static int ioapic_resume(struct sys_device *dev)
1879 {
1880 struct IO_APIC_route_entry *entry;
1881 struct sysfs_ioapic_data *data;
1882 unsigned long flags;
1883 union IO_APIC_reg_00 reg_00;
1884 int i;
1885
1886 data = container_of(dev, struct sysfs_ioapic_data, dev);
1887 entry = data->entry;
1888
1889 spin_lock_irqsave(&ioapic_lock, flags);
1890 reg_00.raw = io_apic_read(dev->id, 0);
1891 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1892 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1893 io_apic_write(dev->id, 0, reg_00.raw);
1894 }
1895 spin_unlock_irqrestore(&ioapic_lock, flags);
1896 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1897 ioapic_write_entry(dev->id, i, entry[i]);
1898
1899 return 0;
1900 }
1901
1902 static struct sysdev_class ioapic_sysdev_class = {
1903 .name = "ioapic",
1904 .suspend = ioapic_suspend,
1905 .resume = ioapic_resume,
1906 };
1907
1908 static int __init ioapic_init_sysfs(void)
1909 {
1910 struct sys_device * dev;
1911 int i, size, error;
1912
1913 error = sysdev_class_register(&ioapic_sysdev_class);
1914 if (error)
1915 return error;
1916
1917 for (i = 0; i < nr_ioapics; i++ ) {
1918 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1919 * sizeof(struct IO_APIC_route_entry);
1920 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1921 if (!mp_ioapic_data[i]) {
1922 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1923 continue;
1924 }
1925 dev = &mp_ioapic_data[i]->dev;
1926 dev->id = i;
1927 dev->cls = &ioapic_sysdev_class;
1928 error = sysdev_register(dev);
1929 if (error) {
1930 kfree(mp_ioapic_data[i]);
1931 mp_ioapic_data[i] = NULL;
1932 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1933 continue;
1934 }
1935 }
1936
1937 return 0;
1938 }
1939
1940 device_initcall(ioapic_init_sysfs);
1941
1942 /*
1943 * Dynamic irq allocate and deallocation
1944 */
1945 int create_irq(void)
1946 {
1947 /* Allocate an unused irq */
1948 int irq;
1949 int new;
1950 unsigned long flags;
1951
1952 irq = -ENOSPC;
1953 spin_lock_irqsave(&vector_lock, flags);
1954 for (new = (NR_IRQS - 1); new >= 0; new--) {
1955 if (platform_legacy_irq(new))
1956 continue;
1957 if (irq_cfg[new].vector != 0)
1958 continue;
1959 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1960 irq = new;
1961 break;
1962 }
1963 spin_unlock_irqrestore(&vector_lock, flags);
1964
1965 if (irq >= 0) {
1966 dynamic_irq_init(irq);
1967 }
1968 return irq;
1969 }
1970
1971 void destroy_irq(unsigned int irq)
1972 {
1973 unsigned long flags;
1974
1975 dynamic_irq_cleanup(irq);
1976
1977 spin_lock_irqsave(&vector_lock, flags);
1978 __clear_irq_vector(irq);
1979 spin_unlock_irqrestore(&vector_lock, flags);
1980 }
1981
1982 /*
1983 * MSI message composition
1984 */
1985 #ifdef CONFIG_PCI_MSI
1986 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1987 {
1988 struct irq_cfg *cfg = irq_cfg + irq;
1989 int err;
1990 unsigned dest;
1991 cpumask_t tmp;
1992
1993 tmp = TARGET_CPUS;
1994 err = assign_irq_vector(irq, tmp);
1995 if (!err) {
1996 cpus_and(tmp, cfg->domain, tmp);
1997 dest = cpu_mask_to_apicid(tmp);
1998
1999 msg->address_hi = MSI_ADDR_BASE_HI;
2000 msg->address_lo =
2001 MSI_ADDR_BASE_LO |
2002 ((INT_DEST_MODE == 0) ?
2003 MSI_ADDR_DEST_MODE_PHYSICAL:
2004 MSI_ADDR_DEST_MODE_LOGICAL) |
2005 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2006 MSI_ADDR_REDIRECTION_CPU:
2007 MSI_ADDR_REDIRECTION_LOWPRI) |
2008 MSI_ADDR_DEST_ID(dest);
2009
2010 msg->data =
2011 MSI_DATA_TRIGGER_EDGE |
2012 MSI_DATA_LEVEL_ASSERT |
2013 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2014 MSI_DATA_DELIVERY_FIXED:
2015 MSI_DATA_DELIVERY_LOWPRI) |
2016 MSI_DATA_VECTOR(cfg->vector);
2017 }
2018 return err;
2019 }
2020
2021 #ifdef CONFIG_SMP
2022 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2023 {
2024 struct irq_cfg *cfg = irq_cfg + irq;
2025 struct msi_msg msg;
2026 unsigned int dest;
2027 cpumask_t tmp;
2028
2029 cpus_and(tmp, mask, cpu_online_map);
2030 if (cpus_empty(tmp))
2031 return;
2032
2033 if (assign_irq_vector(irq, mask))
2034 return;
2035
2036 cpus_and(tmp, cfg->domain, mask);
2037 dest = cpu_mask_to_apicid(tmp);
2038
2039 read_msi_msg(irq, &msg);
2040
2041 msg.data &= ~MSI_DATA_VECTOR_MASK;
2042 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2043 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2044 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2045
2046 write_msi_msg(irq, &msg);
2047 irq_desc[irq].affinity = mask;
2048 }
2049 #endif /* CONFIG_SMP */
2050
2051 /*
2052 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2053 * which implement the MSI or MSI-X Capability Structure.
2054 */
2055 static struct irq_chip msi_chip = {
2056 .name = "PCI-MSI",
2057 .unmask = unmask_msi_irq,
2058 .mask = mask_msi_irq,
2059 .ack = ack_apic_edge,
2060 #ifdef CONFIG_SMP
2061 .set_affinity = set_msi_irq_affinity,
2062 #endif
2063 .retrigger = ioapic_retrigger_irq,
2064 };
2065
2066 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2067 {
2068 struct msi_msg msg;
2069 int irq, ret;
2070 irq = create_irq();
2071 if (irq < 0)
2072 return irq;
2073
2074 ret = msi_compose_msg(dev, irq, &msg);
2075 if (ret < 0) {
2076 destroy_irq(irq);
2077 return ret;
2078 }
2079
2080 set_irq_msi(irq, desc);
2081 write_msi_msg(irq, &msg);
2082
2083 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2084
2085 return 0;
2086 }
2087
2088 void arch_teardown_msi_irq(unsigned int irq)
2089 {
2090 destroy_irq(irq);
2091 }
2092
2093 #ifdef CONFIG_DMAR
2094 #ifdef CONFIG_SMP
2095 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2096 {
2097 struct irq_cfg *cfg = irq_cfg + irq;
2098 struct msi_msg msg;
2099 unsigned int dest;
2100 cpumask_t tmp;
2101
2102 cpus_and(tmp, mask, cpu_online_map);
2103 if (cpus_empty(tmp))
2104 return;
2105
2106 if (assign_irq_vector(irq, mask))
2107 return;
2108
2109 cpus_and(tmp, cfg->domain, mask);
2110 dest = cpu_mask_to_apicid(tmp);
2111
2112 dmar_msi_read(irq, &msg);
2113
2114 msg.data &= ~MSI_DATA_VECTOR_MASK;
2115 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2116 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2117 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2118
2119 dmar_msi_write(irq, &msg);
2120 irq_desc[irq].affinity = mask;
2121 }
2122 #endif /* CONFIG_SMP */
2123
2124 struct irq_chip dmar_msi_type = {
2125 .name = "DMAR_MSI",
2126 .unmask = dmar_msi_unmask,
2127 .mask = dmar_msi_mask,
2128 .ack = ack_apic_edge,
2129 #ifdef CONFIG_SMP
2130 .set_affinity = dmar_msi_set_affinity,
2131 #endif
2132 .retrigger = ioapic_retrigger_irq,
2133 };
2134
2135 int arch_setup_dmar_msi(unsigned int irq)
2136 {
2137 int ret;
2138 struct msi_msg msg;
2139
2140 ret = msi_compose_msg(NULL, irq, &msg);
2141 if (ret < 0)
2142 return ret;
2143 dmar_msi_write(irq, &msg);
2144 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2145 "edge");
2146 return 0;
2147 }
2148 #endif
2149
2150 #endif /* CONFIG_PCI_MSI */
2151 /*
2152 * Hypertransport interrupt support
2153 */
2154 #ifdef CONFIG_HT_IRQ
2155
2156 #ifdef CONFIG_SMP
2157
2158 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2159 {
2160 struct ht_irq_msg msg;
2161 fetch_ht_irq_msg(irq, &msg);
2162
2163 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2164 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2165
2166 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2167 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2168
2169 write_ht_irq_msg(irq, &msg);
2170 }
2171
2172 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2173 {
2174 struct irq_cfg *cfg = irq_cfg + irq;
2175 unsigned int dest;
2176 cpumask_t tmp;
2177
2178 cpus_and(tmp, mask, cpu_online_map);
2179 if (cpus_empty(tmp))
2180 return;
2181
2182 if (assign_irq_vector(irq, mask))
2183 return;
2184
2185 cpus_and(tmp, cfg->domain, mask);
2186 dest = cpu_mask_to_apicid(tmp);
2187
2188 target_ht_irq(irq, dest, cfg->vector);
2189 irq_desc[irq].affinity = mask;
2190 }
2191 #endif
2192
2193 static struct irq_chip ht_irq_chip = {
2194 .name = "PCI-HT",
2195 .mask = mask_ht_irq,
2196 .unmask = unmask_ht_irq,
2197 .ack = ack_apic_edge,
2198 #ifdef CONFIG_SMP
2199 .set_affinity = set_ht_irq_affinity,
2200 #endif
2201 .retrigger = ioapic_retrigger_irq,
2202 };
2203
2204 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2205 {
2206 struct irq_cfg *cfg = irq_cfg + irq;
2207 int err;
2208 cpumask_t tmp;
2209
2210 tmp = TARGET_CPUS;
2211 err = assign_irq_vector(irq, tmp);
2212 if (!err) {
2213 struct ht_irq_msg msg;
2214 unsigned dest;
2215
2216 cpus_and(tmp, cfg->domain, tmp);
2217 dest = cpu_mask_to_apicid(tmp);
2218
2219 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2220
2221 msg.address_lo =
2222 HT_IRQ_LOW_BASE |
2223 HT_IRQ_LOW_DEST_ID(dest) |
2224 HT_IRQ_LOW_VECTOR(cfg->vector) |
2225 ((INT_DEST_MODE == 0) ?
2226 HT_IRQ_LOW_DM_PHYSICAL :
2227 HT_IRQ_LOW_DM_LOGICAL) |
2228 HT_IRQ_LOW_RQEOI_EDGE |
2229 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2230 HT_IRQ_LOW_MT_FIXED :
2231 HT_IRQ_LOW_MT_ARBITRATED) |
2232 HT_IRQ_LOW_IRQ_MASKED;
2233
2234 write_ht_irq_msg(irq, &msg);
2235
2236 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2237 handle_edge_irq, "edge");
2238 }
2239 return err;
2240 }
2241 #endif /* CONFIG_HT_IRQ */
2242
2243 /* --------------------------------------------------------------------------
2244 ACPI-based IOAPIC Configuration
2245 -------------------------------------------------------------------------- */
2246
2247 #ifdef CONFIG_ACPI
2248
2249 #define IO_APIC_MAX_ID 0xFE
2250
2251 int __init io_apic_get_redir_entries (int ioapic)
2252 {
2253 union IO_APIC_reg_01 reg_01;
2254 unsigned long flags;
2255
2256 spin_lock_irqsave(&ioapic_lock, flags);
2257 reg_01.raw = io_apic_read(ioapic, 1);
2258 spin_unlock_irqrestore(&ioapic_lock, flags);
2259
2260 return reg_01.bits.entries;
2261 }
2262
2263
2264 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2265 {
2266 if (!IO_APIC_IRQ(irq)) {
2267 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2268 ioapic);
2269 return -EINVAL;
2270 }
2271
2272 /*
2273 * IRQs < 16 are already in the irq_2_pin[] map
2274 */
2275 if (irq >= 16)
2276 add_pin_to_irq(irq, ioapic, pin);
2277
2278 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2279
2280 return 0;
2281 }
2282
2283
2284 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2285 {
2286 int i;
2287
2288 if (skip_ioapic_setup)
2289 return -1;
2290
2291 for (i = 0; i < mp_irq_entries; i++)
2292 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2293 mp_irqs[i].mpc_srcbusirq == bus_irq)
2294 break;
2295 if (i >= mp_irq_entries)
2296 return -1;
2297
2298 *trigger = irq_trigger(i);
2299 *polarity = irq_polarity(i);
2300 return 0;
2301 }
2302
2303 #endif /* CONFIG_ACPI */
2304
2305 /*
2306 * This function currently is only a helper for the i386 smp boot process where
2307 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2308 * so mask in all cases should simply be TARGET_CPUS
2309 */
2310 #ifdef CONFIG_SMP
2311 void __init setup_ioapic_dest(void)
2312 {
2313 int pin, ioapic, irq, irq_entry;
2314
2315 if (skip_ioapic_setup == 1)
2316 return;
2317
2318 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2319 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2320 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2321 if (irq_entry == -1)
2322 continue;
2323 irq = pin_2_irq(irq_entry, ioapic, pin);
2324
2325 /* setup_IO_APIC_irqs could fail to get vector for some device
2326 * when you have too many devices, because at that time only boot
2327 * cpu is online.
2328 */
2329 if (!irq_cfg[irq].vector)
2330 setup_IO_APIC_irq(ioapic, pin, irq,
2331 irq_trigger(irq_entry),
2332 irq_polarity(irq_entry));
2333 else
2334 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2335 }
2336
2337 }
2338 }
2339 #endif
2340
2341 #define IOAPIC_RESOURCE_NAME_SIZE 11
2342
2343 static struct resource *ioapic_resources;
2344
2345 static struct resource * __init ioapic_setup_resources(void)
2346 {
2347 unsigned long n;
2348 struct resource *res;
2349 char *mem;
2350 int i;
2351
2352 if (nr_ioapics <= 0)
2353 return NULL;
2354
2355 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2356 n *= nr_ioapics;
2357
2358 mem = alloc_bootmem(n);
2359 res = (void *)mem;
2360
2361 if (mem != NULL) {
2362 memset(mem, 0, n);
2363 mem += sizeof(struct resource) * nr_ioapics;
2364
2365 for (i = 0; i < nr_ioapics; i++) {
2366 res[i].name = mem;
2367 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2368 sprintf(mem, "IOAPIC %u", i);
2369 mem += IOAPIC_RESOURCE_NAME_SIZE;
2370 }
2371 }
2372
2373 ioapic_resources = res;
2374
2375 return res;
2376 }
2377
2378 void __init ioapic_init_mappings(void)
2379 {
2380 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2381 struct resource *ioapic_res;
2382 int i;
2383
2384 ioapic_res = ioapic_setup_resources();
2385 for (i = 0; i < nr_ioapics; i++) {
2386 if (smp_found_config) {
2387 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2388 } else {
2389 ioapic_phys = (unsigned long)
2390 alloc_bootmem_pages(PAGE_SIZE);
2391 ioapic_phys = __pa(ioapic_phys);
2392 }
2393 set_fixmap_nocache(idx, ioapic_phys);
2394 apic_printk(APIC_VERBOSE,
2395 "mapped IOAPIC to %016lx (%016lx)\n",
2396 __fix_to_virt(idx), ioapic_phys);
2397 idx++;
2398
2399 if (ioapic_res != NULL) {
2400 ioapic_res->start = ioapic_phys;
2401 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2402 ioapic_res++;
2403 }
2404 }
2405 }
2406
2407 static int __init ioapic_insert_resources(void)
2408 {
2409 int i;
2410 struct resource *r = ioapic_resources;
2411
2412 if (!r) {
2413 printk(KERN_ERR
2414 "IO APIC resources could be not be allocated.\n");
2415 return -1;
2416 }
2417
2418 for (i = 0; i < nr_ioapics; i++) {
2419 insert_resource(&iomem_resource, r);
2420 r++;
2421 }
2422
2423 return 0;
2424 }
2425
2426 /* Insert the IO APIC resources after PCI initialization has occured to handle
2427 * IO APICS that are mapped in on a BAR in PCI space. */
2428 late_initcall(ioapic_insert_resources);
2429
2430
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