1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/mc146818rtc.h>
29 #include <linux/compiler.h>
30 #include <linux/acpi.h>
31 #include <linux/module.h>
32 #include <linux/sysdev.h>
33 #include <linux/pci.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39
40 #include <asm/io.h>
41 #include <asm/smp.h>
42 #include <asm/desc.h>
43 #include <asm/timer.h>
44 #include <asm/i8259.h>
45 #include <asm/nmi.h>
46 #include <asm/msidef.h>
47 #include <asm/hypertransport.h>
48
49 #include <mach_apic.h>
50 #include <mach_apicdef.h>
51
52 int (*ioapic_renumber_irq)(int ioapic, int irq);
53 atomic_t irq_mis_count;
54
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
57
58 static DEFINE_RAW_SPINLOCK(ioapic_lock);
59 static DEFINE_RAW_SPINLOCK(vector_lock);
60
61 int timer_over_8254 __initdata = 1;
62
63 /*
64 * Is the SiS APIC rmw bug present ?
65 * -1 = don't know, 0 = no, 1 = yes
66 */
67 int sis_apic_bug = -1;
68
69 /*
70 * # of IRQ routing registers
71 */
72 int nr_ioapic_registers[MAX_IO_APICS];
73
74 static int disable_timer_pin_1 __initdata;
75
76 /*
77 * Rough estimation of how many shared IRQs there are, can
78 * be changed anytime.
79 */
80 #define MAX_PLUS_SHARED_IRQS NR_IRQS
81 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
82
83 /*
84 * This is performance-critical, we want to do it O(1)
85 *
86 * the indexing order of this array favors 1:1 mappings
87 * between pins and IRQs.
88 */
89
90 static struct irq_pin_list {
91 int apic, pin, next;
92 } irq_2_pin[PIN_MAP_SIZE];
93
94 struct io_apic {
95 unsigned int index;
96 unsigned int unused[3];
97 unsigned int data;
98 };
99
100 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
101 {
102 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
103 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
104 }
105
106 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
107 {
108 struct io_apic __iomem *io_apic = io_apic_base(apic);
109 writel(reg, &io_apic->index);
110 return readl(&io_apic->data);
111 }
112
113 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
114 {
115 struct io_apic __iomem *io_apic = io_apic_base(apic);
116 writel(reg, &io_apic->index);
117 writel(value, &io_apic->data);
118 }
119
120 /*
121 * Re-write a value: to be used for read-modify-write
122 * cycles where the read already set up the index register.
123 *
124 * Older SiS APIC requires we rewrite the index register
125 */
126 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
127 {
128 volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
129 if (sis_apic_bug)
130 writel(reg, &io_apic->index);
131 writel(value, &io_apic->data);
132 }
133
134 union entry_union {
135 struct { u32 w1, w2; };
136 struct IO_APIC_route_entry entry;
137 };
138
139 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
140 {
141 union entry_union eu;
142 unsigned long flags;
143 spin_lock_irqsave(&ioapic_lock, flags);
144 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
145 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
146 spin_unlock_irqrestore(&ioapic_lock, flags);
147 return eu.entry;
148 }
149
150 /*
151 * When we write a new IO APIC routing entry, we need to write the high
152 * word first! If the mask bit in the low word is clear, we will enable
153 * the interrupt, and we need to make sure the entry is fully populated
154 * before that happens.
155 */
156 static void
157 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
158 {
159 union entry_union eu;
160 eu.entry = e;
161 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
162 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
163 }
164
165 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
166 {
167 unsigned long flags;
168 spin_lock_irqsave(&ioapic_lock, flags);
169 __ioapic_write_entry(apic, pin, e);
170 spin_unlock_irqrestore(&ioapic_lock, flags);
171 }
172
173 /*
174 * When we mask an IO APIC routing entry, we need to write the low
175 * word first, in order to set the mask bit before we change the
176 * high bits!
177 */
178 static void ioapic_mask_entry(int apic, int pin)
179 {
180 unsigned long flags;
181 union entry_union eu = { .entry.mask = 1 };
182
183 spin_lock_irqsave(&ioapic_lock, flags);
184 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
185 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
186 spin_unlock_irqrestore(&ioapic_lock, flags);
187 }
188
189 /*
190 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
191 * shared ISA-space IRQs, so we have to support them. We are super
192 * fast in the common case, and fast for shared ISA-space IRQs.
193 */
194 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
195 {
196 static int first_free_entry = NR_IRQS;
197 struct irq_pin_list *entry = irq_2_pin + irq;
198
199 while (entry->next)
200 entry = irq_2_pin + entry->next;
201
202 if (entry->pin != -1) {
203 entry->next = first_free_entry;
204 entry = irq_2_pin + entry->next;
205 if (++first_free_entry >= PIN_MAP_SIZE)
206 panic("io_apic.c: whoops");
207 }
208 entry->apic = apic;
209 entry->pin = pin;
210 }
211
212 /*
213 * Reroute an IRQ to a different pin.
214 */
215 static void __init replace_pin_at_irq(unsigned int irq,
216 int oldapic, int oldpin,
217 int newapic, int newpin)
218 {
219 struct irq_pin_list *entry = irq_2_pin + irq;
220
221 while (1) {
222 if (entry->apic == oldapic && entry->pin == oldpin) {
223 entry->apic = newapic;
224 entry->pin = newpin;
225 }
226 if (!entry->next)
227 break;
228 entry = irq_2_pin + entry->next;
229 }
230 }
231
232 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
233 {
234 struct irq_pin_list *entry = irq_2_pin + irq;
235 unsigned int pin, reg;
236
237 for (;;) {
238 pin = entry->pin;
239 if (pin == -1)
240 break;
241 reg = io_apic_read(entry->apic, 0x10 + pin*2);
242 reg &= ~disable;
243 reg |= enable;
244 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
245 if (!entry->next)
246 break;
247 entry = irq_2_pin + entry->next;
248 }
249 }
250
251 /* mask = 1 */
252 static void __mask_IO_APIC_irq (unsigned int irq)
253 {
254 __modify_IO_APIC_irq(irq, 0x00010000, 0);
255 }
256
257 /* mask = 0 */
258 static void __unmask_IO_APIC_irq (unsigned int irq)
259 {
260 __modify_IO_APIC_irq(irq, 0, 0x00010000);
261 }
262
263 /* trigger = 0 (edge mode) */
264 static void __pcix_mask_IO_APIC_irq (unsigned int irq)
265 {
266 __modify_IO_APIC_irq(irq, 0, 0x00008000);
267 }
268
269 /* mask = 0, trigger = 1 (level mode) */
270 static void __pcix_unmask_IO_APIC_irq (unsigned int irq)
271 {
272 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
273 }
274
275 static void mask_IO_APIC_irq (unsigned int irq)
276 {
277 unsigned long flags;
278
279 spin_lock_irqsave(&ioapic_lock, flags);
280 __mask_IO_APIC_irq(irq);
281 spin_unlock_irqrestore(&ioapic_lock, flags);
282 }
283
284 static void unmask_IO_APIC_irq (unsigned int irq)
285 {
286 unsigned long flags;
287
288 spin_lock_irqsave(&ioapic_lock, flags);
289 __unmask_IO_APIC_irq(irq);
290 spin_unlock_irqrestore(&ioapic_lock, flags);
291 }
292
293 static void pcix_mask_IO_APIC_irq (unsigned int irq)
294 {
295 unsigned long flags;
296
297 spin_lock_irqsave(&ioapic_lock, flags);
298 __pcix_mask_IO_APIC_irq(irq);
299 spin_unlock_irqrestore(&ioapic_lock, flags);
300 }
301
302 static void pcix_unmask_IO_APIC_irq (unsigned int irq)
303 {
304 unsigned long flags;
305
306 spin_lock_irqsave(&ioapic_lock, flags);
307 __pcix_unmask_IO_APIC_irq(irq);
308 spin_unlock_irqrestore(&ioapic_lock, flags);
309 }
310
311 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
312 {
313 struct IO_APIC_route_entry entry;
314
315 /* Check delivery_mode to be sure we're not clearing an SMI pin */
316 entry = ioapic_read_entry(apic, pin);
317 if (entry.delivery_mode == dest_SMI)
318 return;
319
320 /*
321 * Disable it in the IO-APIC irq-routing table:
322 */
323 ioapic_mask_entry(apic, pin);
324 }
325
326 static void clear_IO_APIC (void)
327 {
328 int apic, pin;
329
330 for (apic = 0; apic < nr_ioapics; apic++)
331 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
332 clear_IO_APIC_pin(apic, pin);
333 }
334
335 #ifdef CONFIG_SMP
336 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
337 {
338 unsigned long flags;
339 int pin;
340 struct irq_pin_list *entry = irq_2_pin + irq;
341 unsigned int apicid_value;
342 cpumask_t tmp;
343
344 cpus_and(tmp, cpumask, cpu_online_map);
345 if (cpus_empty(tmp))
346 tmp = TARGET_CPUS;
347
348 cpus_and(cpumask, tmp, CPU_MASK_ALL);
349
350 apicid_value = cpu_mask_to_apicid(cpumask);
351 /* Prepare to do the io_apic_write */
352 apicid_value = apicid_value << 24;
353 spin_lock_irqsave(&ioapic_lock, flags);
354 for (;;) {
355 pin = entry->pin;
356 if (pin == -1)
357 break;
358 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
359 if (!entry->next)
360 break;
361 entry = irq_2_pin + entry->next;
362 }
363 irq_desc[irq].affinity = cpumask;
364 spin_unlock_irqrestore(&ioapic_lock, flags);
365 }
366
367 #if defined(CONFIG_IRQBALANCE)
368 # include <asm/processor.h> /* kernel_thread() */
369 # include <linux/kernel_stat.h> /* kstat */
370 # include <linux/slab.h> /* kmalloc() */
371 # include <linux/timer.h>
372
373 #define IRQBALANCE_CHECK_ARCH -999
374 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
375 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
376 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
377 #define BALANCED_IRQ_LESS_DELTA (HZ)
378
379 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
380 static int physical_balance __read_mostly;
381 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
382
383 static struct irq_cpu_info {
384 unsigned long * last_irq;
385 unsigned long * irq_delta;
386 unsigned long irq;
387 } irq_cpu_data[NR_CPUS];
388
389 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
390 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
391 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
392
393 #define IDLE_ENOUGH(cpu,now) \
394 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
395
396 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
397
398 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
399
400 static cpumask_t balance_irq_affinity[NR_IRQS] = {
401 [0 ... NR_IRQS-1] = CPU_MASK_ALL
402 };
403
404 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
405 {
406 balance_irq_affinity[irq] = mask;
407 }
408
409 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
410 unsigned long now, int direction)
411 {
412 int search_idle = 1;
413 int cpu = curr_cpu;
414
415 goto inside;
416
417 do {
418 if (unlikely(cpu == curr_cpu))
419 search_idle = 0;
420 inside:
421 if (direction == 1) {
422 cpu++;
423 if (cpu >= NR_CPUS)
424 cpu = 0;
425 } else {
426 cpu--;
427 if (cpu == -1)
428 cpu = NR_CPUS-1;
429 }
430 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
431 (search_idle && !IDLE_ENOUGH(cpu,now)));
432
433 return cpu;
434 }
435
436 static inline void balance_irq(int cpu, int irq)
437 {
438 unsigned long now = jiffies;
439 cpumask_t allowed_mask;
440 unsigned int new_cpu;
441
442 if (irqbalance_disabled)
443 return;
444
445 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
446 new_cpu = move(cpu, allowed_mask, now, 1);
447 if (cpu != new_cpu) {
448 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
449 }
450 }
451
452 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
453 {
454 int i, j;
455
456 for_each_online_cpu(i) {
457 for (j = 0; j < NR_IRQS; j++) {
458 if (!irq_desc[j].action)
459 continue;
460 /* Is it a significant load ? */
461 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
462 useful_load_threshold)
463 continue;
464 balance_irq(i, j);
465 }
466 }
467 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
468 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
469 return;
470 }
471
472 static void do_irq_balance(void)
473 {
474 int i, j;
475 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
476 unsigned long move_this_load = 0;
477 int max_loaded = 0, min_loaded = 0;
478 int load;
479 unsigned long useful_load_threshold = balanced_irq_interval + 10;
480 int selected_irq;
481 int tmp_loaded, first_attempt = 1;
482 unsigned long tmp_cpu_irq;
483 unsigned long imbalance = 0;
484 cpumask_t allowed_mask, target_cpu_mask, tmp;
485
486 for_each_possible_cpu(i) {
487 int package_index;
488 CPU_IRQ(i) = 0;
489 if (!cpu_online(i))
490 continue;
491 package_index = CPU_TO_PACKAGEINDEX(i);
492 for (j = 0; j < NR_IRQS; j++) {
493 unsigned long value_now, delta;
494 /* Is this an active IRQ or balancing disabled ? */
495 if (!irq_desc[j].action || irq_balancing_disabled(j))
496 continue;
497 if ( package_index == i )
498 IRQ_DELTA(package_index,j) = 0;
499 /* Determine the total count per processor per IRQ */
500 value_now = (unsigned long) kstat_cpu(i).irqs[j];
501
502 /* Determine the activity per processor per IRQ */
503 delta = value_now - LAST_CPU_IRQ(i,j);
504
505 /* Update last_cpu_irq[][] for the next time */
506 LAST_CPU_IRQ(i,j) = value_now;
507
508 /* Ignore IRQs whose rate is less than the clock */
509 if (delta < useful_load_threshold)
510 continue;
511 /* update the load for the processor or package total */
512 IRQ_DELTA(package_index,j) += delta;
513
514 /* Keep track of the higher numbered sibling as well */
515 if (i != package_index)
516 CPU_IRQ(i) += delta;
517 /*
518 * We have sibling A and sibling B in the package
519 *
520 * cpu_irq[A] = load for cpu A + load for cpu B
521 * cpu_irq[B] = load for cpu B
522 */
523 CPU_IRQ(package_index) += delta;
524 }
525 }
526 /* Find the least loaded processor package */
527 for_each_online_cpu(i) {
528 if (i != CPU_TO_PACKAGEINDEX(i))
529 continue;
530 if (min_cpu_irq > CPU_IRQ(i)) {
531 min_cpu_irq = CPU_IRQ(i);
532 min_loaded = i;
533 }
534 }
535 max_cpu_irq = ULONG_MAX;
536
537 tryanothercpu:
538 /* Look for heaviest loaded processor.
539 * We may come back to get the next heaviest loaded processor.
540 * Skip processors with trivial loads.
541 */
542 tmp_cpu_irq = 0;
543 tmp_loaded = -1;
544 for_each_online_cpu(i) {
545 if (i != CPU_TO_PACKAGEINDEX(i))
546 continue;
547 if (max_cpu_irq <= CPU_IRQ(i))
548 continue;
549 if (tmp_cpu_irq < CPU_IRQ(i)) {
550 tmp_cpu_irq = CPU_IRQ(i);
551 tmp_loaded = i;
552 }
553 }
554
555 if (tmp_loaded == -1) {
556 /* In the case of small number of heavy interrupt sources,
557 * loading some of the cpus too much. We use Ingo's original
558 * approach to rotate them around.
559 */
560 if (!first_attempt && imbalance >= useful_load_threshold) {
561 rotate_irqs_among_cpus(useful_load_threshold);
562 return;
563 }
564 goto not_worth_the_effort;
565 }
566
567 first_attempt = 0; /* heaviest search */
568 max_cpu_irq = tmp_cpu_irq; /* load */
569 max_loaded = tmp_loaded; /* processor */
570 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
571
572 /* if imbalance is less than approx 10% of max load, then
573 * observe diminishing returns action. - quit
574 */
575 if (imbalance < (max_cpu_irq >> 3))
576 goto not_worth_the_effort;
577
578 tryanotherirq:
579 /* if we select an IRQ to move that can't go where we want, then
580 * see if there is another one to try.
581 */
582 move_this_load = 0;
583 selected_irq = -1;
584 for (j = 0; j < NR_IRQS; j++) {
585 /* Is this an active IRQ? */
586 if (!irq_desc[j].action)
587 continue;
588 if (imbalance <= IRQ_DELTA(max_loaded,j))
589 continue;
590 /* Try to find the IRQ that is closest to the imbalance
591 * without going over.
592 */
593 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
594 move_this_load = IRQ_DELTA(max_loaded,j);
595 selected_irq = j;
596 }
597 }
598 if (selected_irq == -1) {
599 goto tryanothercpu;
600 }
601
602 imbalance = move_this_load;
603
604 /* For physical_balance case, we accumulated both load
605 * values in the one of the siblings cpu_irq[],
606 * to use the same code for physical and logical processors
607 * as much as possible.
608 *
609 * NOTE: the cpu_irq[] array holds the sum of the load for
610 * sibling A and sibling B in the slot for the lowest numbered
611 * sibling (A), _AND_ the load for sibling B in the slot for
612 * the higher numbered sibling.
613 *
614 * We seek the least loaded sibling by making the comparison
615 * (A+B)/2 vs B
616 */
617 load = CPU_IRQ(min_loaded) >> 1;
618 for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
619 if (load > CPU_IRQ(j)) {
620 /* This won't change cpu_sibling_map[min_loaded] */
621 load = CPU_IRQ(j);
622 min_loaded = j;
623 }
624 }
625
626 cpus_and(allowed_mask,
627 cpu_online_map,
628 balance_irq_affinity[selected_irq]);
629 target_cpu_mask = cpumask_of_cpu(min_loaded);
630 cpus_and(tmp, target_cpu_mask, allowed_mask);
631
632 if (!cpus_empty(tmp)) {
633 /* mark for change destination */
634 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
635
636 /* Since we made a change, come back sooner to
637 * check for more variation.
638 */
639 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
640 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
641 return;
642 }
643 goto tryanotherirq;
644
645 not_worth_the_effort:
646 /*
647 * if we did not find an IRQ to move, then adjust the time interval
648 * upward
649 */
650 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
651 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
652 return;
653 }
654
655 static int balanced_irq(void *unused)
656 {
657 int i;
658 unsigned long prev_balance_time = jiffies;
659 long time_remaining = balanced_irq_interval;
660
661 /* push everything to CPU 0 to give us a starting point. */
662 for (i = 0 ; i < NR_IRQS ; i++) {
663 irq_desc[i].pending_mask = cpumask_of_cpu(0);
664 set_pending_irq(i, cpumask_of_cpu(0));
665 }
666
667 set_freezable();
668 for ( ; ; ) {
669 time_remaining = schedule_timeout_interruptible(time_remaining);
670 try_to_freeze();
671 if (time_after(jiffies,
672 prev_balance_time+balanced_irq_interval)) {
673 preempt_disable();
674 do_irq_balance();
675 prev_balance_time = jiffies;
676 time_remaining = balanced_irq_interval;
677 preempt_enable();
678 }
679 }
680 return 0;
681 }
682
683 static int __init balanced_irq_init(void)
684 {
685 int i;
686 struct cpuinfo_x86 *c;
687 cpumask_t tmp;
688
689 cpus_shift_right(tmp, cpu_online_map, 2);
690 c = &boot_cpu_data;
691 /* When not overwritten by the command line ask subarchitecture. */
692 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
693 irqbalance_disabled = NO_BALANCE_IRQ;
694 if (irqbalance_disabled)
695 return 0;
696
697 /* disable irqbalance completely if there is only one processor online */
698 if (num_online_cpus() < 2) {
699 irqbalance_disabled = 1;
700 return 0;
701 }
702 /*
703 * Enable physical balance only if more than 1 physical processor
704 * is present
705 */
706 if (smp_num_siblings > 1 && !cpus_empty(tmp))
707 physical_balance = 1;
708
709 for_each_online_cpu(i) {
710 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
711 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
712 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
713 printk(KERN_ERR "balanced_irq_init: out of memory");
714 goto failed;
715 }
716 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
717 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
718 }
719
720 printk(KERN_INFO "Starting balanced_irq\n");
721 if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
722 return 0;
723 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
724 failed:
725 for_each_possible_cpu(i) {
726 kfree(irq_cpu_data[i].irq_delta);
727 irq_cpu_data[i].irq_delta = NULL;
728 kfree(irq_cpu_data[i].last_irq);
729 irq_cpu_data[i].last_irq = NULL;
730 }
731 return 0;
732 }
733
734 int __devinit irqbalance_disable(char *str)
735 {
736 irqbalance_disabled = 1;
737 return 1;
738 }
739
740 __setup("noirqbalance", irqbalance_disable);
741
742 late_initcall(balanced_irq_init);
743 #endif /* CONFIG_IRQBALANCE */
744 #endif /* CONFIG_SMP */
745
746 #ifndef CONFIG_SMP
747 void send_IPI_self(int vector)
748 {
749 unsigned int cfg;
750
751 /*
752 * Wait for idle.
753 */
754 apic_wait_icr_idle();
755 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
756 /*
757 * Send the IPI. The write to APIC_ICR fires this off.
758 */
759 apic_write_around(APIC_ICR, cfg);
760 }
761 #endif /* !CONFIG_SMP */
762
763
764 /*
765 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
766 * specific CPU-side IRQs.
767 */
768
769 #define MAX_PIRQS 8
770 static int pirq_entries [MAX_PIRQS];
771 static int pirqs_enabled;
772 int skip_ioapic_setup;
773
774 static int __init ioapic_pirq_setup(char *str)
775 {
776 int i, max;
777 int ints[MAX_PIRQS+1];
778
779 get_options(str, ARRAY_SIZE(ints), ints);
780
781 for (i = 0; i < MAX_PIRQS; i++)
782 pirq_entries[i] = -1;
783
784 pirqs_enabled = 1;
785 apic_printk(APIC_VERBOSE, KERN_INFO
786 "PIRQ redirection, working around broken MP-BIOS.\n");
787 max = MAX_PIRQS;
788 if (ints[0] < MAX_PIRQS)
789 max = ints[0];
790
791 for (i = 0; i < max; i++) {
792 apic_printk(APIC_VERBOSE, KERN_DEBUG
793 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
794 /*
795 * PIRQs are mapped upside down, usually.
796 */
797 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
798 }
799 return 1;
800 }
801
802 __setup("pirq=", ioapic_pirq_setup);
803
804 /*
805 * Find the IRQ entry number of a certain pin.
806 */
807 static int find_irq_entry(int apic, int pin, int type)
808 {
809 int i;
810
811 for (i = 0; i < mp_irq_entries; i++)
812 if (mp_irqs[i].mpc_irqtype == type &&
813 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
814 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
815 mp_irqs[i].mpc_dstirq == pin)
816 return i;
817
818 return -1;
819 }
820
821 /*
822 * Find the pin to which IRQ[irq] (ISA) is connected
823 */
824 static int __init find_isa_irq_pin(int irq, int type)
825 {
826 int i;
827
828 for (i = 0; i < mp_irq_entries; i++) {
829 int lbus = mp_irqs[i].mpc_srcbus;
830
831 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
832 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
833 mp_bus_id_to_type[lbus] == MP_BUS_MCA
834 ) &&
835 (mp_irqs[i].mpc_irqtype == type) &&
836 (mp_irqs[i].mpc_srcbusirq == irq))
837
838 return mp_irqs[i].mpc_dstirq;
839 }
840 return -1;
841 }
842
843 static int __init find_isa_irq_apic(int irq, int type)
844 {
845 int i;
846
847 for (i = 0; i < mp_irq_entries; i++) {
848 int lbus = mp_irqs[i].mpc_srcbus;
849
850 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
851 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
852 mp_bus_id_to_type[lbus] == MP_BUS_MCA
853 ) &&
854 (mp_irqs[i].mpc_irqtype == type) &&
855 (mp_irqs[i].mpc_srcbusirq == irq))
856 break;
857 }
858 if (i < mp_irq_entries) {
859 int apic;
860 for(apic = 0; apic < nr_ioapics; apic++) {
861 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
862 return apic;
863 }
864 }
865
866 return -1;
867 }
868
869 /*
870 * Find a specific PCI IRQ entry.
871 * Not an __init, possibly needed by modules
872 */
873 static int pin_2_irq(int idx, int apic, int pin);
874
875 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
876 {
877 int apic, i, best_guess = -1;
878
879 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
880 "slot:%d, pin:%d.\n", bus, slot, pin);
881 if (mp_bus_id_to_pci_bus[bus] == -1) {
882 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
883 return -1;
884 }
885 for (i = 0; i < mp_irq_entries; i++) {
886 int lbus = mp_irqs[i].mpc_srcbus;
887
888 for (apic = 0; apic < nr_ioapics; apic++)
889 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
890 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
891 break;
892
893 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
894 !mp_irqs[i].mpc_irqtype &&
895 (bus == lbus) &&
896 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
897 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
898
899 if (!(apic || IO_APIC_IRQ(irq)))
900 continue;
901
902 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
903 return irq;
904 /*
905 * Use the first all-but-pin matching entry as a
906 * best-guess fuzzy result for broken mptables.
907 */
908 if (best_guess < 0)
909 best_guess = irq;
910 }
911 }
912 return best_guess;
913 }
914 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
915
916 /*
917 * This function currently is only a helper for the i386 smp boot process where
918 * we need to reprogram the ioredtbls to cater for the cpus which have come online
919 * so mask in all cases should simply be TARGET_CPUS
920 */
921 #ifdef CONFIG_SMP
922 void __init setup_ioapic_dest(void)
923 {
924 int pin, ioapic, irq, irq_entry;
925
926 if (skip_ioapic_setup == 1)
927 return;
928
929 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
930 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
931 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
932 if (irq_entry == -1)
933 continue;
934 irq = pin_2_irq(irq_entry, ioapic, pin);
935 set_ioapic_affinity_irq(irq, TARGET_CPUS);
936 }
937
938 }
939 }
940 #endif
941
942 /*
943 * EISA Edge/Level control register, ELCR
944 */
945 static int EISA_ELCR(unsigned int irq)
946 {
947 if (irq < 16) {
948 unsigned int port = 0x4d0 + (irq >> 3);
949 return (inb(port) >> (irq & 7)) & 1;
950 }
951 apic_printk(APIC_VERBOSE, KERN_INFO
952 "Broken MPtable reports ISA irq %d\n", irq);
953 return 0;
954 }
955
956 /* EISA interrupts are always polarity zero and can be edge or level
957 * trigger depending on the ELCR value. If an interrupt is listed as
958 * EISA conforming in the MP table, that means its trigger type must
959 * be read in from the ELCR */
960
961 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
962 #define default_EISA_polarity(idx) (0)
963
964 /* ISA interrupts are always polarity zero edge triggered,
965 * when listed as conforming in the MP table. */
966
967 #define default_ISA_trigger(idx) (0)
968 #define default_ISA_polarity(idx) (0)
969
970 /* PCI interrupts are always polarity one level triggered,
971 * when listed as conforming in the MP table. */
972
973 #define default_PCI_trigger(idx) (1)
974 #define default_PCI_polarity(idx) (1)
975
976 /* MCA interrupts are always polarity zero level triggered,
977 * when listed as conforming in the MP table. */
978
979 #define default_MCA_trigger(idx) (1)
980 #define default_MCA_polarity(idx) (0)
981
982 static int MPBIOS_polarity(int idx)
983 {
984 int bus = mp_irqs[idx].mpc_srcbus;
985 int polarity;
986
987 /*
988 * Determine IRQ line polarity (high active or low active):
989 */
990 switch (mp_irqs[idx].mpc_irqflag & 3)
991 {
992 case 0: /* conforms, ie. bus-type dependent polarity */
993 {
994 switch (mp_bus_id_to_type[bus])
995 {
996 case MP_BUS_ISA: /* ISA pin */
997 {
998 polarity = default_ISA_polarity(idx);
999 break;
1000 }
1001 case MP_BUS_EISA: /* EISA pin */
1002 {
1003 polarity = default_EISA_polarity(idx);
1004 break;
1005 }
1006 case MP_BUS_PCI: /* PCI pin */
1007 {
1008 polarity = default_PCI_polarity(idx);
1009 break;
1010 }
1011 case MP_BUS_MCA: /* MCA pin */
1012 {
1013 polarity = default_MCA_polarity(idx);
1014 break;
1015 }
1016 default:
1017 {
1018 printk(KERN_WARNING "broken BIOS!!\n");
1019 polarity = 1;
1020 break;
1021 }
1022 }
1023 break;
1024 }
1025 case 1: /* high active */
1026 {
1027 polarity = 0;
1028 break;
1029 }
1030 case 2: /* reserved */
1031 {
1032 printk(KERN_WARNING "broken BIOS!!\n");
1033 polarity = 1;
1034 break;
1035 }
1036 case 3: /* low active */
1037 {
1038 polarity = 1;
1039 break;
1040 }
1041 default: /* invalid */
1042 {
1043 printk(KERN_WARNING "broken BIOS!!\n");
1044 polarity = 1;
1045 break;
1046 }
1047 }
1048 return polarity;
1049 }
1050
1051 static int MPBIOS_trigger(int idx)
1052 {
1053 int bus = mp_irqs[idx].mpc_srcbus;
1054 int trigger;
1055
1056 /*
1057 * Determine IRQ trigger mode (edge or level sensitive):
1058 */
1059 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1060 {
1061 case 0: /* conforms, ie. bus-type dependent */
1062 {
1063 switch (mp_bus_id_to_type[bus])
1064 {
1065 case MP_BUS_ISA: /* ISA pin */
1066 {
1067 trigger = default_ISA_trigger(idx);
1068 break;
1069 }
1070 case MP_BUS_EISA: /* EISA pin */
1071 {
1072 trigger = default_EISA_trigger(idx);
1073 break;
1074 }
1075 case MP_BUS_PCI: /* PCI pin */
1076 {
1077 trigger = default_PCI_trigger(idx);
1078 break;
1079 }
1080 case MP_BUS_MCA: /* MCA pin */
1081 {
1082 trigger = default_MCA_trigger(idx);
1083 break;
1084 }
1085 default:
1086 {
1087 printk(KERN_WARNING "broken BIOS!!\n");
1088 trigger = 1;
1089 break;
1090 }
1091 }
1092 break;
1093 }
1094 case 1: /* edge */
1095 {
1096 trigger = 0;
1097 break;
1098 }
1099 case 2: /* reserved */
1100 {
1101 printk(KERN_WARNING "broken BIOS!!\n");
1102 trigger = 1;
1103 break;
1104 }
1105 case 3: /* level */
1106 {
1107 trigger = 1;
1108 break;
1109 }
1110 default: /* invalid */
1111 {
1112 printk(KERN_WARNING "broken BIOS!!\n");
1113 trigger = 0;
1114 break;
1115 }
1116 }
1117 return trigger;
1118 }
1119
1120 static inline int irq_polarity(int idx)
1121 {
1122 return MPBIOS_polarity(idx);
1123 }
1124
1125 static inline int irq_trigger(int idx)
1126 {
1127 return MPBIOS_trigger(idx);
1128 }
1129
1130 static int pin_2_irq(int idx, int apic, int pin)
1131 {
1132 int irq, i;
1133 int bus = mp_irqs[idx].mpc_srcbus;
1134
1135 /*
1136 * Debugging check, we are in big trouble if this message pops up!
1137 */
1138 if (mp_irqs[idx].mpc_dstirq != pin)
1139 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1140
1141 switch (mp_bus_id_to_type[bus])
1142 {
1143 case MP_BUS_ISA: /* ISA pin */
1144 case MP_BUS_EISA:
1145 case MP_BUS_MCA:
1146 {
1147 irq = mp_irqs[idx].mpc_srcbusirq;
1148 break;
1149 }
1150 case MP_BUS_PCI: /* PCI pin */
1151 {
1152 /*
1153 * PCI IRQs are mapped in order
1154 */
1155 i = irq = 0;
1156 while (i < apic)
1157 irq += nr_ioapic_registers[i++];
1158 irq += pin;
1159
1160 /*
1161 * For MPS mode, so far only needed by ES7000 platform
1162 */
1163 if (ioapic_renumber_irq)
1164 irq = ioapic_renumber_irq(apic, irq);
1165
1166 break;
1167 }
1168 default:
1169 {
1170 printk(KERN_ERR "unknown bus type %d.\n",bus);
1171 irq = 0;
1172 break;
1173 }
1174 }
1175
1176 /*
1177 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1178 */
1179 if ((pin >= 16) && (pin <= 23)) {
1180 if (pirq_entries[pin-16] != -1) {
1181 if (!pirq_entries[pin-16]) {
1182 apic_printk(APIC_VERBOSE, KERN_DEBUG
1183 "disabling PIRQ%d\n", pin-16);
1184 } else {
1185 irq = pirq_entries[pin-16];
1186 apic_printk(APIC_VERBOSE, KERN_DEBUG
1187 "using PIRQ%d -> IRQ %d\n",
1188 pin-16, irq);
1189 }
1190 }
1191 }
1192 return irq;
1193 }
1194
1195 static inline int IO_APIC_irq_trigger(int irq)
1196 {
1197 int apic, idx, pin;
1198
1199 for (apic = 0; apic < nr_ioapics; apic++) {
1200 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1201 idx = find_irq_entry(apic,pin,mp_INT);
1202 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1203 return irq_trigger(idx);
1204 }
1205 }
1206 /*
1207 * nonexistent IRQs are edge default
1208 */
1209 return 0;
1210 }
1211
1212 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1213 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1214
1215 static int __assign_irq_vector(int irq)
1216 {
1217 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1218 int vector, offset;
1219
1220 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1221
1222 if (irq_vector[irq] > 0)
1223 return irq_vector[irq];
1224
1225 vector = current_vector;
1226 offset = current_offset;
1227 next:
1228 vector += 8;
1229 if (vector >= FIRST_SYSTEM_VECTOR) {
1230 offset = (offset + 1) % 8;
1231 vector = FIRST_DEVICE_VECTOR + offset;
1232 }
1233 if (vector == current_vector)
1234 return -ENOSPC;
1235 if (test_and_set_bit(vector, used_vectors))
1236 goto next;
1237
1238 current_vector = vector;
1239 current_offset = offset;
1240 irq_vector[irq] = vector;
1241
1242 return vector;
1243 }
1244
1245 static int assign_irq_vector(int irq)
1246 {
1247 unsigned long flags;
1248 int vector;
1249
1250 spin_lock_irqsave(&vector_lock, flags);
1251 vector = __assign_irq_vector(irq);
1252 spin_unlock_irqrestore(&vector_lock, flags);
1253
1254 return vector;
1255 }
1256
1257 static struct irq_chip ioapic_chip;
1258 static struct irq_chip pcix_ioapic_chip;
1259
1260 #define IOAPIC_AUTO -1
1261 #define IOAPIC_EDGE 0
1262 #define IOAPIC_LEVEL 1
1263
1264 static void ioapic_register_intr(int irq, int vector, unsigned long trigger,
1265 int pcix)
1266 {
1267 struct irq_chip *chip = pcix ? &pcix_ioapic_chip : &ioapic_chip;
1268
1269 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1270 trigger == IOAPIC_LEVEL) {
1271 irq_desc[irq].status |= IRQ_LEVEL;
1272 set_irq_chip_and_handler_name(irq, chip, handle_fasteoi_irq,
1273 pcix ? "pcix-fasteoi" : "fasteoi");
1274 } else {
1275 irq_desc[irq].status &= ~IRQ_LEVEL;
1276 set_irq_chip_and_handler_name(irq, chip, handle_edge_irq,
1277 pcix ? "pcix-edge" : "edge");
1278 }
1279 set_intr_gate(vector, interrupt[irq]);
1280 }
1281
1282 static void __init setup_IO_APIC_irqs(void)
1283 {
1284 struct IO_APIC_route_entry entry;
1285 int apic, pin, idx, irq, first_notcon = 1, vector;
1286 unsigned long flags;
1287
1288 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1289
1290 for (apic = 0; apic < nr_ioapics; apic++) {
1291 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1292
1293 /*
1294 * add it to the IO-APIC irq-routing table:
1295 */
1296 memset(&entry,0,sizeof(entry));
1297
1298 entry.delivery_mode = INT_DELIVERY_MODE;
1299 entry.dest_mode = INT_DEST_MODE;
1300 entry.mask = 0; /* enable IRQ */
1301 entry.dest.logical.logical_dest =
1302 cpu_mask_to_apicid(TARGET_CPUS);
1303
1304 idx = find_irq_entry(apic,pin,mp_INT);
1305 if (idx == -1) {
1306 if (first_notcon) {
1307 apic_printk(APIC_VERBOSE, KERN_DEBUG
1308 " IO-APIC (apicid-pin) %d-%d",
1309 mp_ioapics[apic].mpc_apicid,
1310 pin);
1311 first_notcon = 0;
1312 } else
1313 apic_printk(APIC_VERBOSE, ", %d-%d",
1314 mp_ioapics[apic].mpc_apicid, pin);
1315 continue;
1316 }
1317
1318 if (!first_notcon) {
1319 apic_printk(APIC_VERBOSE, " not connected.\n");
1320 first_notcon = 1;
1321 }
1322
1323 entry.trigger = irq_trigger(idx);
1324 entry.polarity = irq_polarity(idx);
1325
1326 if (irq_trigger(idx)) {
1327 entry.trigger = 1;
1328 entry.mask = 1;
1329 }
1330
1331 irq = pin_2_irq(idx, apic, pin);
1332 /*
1333 * skip adding the timer int on secondary nodes, which causes
1334 * a small but painful rift in the time-space continuum
1335 */
1336 if (multi_timer_check(apic, irq))
1337 continue;
1338 else
1339 add_pin_to_irq(irq, apic, pin);
1340
1341 if (!apic && !IO_APIC_IRQ(irq))
1342 continue;
1343
1344 if (IO_APIC_IRQ(irq)) {
1345 vector = assign_irq_vector(irq);
1346 entry.vector = vector;
1347 ioapic_register_intr(irq, vector, IOAPIC_AUTO,
1348 apic > 0);
1349
1350 if (!apic && (irq < 16))
1351 disable_8259A_irq(irq);
1352 }
1353 spin_lock_irqsave(&ioapic_lock, flags);
1354 __ioapic_write_entry(apic, pin, entry);
1355 spin_unlock_irqrestore(&ioapic_lock, flags);
1356 }
1357 }
1358
1359 if (!first_notcon)
1360 apic_printk(APIC_VERBOSE, " not connected.\n");
1361 }
1362
1363 /*
1364 * Set up the 8259A-master output pin:
1365 */
1366 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1367 {
1368 struct IO_APIC_route_entry entry;
1369
1370 memset(&entry,0,sizeof(entry));
1371
1372 disable_8259A_irq(0);
1373
1374 /* mask LVT0 */
1375 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1376
1377 /*
1378 * We use logical delivery to get the timer IRQ
1379 * to the first CPU.
1380 */
1381 entry.dest_mode = INT_DEST_MODE;
1382 entry.mask = 0; /* unmask IRQ now */
1383 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1384 entry.delivery_mode = INT_DELIVERY_MODE;
1385 entry.polarity = 0;
1386 entry.trigger = 0;
1387 entry.vector = vector;
1388
1389 /*
1390 * The timer IRQ doesn't have to know that behind the
1391 * scene we have a 8259A-master in AEOI mode ...
1392 */
1393 irq_desc[0].chip = &ioapic_chip;
1394 set_irq_handler(0, handle_edge_irq);
1395
1396 /*
1397 * Add it to the IO-APIC irq-routing table:
1398 */
1399 ioapic_write_entry(apic, pin, entry);
1400
1401 enable_8259A_irq(0);
1402 }
1403
1404 void __init print_IO_APIC(void)
1405 {
1406 int apic, i;
1407 union IO_APIC_reg_00 reg_00;
1408 union IO_APIC_reg_01 reg_01;
1409 union IO_APIC_reg_02 reg_02;
1410 union IO_APIC_reg_03 reg_03;
1411 unsigned long flags;
1412
1413 if (apic_verbosity == APIC_QUIET)
1414 return;
1415
1416 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1417 for (i = 0; i < nr_ioapics; i++)
1418 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1419 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1420
1421 /*
1422 * We are a bit conservative about what we expect. We have to
1423 * know about every hardware change ASAP.
1424 */
1425 printk(KERN_INFO "testing the IO APIC.......................\n");
1426
1427 for (apic = 0; apic < nr_ioapics; apic++) {
1428
1429 spin_lock_irqsave(&ioapic_lock, flags);
1430 reg_00.raw = io_apic_read(apic, 0);
1431 reg_01.raw = io_apic_read(apic, 1);
1432 if (reg_01.bits.version >= 0x10)
1433 reg_02.raw = io_apic_read(apic, 2);
1434 if (reg_01.bits.version >= 0x20)
1435 reg_03.raw = io_apic_read(apic, 3);
1436 spin_unlock_irqrestore(&ioapic_lock, flags);
1437
1438 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1439 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1440 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1441 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1442 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1443
1444 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1445 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1446
1447 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1448 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1449
1450 /*
1451 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1452 * but the value of reg_02 is read as the previous read register
1453 * value, so ignore it if reg_02 == reg_01.
1454 */
1455 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1456 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1457 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1458 }
1459
1460 /*
1461 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1462 * or reg_03, but the value of reg_0[23] is read as the previous read
1463 * register value, so ignore it if reg_03 == reg_0[12].
1464 */
1465 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1466 reg_03.raw != reg_01.raw) {
1467 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1468 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1469 }
1470
1471 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1472
1473 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1474 " Stat Dest Deli Vect: \n");
1475
1476 for (i = 0; i <= reg_01.bits.entries; i++) {
1477 struct IO_APIC_route_entry entry;
1478
1479 entry = ioapic_read_entry(apic, i);
1480
1481 printk(KERN_DEBUG " %02x %03X %02X ",
1482 i,
1483 entry.dest.logical.logical_dest,
1484 entry.dest.physical.physical_dest
1485 );
1486
1487 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1488 entry.mask,
1489 entry.trigger,
1490 entry.irr,
1491 entry.polarity,
1492 entry.delivery_status,
1493 entry.dest_mode,
1494 entry.delivery_mode,
1495 entry.vector
1496 );
1497 }
1498 }
1499 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1500 for (i = 0; i < NR_IRQS; i++) {
1501 struct irq_pin_list *entry = irq_2_pin + i;
1502 if (entry->pin < 0)
1503 continue;
1504 printk(KERN_DEBUG "IRQ%d ", i);
1505 for (;;) {
1506 printk("-> %d:%d", entry->apic, entry->pin);
1507 if (!entry->next)
1508 break;
1509 entry = irq_2_pin + entry->next;
1510 }
1511 printk("\n");
1512 }
1513
1514 printk(KERN_INFO ".................................... done.\n");
1515
1516 return;
1517 }
1518
1519 #if 1
1520
1521 static void print_APIC_bitfield (int base)
1522 {
1523 unsigned int v;
1524 int i, j;
1525
1526 if (apic_verbosity == APIC_QUIET)
1527 return;
1528
1529 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1530 for (i = 0; i < 8; i++) {
1531 v = apic_read(base + i*0x10);
1532 for (j = 0; j < 32; j++) {
1533 if (v & (1<<j))
1534 printk("1");
1535 else
1536 printk("");
1537 }
1538 printk("\n");
1539 }
1540 }
1541
1542 void /*__init*/ print_local_APIC(void * dummy)
1543 {
1544 unsigned int v, ver, maxlvt;
1545
1546 if (apic_verbosity == APIC_QUIET)
1547 return;
1548
1549 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1550 smp_processor_id(), hard_smp_processor_id());
1551 v = apic_read(APIC_ID);
1552 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1553 v = apic_read(APIC_LVR);
1554 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1555 ver = GET_APIC_VERSION(v);
1556 maxlvt = lapic_get_maxlvt();
1557
1558 v = apic_read(APIC_TASKPRI);
1559 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1560
1561 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1562 v = apic_read(APIC_ARBPRI);
1563 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1564 v & APIC_ARBPRI_MASK);
1565 v = apic_read(APIC_PROCPRI);
1566 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1567 }
1568
1569 v = apic_read(APIC_EOI);
1570 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1571 v = apic_read(APIC_RRR);
1572 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1573 v = apic_read(APIC_LDR);
1574 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1575 v = apic_read(APIC_DFR);
1576 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1577 v = apic_read(APIC_SPIV);
1578 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1579
1580 printk(KERN_DEBUG "... APIC ISR field:\n");
1581 print_APIC_bitfield(APIC_ISR);
1582 printk(KERN_DEBUG "... APIC TMR field:\n");
1583 print_APIC_bitfield(APIC_TMR);
1584 printk(KERN_DEBUG "... APIC IRR field:\n");
1585 print_APIC_bitfield(APIC_IRR);
1586
1587 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1588 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1589 apic_write(APIC_ESR, 0);
1590 v = apic_read(APIC_ESR);
1591 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1592 }
1593
1594 v = apic_read(APIC_ICR);
1595 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1596 v = apic_read(APIC_ICR2);
1597 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1598
1599 v = apic_read(APIC_LVTT);
1600 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1601
1602 if (maxlvt > 3) { /* PC is LVT#4. */
1603 v = apic_read(APIC_LVTPC);
1604 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1605 }
1606 v = apic_read(APIC_LVT0);
1607 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1608 v = apic_read(APIC_LVT1);
1609 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1610
1611 if (maxlvt > 2) { /* ERR is LVT#3. */
1612 v = apic_read(APIC_LVTERR);
1613 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1614 }
1615
1616 v = apic_read(APIC_TMICT);
1617 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1618 v = apic_read(APIC_TMCCT);
1619 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1620 v = apic_read(APIC_TDCR);
1621 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1622 printk("\n");
1623 }
1624
1625 void print_all_local_APICs (void)
1626 {
1627 on_each_cpu(print_local_APIC, NULL, 1, 1);
1628 }
1629
1630 void /*__init*/ print_PIC(void)
1631 {
1632 unsigned int v;
1633 unsigned long flags;
1634
1635 if (apic_verbosity == APIC_QUIET)
1636 return;
1637
1638 printk(KERN_DEBUG "\nprinting PIC contents\n");
1639
1640 spin_lock_irqsave(&i8259A_lock, flags);
1641
1642 v = inb(0xa1) << 8 | inb(0x21);
1643 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1644
1645 v = inb(0xa0) << 8 | inb(0x20);
1646 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1647
1648 outb(0x0b,0xa0);
1649 outb(0x0b,0x20);
1650 v = inb(0xa0) << 8 | inb(0x20);
1651 outb(0x0a,0xa0);
1652 outb(0x0a,0x20);
1653
1654 spin_unlock_irqrestore(&i8259A_lock, flags);
1655
1656 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1657
1658 v = inb(0x4d1) << 8 | inb(0x4d0);
1659 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1660 }
1661
1662 #endif /* 0 */
1663
1664 static void __init enable_IO_APIC(void)
1665 {
1666 union IO_APIC_reg_01 reg_01;
1667 int i8259_apic, i8259_pin;
1668 int i, apic;
1669 unsigned long flags;
1670
1671 for (i = 0; i < PIN_MAP_SIZE; i++) {
1672 irq_2_pin[i].pin = -1;
1673 irq_2_pin[i].next = 0;
1674 }
1675 if (!pirqs_enabled)
1676 for (i = 0; i < MAX_PIRQS; i++)
1677 pirq_entries[i] = -1;
1678
1679 /*
1680 * The number of IO-APIC IRQ registers (== #pins):
1681 */
1682 for (apic = 0; apic < nr_ioapics; apic++) {
1683 spin_lock_irqsave(&ioapic_lock, flags);
1684 reg_01.raw = io_apic_read(apic, 1);
1685 spin_unlock_irqrestore(&ioapic_lock, flags);
1686 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1687 }
1688 for(apic = 0; apic < nr_ioapics; apic++) {
1689 int pin;
1690 /* See if any of the pins is in ExtINT mode */
1691 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1692 struct IO_APIC_route_entry entry;
1693 entry = ioapic_read_entry(apic, pin);
1694
1695
1696 /* If the interrupt line is enabled and in ExtInt mode
1697 * I have found the pin where the i8259 is connected.
1698 */
1699 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1700 ioapic_i8259.apic = apic;
1701 ioapic_i8259.pin = pin;
1702 goto found_i8259;
1703 }
1704 }
1705 }
1706 found_i8259:
1707 /* Look to see what if the MP table has reported the ExtINT */
1708 /* If we could not find the appropriate pin by looking at the ioapic
1709 * the i8259 probably is not connected the ioapic but give the
1710 * mptable a chance anyway.
1711 */
1712 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1713 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1714 /* Trust the MP table if nothing is setup in the hardware */
1715 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1716 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1717 ioapic_i8259.pin = i8259_pin;
1718 ioapic_i8259.apic = i8259_apic;
1719 }
1720 /* Complain if the MP table and the hardware disagree */
1721 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1722 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1723 {
1724 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1725 }
1726
1727 /*
1728 * Do not trust the IO-APIC being empty at bootup
1729 */
1730 clear_IO_APIC();
1731 }
1732
1733 /*
1734 * Not an __init, needed by the reboot code
1735 */
1736 void disable_IO_APIC(void)
1737 {
1738 /*
1739 * Clear the IO-APIC before rebooting:
1740 */
1741 clear_IO_APIC();
1742
1743 /*
1744 * If the i8259 is routed through an IOAPIC
1745 * Put that IOAPIC in virtual wire mode
1746 * so legacy interrupts can be delivered.
1747 */
1748 if (ioapic_i8259.pin != -1) {
1749 struct IO_APIC_route_entry entry;
1750
1751 memset(&entry, 0, sizeof(entry));
1752 entry.mask = 0; /* Enabled */
1753 entry.trigger = 0; /* Edge */
1754 entry.irr = 0;
1755 entry.polarity = 0; /* High */
1756 entry.delivery_status = 0;
1757 entry.dest_mode = 0; /* Physical */
1758 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1759 entry.vector = 0;
1760 entry.dest.physical.physical_dest =
1761 GET_APIC_ID(apic_read(APIC_ID));
1762
1763 /*
1764 * Add it to the IO-APIC irq-routing table:
1765 */
1766 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1767 }
1768 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1769 }
1770
1771 /*
1772 * function to set the IO-APIC physical IDs based on the
1773 * values stored in the MPC table.
1774 *
1775 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1776 */
1777
1778 #ifndef CONFIG_X86_NUMAQ
1779 static void __init setup_ioapic_ids_from_mpc(void)
1780 {
1781 union IO_APIC_reg_00 reg_00;
1782 physid_mask_t phys_id_present_map;
1783 int apic;
1784 int i;
1785 unsigned char old_id;
1786 unsigned long flags;
1787
1788 /*
1789 * Don't check I/O APIC IDs for xAPIC systems. They have
1790 * no meaning without the serial APIC bus.
1791 */
1792 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1793 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1794 return;
1795 /*
1796 * This is broken; anything with a real cpu count has to
1797 * circumvent this idiocy regardless.
1798 */
1799 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1800
1801 /*
1802 * Set the IOAPIC ID to the value stored in the MPC table.
1803 */
1804 for (apic = 0; apic < nr_ioapics; apic++) {
1805
1806 /* Read the register 0 value */
1807 spin_lock_irqsave(&ioapic_lock, flags);
1808 reg_00.raw = io_apic_read(apic, 0);
1809 spin_unlock_irqrestore(&ioapic_lock, flags);
1810
1811 old_id = mp_ioapics[apic].mpc_apicid;
1812
1813 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1814 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1815 apic, mp_ioapics[apic].mpc_apicid);
1816 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1817 reg_00.bits.ID);
1818 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1819 }
1820
1821 /*
1822 * Sanity check, is the ID really free? Every APIC in a
1823 * system must have a unique ID or we get lots of nice
1824 * 'stuck on smp_invalidate_needed IPI wait' messages.
1825 */
1826 if (check_apicid_used(phys_id_present_map,
1827 mp_ioapics[apic].mpc_apicid)) {
1828 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1829 apic, mp_ioapics[apic].mpc_apicid);
1830 for (i = 0; i < get_physical_broadcast(); i++)
1831 if (!physid_isset(i, phys_id_present_map))
1832 break;
1833 if (i >= get_physical_broadcast())
1834 panic("Max APIC ID exceeded!\n");
1835 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1836 i);
1837 physid_set(i, phys_id_present_map);
1838 mp_ioapics[apic].mpc_apicid = i;
1839 } else {
1840 physid_mask_t tmp;
1841 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1842 apic_printk(APIC_VERBOSE, "Setting %d in the "
1843 "phys_id_present_map\n",
1844 mp_ioapics[apic].mpc_apicid);
1845 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1846 }
1847
1848
1849 /*
1850 * We need to adjust the IRQ routing table
1851 * if the ID changed.
1852 */
1853 if (old_id != mp_ioapics[apic].mpc_apicid)
1854 for (i = 0; i < mp_irq_entries; i++)
1855 if (mp_irqs[i].mpc_dstapic == old_id)
1856 mp_irqs[i].mpc_dstapic
1857 = mp_ioapics[apic].mpc_apicid;
1858
1859 /*
1860 * Read the right value from the MPC table and
1861 * write it into the ID register.
1862 */
1863 apic_printk(APIC_VERBOSE, KERN_INFO
1864 "...changing IO-APIC physical APIC ID to %d ...",
1865 mp_ioapics[apic].mpc_apicid);
1866
1867 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1868 spin_lock_irqsave(&ioapic_lock, flags);
1869 io_apic_write(apic, 0, reg_00.raw);
1870 spin_unlock_irqrestore(&ioapic_lock, flags);
1871
1872 /*
1873 * Sanity check
1874 */
1875 spin_lock_irqsave(&ioapic_lock, flags);
1876 reg_00.raw = io_apic_read(apic, 0);
1877 spin_unlock_irqrestore(&ioapic_lock, flags);
1878 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1879 printk("could not set ID!\n");
1880 else
1881 apic_printk(APIC_VERBOSE, " ok.\n");
1882 }
1883 }
1884 #else
1885 static void __init setup_ioapic_ids_from_mpc(void) { }
1886 #endif
1887
1888 int no_timer_check __initdata;
1889
1890 static int __init notimercheck(char *s)
1891 {
1892 no_timer_check = 1;
1893 return 1;
1894 }
1895 __setup("no_timer_check", notimercheck);
1896
1897 /*
1898 * There is a nasty bug in some older SMP boards, their mptable lies
1899 * about the timer IRQ. We do the following to work around the situation:
1900 *
1901 * - timer IRQ defaults to IO-APIC IRQ
1902 * - if this function detects that timer IRQs are defunct, then we fall
1903 * back to ISA timer IRQs
1904 */
1905 static int __init timer_irq_works(void)
1906 {
1907 unsigned long t1 = jiffies;
1908 unsigned long flags;
1909
1910 if (no_timer_check)
1911 return 1;
1912
1913 local_save_flags(flags);
1914 local_irq_enable();
1915 /* Let ten ticks pass... */
1916 mdelay((10 * 1000) / HZ);
1917 local_irq_restore(flags);
1918
1919 /*
1920 * Expect a few ticks at least, to be sure some possible
1921 * glue logic does not lock up after one or two first
1922 * ticks in a non-ExtINT mode. Also the local APIC
1923 * might have cached one ExtINT interrupt. Finally, at
1924 * least one tick may be lost due to delays.
1925 */
1926 if (time_after(jiffies, t1 + 4) &&
1927 time_before(jiffies, t1 + 16))
1928 return 1;
1929
1930 return 0;
1931 }
1932
1933 /*
1934 * In the SMP+IOAPIC case it might happen that there are an unspecified
1935 * number of pending IRQ events unhandled. These cases are very rare,
1936 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1937 * better to do it this way as thus we do not have to be aware of
1938 * 'pending' interrupts in the IRQ path, except at this point.
1939 */
1940 /*
1941 * Edge triggered needs to resend any interrupt
1942 * that was delayed but this is now handled in the device
1943 * independent code.
1944 */
1945
1946 /*
1947 * Startup quirk:
1948 *
1949 * Starting up a edge-triggered IO-APIC interrupt is
1950 * nasty - we need to make sure that we get the edge.
1951 * If it is already asserted for some reason, we need
1952 * return 1 to indicate that is was pending.
1953 *
1954 * This is not complete - we should be able to fake
1955 * an edge even if it isn't on the 8259A...
1956 *
1957 * (We do this for level-triggered IRQs too - it cannot hurt.)
1958 */
1959 static unsigned int startup_ioapic_irq(unsigned int irq)
1960 {
1961 int was_pending = 0;
1962 unsigned long flags;
1963
1964 spin_lock_irqsave(&ioapic_lock, flags);
1965 if (irq < 16) {
1966 disable_8259A_irq(irq);
1967 if (i8259A_irq_pending(irq))
1968 was_pending = 1;
1969 }
1970 __unmask_IO_APIC_irq(irq);
1971 spin_unlock_irqrestore(&ioapic_lock, flags);
1972
1973 return was_pending;
1974 }
1975
1976 static void ack_ioapic_irq(unsigned int irq)
1977 {
1978 move_native_irq(irq);
1979 ack_APIC_irq();
1980 }
1981
1982 static void ack_ioapic_quirk_irq(unsigned int irq)
1983 {
1984 unsigned long v;
1985 int i;
1986
1987 move_native_irq(irq);
1988 /*
1989 * It appears there is an erratum which affects at least version 0x11
1990 * of I/O APIC (that's the 82093AA and cores integrated into various
1991 * chipsets). Under certain conditions a level-triggered interrupt is
1992 * erroneously delivered as edge-triggered one but the respective IRR
1993 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1994 * message but it will never arrive and further interrupts are blocked
1995 * from the source. The exact reason is so far unknown, but the
1996 * phenomenon was observed when two consecutive interrupt requests
1997 * from a given source get delivered to the same CPU and the source is
1998 * temporarily disabled in between.
1999 *
2000 * A workaround is to simulate an EOI message manually. We achieve it
2001 * by setting the trigger mode to edge and then to level when the edge
2002 * trigger mode gets detected in the TMR of a local APIC for a
2003 * level-triggered interrupt. We mask the source for the time of the
2004 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2005 * The idea is from Manfred Spraul. --macro
2006 */
2007 i = irq_vector[irq];
2008
2009 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2010
2011 ack_APIC_irq();
2012
2013 if (!(v & (1 << (i & 0x1f)))) {
2014 atomic_inc(&irq_mis_count);
2015 spin_lock(&ioapic_lock);
2016 /* mask = 1, trigger = 0 */
2017 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
2018 /* mask = 0, trigger = 1 */
2019 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
2020 spin_unlock(&ioapic_lock);
2021 }
2022 }
2023
2024 static int ioapic_retrigger_irq(unsigned int irq)
2025 {
2026 send_IPI_self(irq_vector[irq]);
2027
2028 return 1;
2029 }
2030
2031 static struct irq_chip ioapic_chip __read_mostly = {
2032 .name = "IO-APIC",
2033 .startup = startup_ioapic_irq,
2034 .mask = mask_IO_APIC_irq,
2035 .unmask = unmask_IO_APIC_irq,
2036 .ack = ack_ioapic_irq,
2037 .eoi = ack_ioapic_quirk_irq,
2038 #ifdef CONFIG_SMP
2039 .set_affinity = set_ioapic_affinity_irq,
2040 #endif
2041 .retrigger = ioapic_retrigger_irq,
2042 };
2043
2044 static struct irq_chip pcix_ioapic_chip __read_mostly = {
2045 .name = "IO-APIC",
2046 .startup = startup_ioapic_irq,
2047 .mask = pcix_mask_IO_APIC_irq,
2048 .unmask = pcix_unmask_IO_APIC_irq,
2049 .ack = ack_ioapic_irq,
2050 .eoi = ack_ioapic_irq,
2051 #ifdef CONFIG_SMP
2052 .set_affinity = set_ioapic_affinity_irq,
2053 #endif
2054 .retrigger = ioapic_retrigger_irq,
2055 };
2056
2057 static inline void init_IO_APIC_traps(void)
2058 {
2059 int irq;
2060
2061 /*
2062 * NOTE! The local APIC isn't very good at handling
2063 * multiple interrupts at the same interrupt level.
2064 * As the interrupt level is determined by taking the
2065 * vector number and shifting that right by 4, we
2066 * want to spread these out a bit so that they don't
2067 * all fall in the same interrupt level.
2068 *
2069 * Also, we've got to be careful not to trash gate
2070 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2071 */
2072 for (irq = 0; irq < NR_IRQS ; irq++) {
2073 int tmp = irq;
2074 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2075 /*
2076 * Hmm.. We don't have an entry for this,
2077 * so default to an old-fashioned 8259
2078 * interrupt if we can..
2079 */
2080 if (irq < 16)
2081 make_8259A_irq(irq);
2082 else
2083 /* Strange. Oh, well.. */
2084 irq_desc[irq].chip = &no_irq_chip;
2085 }
2086 }
2087 }
2088
2089 /*
2090 * The local APIC irq-chip implementation:
2091 */
2092
2093 static void ack_apic(unsigned int irq)
2094 {
2095 ack_APIC_irq();
2096 }
2097
2098 static void mask_lapic_irq (unsigned int irq)
2099 {
2100 unsigned long v;
2101
2102 v = apic_read(APIC_LVT0);
2103 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2104 }
2105
2106 static void unmask_lapic_irq (unsigned int irq)
2107 {
2108 unsigned long v;
2109
2110 v = apic_read(APIC_LVT0);
2111 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2112 }
2113
2114 static struct irq_chip lapic_chip __read_mostly = {
2115 .name = "local-APIC-edge",
2116 .mask = mask_lapic_irq,
2117 .unmask = unmask_lapic_irq,
2118 .eoi = ack_apic,
2119 };
2120
2121 static void __init setup_nmi(void)
2122 {
2123 /*
2124 * Dirty trick to enable the NMI watchdog ...
2125 * We put the 8259A master into AEOI mode and
2126 * unmask on all local APICs LVT0 as NMI.
2127 *
2128 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2129 * is from Maciej W. Rozycki - so we do not have to EOI from
2130 * the NMI handler or the timer interrupt.
2131 */
2132 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2133
2134 enable_NMI_through_LVT0();
2135
2136 apic_printk(APIC_VERBOSE, " done.\n");
2137 }
2138
2139 /*
2140 * This looks a bit hackish but it's about the only one way of sending
2141 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2142 * not support the ExtINT mode, unfortunately. We need to send these
2143 * cycles as some i82489DX-based boards have glue logic that keeps the
2144 * 8259A interrupt line asserted until INTA. --macro
2145 */
2146 static inline void unlock_ExtINT_logic(void)
2147 {
2148 int apic, pin, i;
2149 struct IO_APIC_route_entry entry0, entry1;
2150 unsigned char save_control, save_freq_select;
2151
2152 pin = find_isa_irq_pin(8, mp_INT);
2153 if (pin == -1) {
2154 WARN_ON_ONCE(1);
2155 return;
2156 }
2157 apic = find_isa_irq_apic(8, mp_INT);
2158 if (apic == -1) {
2159 WARN_ON_ONCE(1);
2160 return;
2161 }
2162
2163 entry0 = ioapic_read_entry(apic, pin);
2164 clear_IO_APIC_pin(apic, pin);
2165
2166 memset(&entry1, 0, sizeof(entry1));
2167
2168 entry1.dest_mode = 0; /* physical delivery */
2169 entry1.mask = 0; /* unmask IRQ now */
2170 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2171 entry1.delivery_mode = dest_ExtINT;
2172 entry1.polarity = entry0.polarity;
2173 entry1.trigger = 0;
2174 entry1.vector = 0;
2175
2176 ioapic_write_entry(apic, pin, entry1);
2177
2178 save_control = CMOS_READ(RTC_CONTROL);
2179 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2180 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2181 RTC_FREQ_SELECT);
2182 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2183
2184 i = 100;
2185 while (i-- > 0) {
2186 mdelay(10);
2187 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2188 i -= 10;
2189 }
2190
2191 CMOS_WRITE(save_control, RTC_CONTROL);
2192 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2193 clear_IO_APIC_pin(apic, pin);
2194
2195 ioapic_write_entry(apic, pin, entry0);
2196 }
2197
2198 int timer_uses_ioapic_pin_0;
2199
2200 /*
2201 * This code may look a bit paranoid, but it's supposed to cooperate with
2202 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2203 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2204 * fanatically on his truly buggy board.
2205 */
2206 static inline void __init check_timer(void)
2207 {
2208 int apic1, pin1, apic2, pin2;
2209 int vector;
2210 unsigned long flags;
2211
2212 local_irq_save(flags);
2213
2214 /*
2215 * get/set the timer IRQ vector:
2216 */
2217 disable_8259A_irq(0);
2218 vector = assign_irq_vector(0);
2219 set_intr_gate(vector, interrupt[0]);
2220
2221 /*
2222 * Subtle, code in do_timer_interrupt() expects an AEOI
2223 * mode for the 8259A whenever interrupts are routed
2224 * through I/O APICs. Also IRQ0 has to be enabled in
2225 * the 8259A which implies the virtual wire has to be
2226 * disabled in the local APIC.
2227 */
2228 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2229 init_8259A(1);
2230 timer_ack = 1;
2231 if (timer_over_8254 > 0)
2232 enable_8259A_irq(0);
2233
2234 pin1 = find_isa_irq_pin(0, mp_INT);
2235 apic1 = find_isa_irq_apic(0, mp_INT);
2236 pin2 = ioapic_i8259.pin;
2237 apic2 = ioapic_i8259.apic;
2238
2239 if (pin1 == 0)
2240 timer_uses_ioapic_pin_0 = 1;
2241
2242 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2243 vector, apic1, pin1, apic2, pin2);
2244
2245 if (pin1 != -1) {
2246 /*
2247 * Ok, does IRQ0 through the IOAPIC work?
2248 */
2249 unmask_IO_APIC_irq(0);
2250 if (timer_irq_works()) {
2251 if (nmi_watchdog == NMI_IO_APIC) {
2252 disable_8259A_irq(0);
2253 setup_nmi();
2254 enable_8259A_irq(0);
2255 }
2256 if (disable_timer_pin_1 > 0)
2257 clear_IO_APIC_pin(0, pin1);
2258 goto out;
2259 }
2260 clear_IO_APIC_pin(apic1, pin1);
2261 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2262 "IO-APIC\n");
2263 }
2264
2265 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2266 if (pin2 != -1) {
2267 printk("\n..... (found pin %d) ...", pin2);
2268 /*
2269 * legacy devices should be connected to IO APIC #0
2270 */
2271 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2272 if (timer_irq_works()) {
2273 printk("works.\n");
2274 if (pin1 != -1)
2275 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2276 else
2277 add_pin_to_irq(0, apic2, pin2);
2278 if (nmi_watchdog == NMI_IO_APIC) {
2279 setup_nmi();
2280 }
2281 goto out;
2282 }
2283 /*
2284 * Cleanup, just in case ...
2285 */
2286 clear_IO_APIC_pin(apic2, pin2);
2287 }
2288 printk(" failed.\n");
2289
2290 if (nmi_watchdog == NMI_IO_APIC) {
2291 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2292 nmi_watchdog = 0;
2293 }
2294
2295 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2296
2297 disable_8259A_irq(0);
2298 set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2299 "fasteoi");
2300 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2301 enable_8259A_irq(0);
2302
2303 if (timer_irq_works()) {
2304 printk(" works.\n");
2305 goto out;
2306 }
2307 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2308 printk(" failed.\n");
2309
2310 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2311
2312 timer_ack = 0;
2313 init_8259A(0);
2314 make_8259A_irq(0);
2315 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2316
2317 unlock_ExtINT_logic();
2318
2319 if (timer_irq_works()) {
2320 printk(" works.\n");
2321 goto out;
2322 }
2323 printk(" failed :(.\n");
2324 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2325 "report. Then try booting with the 'noapic' option");
2326 out:
2327 local_irq_restore(flags);
2328 }
2329
2330 /*
2331 *
2332 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2333 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2334 * Linux doesn't really care, as it's not actually used
2335 * for any interrupt handling anyway.
2336 */
2337 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2338
2339 void __init setup_IO_APIC(void)
2340 {
2341 int i;
2342
2343 /* Reserve all the system vectors. */
2344 for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
2345 set_bit(i, used_vectors);
2346
2347 enable_IO_APIC();
2348
2349 if (acpi_ioapic)
2350 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2351 else
2352 io_apic_irqs = ~PIC_IRQS;
2353
2354 printk("ENABLING IO-APIC IRQs\n");
2355
2356 /*
2357 * Set up IO-APIC IRQ routing.
2358 */
2359 if (!acpi_ioapic)
2360 setup_ioapic_ids_from_mpc();
2361 sync_Arb_IDs();
2362 setup_IO_APIC_irqs();
2363 init_IO_APIC_traps();
2364 check_timer();
2365 if (!acpi_ioapic)
2366 print_IO_APIC();
2367 }
2368
2369 static int __init setup_disable_8254_timer(char *s)
2370 {
2371 timer_over_8254 = -1;
2372 return 1;
2373 }
2374 static int __init setup_enable_8254_timer(char *s)
2375 {
2376 timer_over_8254 = 2;
2377 return 1;
2378 }
2379
2380 __setup("disable_8254_timer", setup_disable_8254_timer);
2381 __setup("enable_8254_timer", setup_enable_8254_timer);
2382
2383 /*
2384 * Called after all the initialization is done. If we didnt find any
2385 * APIC bugs then we can allow the modify fast path
2386 */
2387
2388 static int __init io_apic_bug_finalize(void)
2389 {
2390 if(sis_apic_bug == -1)
2391 sis_apic_bug = 0;
2392 return 0;
2393 }
2394
2395 late_initcall(io_apic_bug_finalize);
2396
2397 struct sysfs_ioapic_data {
2398 struct sys_device dev;
2399 struct IO_APIC_route_entry entry[0];
2400 };
2401 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2402
2403 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2404 {
2405 struct IO_APIC_route_entry *entry;
2406 struct sysfs_ioapic_data *data;
2407 int i;
2408
2409 data = container_of(dev, struct sysfs_ioapic_data, dev);
2410 entry = data->entry;
2411 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2412 entry[i] = ioapic_read_entry(dev->id, i);
2413
2414 return 0;
2415 }
2416
2417 static int ioapic_resume(struct sys_device *dev)
2418 {
2419 struct IO_APIC_route_entry *entry;
2420 struct sysfs_ioapic_data *data;
2421 unsigned long flags;
2422 union IO_APIC_reg_00 reg_00;
2423 int i;
2424
2425 data = container_of(dev, struct sysfs_ioapic_data, dev);
2426 entry = data->entry;
2427
2428 spin_lock_irqsave(&ioapic_lock, flags);
2429 reg_00.raw = io_apic_read(dev->id, 0);
2430 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2431 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2432 io_apic_write(dev->id, 0, reg_00.raw);
2433 }
2434 spin_unlock_irqrestore(&ioapic_lock, flags);
2435 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2436 ioapic_write_entry(dev->id, i, entry[i]);
2437
2438 return 0;
2439 }
2440
2441 static struct sysdev_class ioapic_sysdev_class = {
2442 .name = "ioapic",
2443 .suspend = ioapic_suspend,
2444 .resume = ioapic_resume,
2445 };
2446
2447 static int __init ioapic_init_sysfs(void)
2448 {
2449 struct sys_device * dev;
2450 int i, size, error = 0;
2451
2452 error = sysdev_class_register(&ioapic_sysdev_class);
2453 if (error)
2454 return error;
2455
2456 for (i = 0; i < nr_ioapics; i++ ) {
2457 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2458 * sizeof(struct IO_APIC_route_entry);
2459 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2460 if (!mp_ioapic_data[i]) {
2461 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2462 continue;
2463 }
2464 memset(mp_ioapic_data[i], 0, size);
2465 dev = &mp_ioapic_data[i]->dev;
2466 dev->id = i;
2467 dev->cls = &ioapic_sysdev_class;
2468 error = sysdev_register(dev);
2469 if (error) {
2470 kfree(mp_ioapic_data[i]);
2471 mp_ioapic_data[i] = NULL;
2472 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2473 continue;
2474 }
2475 }
2476
2477 return 0;
2478 }
2479
2480 device_initcall(ioapic_init_sysfs);
2481
2482 /*
2483 * Dynamic irq allocate and deallocation
2484 */
2485 int create_irq(void)
2486 {
2487 /* Allocate an unused irq */
2488 int irq, new, vector = 0;
2489 unsigned long flags;
2490
2491 irq = -ENOSPC;
2492 spin_lock_irqsave(&vector_lock, flags);
2493 for (new = (NR_IRQS - 1); new >= 0; new--) {
2494 if (platform_legacy_irq(new))
2495 continue;
2496 if (irq_vector[new] != 0)
2497 continue;
2498 vector = __assign_irq_vector(new);
2499 if (likely(vector > 0))
2500 irq = new;
2501 break;
2502 }
2503 spin_unlock_irqrestore(&vector_lock, flags);
2504
2505 if (irq >= 0) {
2506 set_intr_gate(vector, interrupt[irq]);
2507 dynamic_irq_init(irq);
2508 }
2509 return irq;
2510 }
2511
2512 void destroy_irq(unsigned int irq)
2513 {
2514 unsigned long flags;
2515
2516 dynamic_irq_cleanup(irq);
2517
2518 spin_lock_irqsave(&vector_lock, flags);
2519 clear_bit(irq_vector[irq], used_vectors);
2520 irq_vector[irq] = 0;
2521 spin_unlock_irqrestore(&vector_lock, flags);
2522 }
2523
2524 /*
2525 * MSI message composition
2526 */
2527 #ifdef CONFIG_PCI_MSI
2528 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2529 {
2530 int vector;
2531 unsigned dest;
2532
2533 vector = assign_irq_vector(irq);
2534 if (vector >= 0) {
2535 dest = cpu_mask_to_apicid(TARGET_CPUS);
2536
2537 msg->address_hi = MSI_ADDR_BASE_HI;
2538 msg->address_lo =
2539 MSI_ADDR_BASE_LO |
2540 ((INT_DEST_MODE == 0) ?
2541 MSI_ADDR_DEST_MODE_PHYSICAL:
2542 MSI_ADDR_DEST_MODE_LOGICAL) |
2543 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2544 MSI_ADDR_REDIRECTION_CPU:
2545 MSI_ADDR_REDIRECTION_LOWPRI) |
2546 MSI_ADDR_DEST_ID(dest);
2547
2548 msg->data =
2549 MSI_DATA_TRIGGER_EDGE |
2550 MSI_DATA_LEVEL_ASSERT |
2551 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2552 MSI_DATA_DELIVERY_FIXED:
2553 MSI_DATA_DELIVERY_LOWPRI) |
2554 MSI_DATA_VECTOR(vector);
2555 }
2556 return vector;
2557 }
2558
2559 #ifdef CONFIG_SMP
2560 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2561 {
2562 struct msi_msg msg;
2563 unsigned int dest;
2564 cpumask_t tmp;
2565 int vector;
2566
2567 cpus_and(tmp, mask, cpu_online_map);
2568 if (cpus_empty(tmp))
2569 tmp = TARGET_CPUS;
2570
2571 vector = assign_irq_vector(irq);
2572 if (vector < 0)
2573 return;
2574
2575 dest = cpu_mask_to_apicid(mask);
2576
2577 read_msi_msg(irq, &msg);
2578
2579 msg.data &= ~MSI_DATA_VECTOR_MASK;
2580 msg.data |= MSI_DATA_VECTOR(vector);
2581 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2582 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2583
2584 write_msi_msg(irq, &msg);
2585 irq_desc[irq].affinity = mask;
2586 }
2587 #endif /* CONFIG_SMP */
2588
2589 /*
2590 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2591 * which implement the MSI or MSI-X Capability Structure.
2592 */
2593 static struct irq_chip msi_chip = {
2594 .name = "PCI-MSI",
2595 .unmask = unmask_msi_irq,
2596 .mask = mask_msi_irq,
2597 .ack = ack_ioapic_irq,
2598 #ifdef CONFIG_SMP
2599 .set_affinity = set_msi_irq_affinity,
2600 #endif
2601 .retrigger = ioapic_retrigger_irq,
2602 };
2603
2604 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2605 {
2606 struct msi_msg msg;
2607 int irq, ret;
2608 irq = create_irq();
2609 if (irq < 0)
2610 return irq;
2611
2612 ret = msi_compose_msg(dev, irq, &msg);
2613 if (ret < 0) {
2614 destroy_irq(irq);
2615 return ret;
2616 }
2617
2618 set_irq_msi(irq, desc);
2619 write_msi_msg(irq, &msg);
2620
2621 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2622 "edge");
2623
2624 return 0;
2625 }
2626
2627 void arch_teardown_msi_irq(unsigned int irq)
2628 {
2629 destroy_irq(irq);
2630 }
2631
2632 #endif /* CONFIG_PCI_MSI */
2633
2634 /*
2635 * Hypertransport interrupt support
2636 */
2637 #ifdef CONFIG_HT_IRQ
2638
2639 #ifdef CONFIG_SMP
2640
2641 static void target_ht_irq(unsigned int irq, unsigned int dest)
2642 {
2643 struct ht_irq_msg msg;
2644 fetch_ht_irq_msg(irq, &msg);
2645
2646 msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2647 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2648
2649 msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2650 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2651
2652 write_ht_irq_msg(irq, &msg);
2653 }
2654
2655 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2656 {
2657 unsigned int dest;
2658 cpumask_t tmp;
2659
2660 cpus_and(tmp, mask, cpu_online_map);
2661 if (cpus_empty(tmp))
2662 tmp = TARGET_CPUS;
2663
2664 cpus_and(mask, tmp, CPU_MASK_ALL);
2665
2666 dest = cpu_mask_to_apicid(mask);
2667
2668 target_ht_irq(irq, dest);
2669 irq_desc[irq].affinity = mask;
2670 }
2671 #endif
2672
2673 static struct irq_chip ht_irq_chip = {
2674 .name = "PCI-HT",
2675 .mask = mask_ht_irq,
2676 .unmask = unmask_ht_irq,
2677 .ack = ack_ioapic_irq,
2678 #ifdef CONFIG_SMP
2679 .set_affinity = set_ht_irq_affinity,
2680 #endif
2681 .retrigger = ioapic_retrigger_irq,
2682 };
2683
2684 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2685 {
2686 int vector;
2687
2688 vector = assign_irq_vector(irq);
2689 if (vector >= 0) {
2690 struct ht_irq_msg msg;
2691 unsigned dest;
2692 cpumask_t tmp;
2693
2694 cpus_clear(tmp);
2695 cpu_set(vector >> 8, tmp);
2696 dest = cpu_mask_to_apicid(tmp);
2697
2698 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2699
2700 msg.address_lo =
2701 HT_IRQ_LOW_BASE |
2702 HT_IRQ_LOW_DEST_ID(dest) |
2703 HT_IRQ_LOW_VECTOR(vector) |
2704 ((INT_DEST_MODE == 0) ?
2705 HT_IRQ_LOW_DM_PHYSICAL :
2706 HT_IRQ_LOW_DM_LOGICAL) |
2707 HT_IRQ_LOW_RQEOI_EDGE |
2708 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2709 HT_IRQ_LOW_MT_FIXED :
2710 HT_IRQ_LOW_MT_ARBITRATED) |
2711 HT_IRQ_LOW_IRQ_MASKED;
2712
2713 write_ht_irq_msg(irq, &msg);
2714
2715 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2716 handle_edge_irq, "edge");
2717 }
2718 return vector;
2719 }
2720 #endif /* CONFIG_HT_IRQ */
2721
2722 /* --------------------------------------------------------------------------
2723 ACPI-based IOAPIC Configuration
2724 -------------------------------------------------------------------------- */
2725
2726 #ifdef CONFIG_ACPI
2727
2728 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2729 {
2730 union IO_APIC_reg_00 reg_00;
2731 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2732 physid_mask_t tmp;
2733 unsigned long flags;
2734 int i = 0;
2735
2736 /*
2737 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2738 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2739 * supports up to 16 on one shared APIC bus.
2740 *
2741 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2742 * advantage of new APIC bus architecture.
2743 */
2744
2745 if (physids_empty(apic_id_map))
2746 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2747
2748 spin_lock_irqsave(&ioapic_lock, flags);
2749 reg_00.raw = io_apic_read(ioapic, 0);
2750 spin_unlock_irqrestore(&ioapic_lock, flags);
2751
2752 if (apic_id >= get_physical_broadcast()) {
2753 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2754 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2755 apic_id = reg_00.bits.ID;
2756 }
2757
2758 /*
2759 * Every APIC in a system must have a unique ID or we get lots of nice
2760 * 'stuck on smp_invalidate_needed IPI wait' messages.
2761 */
2762 if (check_apicid_used(apic_id_map, apic_id)) {
2763
2764 for (i = 0; i < get_physical_broadcast(); i++) {
2765 if (!check_apicid_used(apic_id_map, i))
2766 break;
2767 }
2768
2769 if (i == get_physical_broadcast())
2770 panic("Max apic_id exceeded!\n");
2771
2772 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2773 "trying %d\n", ioapic, apic_id, i);
2774
2775 apic_id = i;
2776 }
2777
2778 tmp = apicid_to_cpu_present(apic_id);
2779 physids_or(apic_id_map, apic_id_map, tmp);
2780
2781 if (reg_00.bits.ID != apic_id) {
2782 reg_00.bits.ID = apic_id;
2783
2784 spin_lock_irqsave(&ioapic_lock, flags);
2785 io_apic_write(ioapic, 0, reg_00.raw);
2786 reg_00.raw = io_apic_read(ioapic, 0);
2787 spin_unlock_irqrestore(&ioapic_lock, flags);
2788
2789 /* Sanity check */
2790 if (reg_00.bits.ID != apic_id) {
2791 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2792 return -1;
2793 }
2794 }
2795
2796 apic_printk(APIC_VERBOSE, KERN_INFO
2797 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2798
2799 return apic_id;
2800 }
2801
2802
2803 int __init io_apic_get_version (int ioapic)
2804 {
2805 union IO_APIC_reg_01 reg_01;
2806 unsigned long flags;
2807
2808 spin_lock_irqsave(&ioapic_lock, flags);
2809 reg_01.raw = io_apic_read(ioapic, 1);
2810 spin_unlock_irqrestore(&ioapic_lock, flags);
2811
2812 return reg_01.bits.version;
2813 }
2814
2815
2816 int __init io_apic_get_redir_entries (int ioapic)
2817 {
2818 union IO_APIC_reg_01 reg_01;
2819 unsigned long flags;
2820
2821 spin_lock_irqsave(&ioapic_lock, flags);
2822 reg_01.raw = io_apic_read(ioapic, 1);
2823 spin_unlock_irqrestore(&ioapic_lock, flags);
2824
2825 return reg_01.bits.entries;
2826 }
2827
2828
2829 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2830 {
2831 struct IO_APIC_route_entry entry;
2832 unsigned long flags;
2833
2834 if (!IO_APIC_IRQ(irq)) {
2835 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2836 ioapic);
2837 return -EINVAL;
2838 }
2839
2840 /*
2841 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2842 * Note that we mask (disable) IRQs now -- these get enabled when the
2843 * corresponding device driver registers for this IRQ.
2844 */
2845
2846 memset(&entry,0,sizeof(entry));
2847
2848 entry.delivery_mode = INT_DELIVERY_MODE;
2849 entry.dest_mode = INT_DEST_MODE;
2850 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2851 entry.trigger = edge_level;
2852 entry.polarity = active_high_low;
2853 entry.mask = 1;
2854
2855 /*
2856 * IRQs < 16 are already in the irq_2_pin[] map
2857 */
2858 if (irq >= 16)
2859 add_pin_to_irq(irq, ioapic, pin);
2860
2861 entry.vector = assign_irq_vector(irq);
2862
2863 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2864 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2865 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2866 edge_level, active_high_low);
2867
2868 ioapic_register_intr(irq, entry.vector, edge_level, ioapic > 0);
2869
2870 if (!ioapic && (irq < 16))
2871 disable_8259A_irq(irq);
2872
2873 spin_lock_irqsave(&ioapic_lock, flags);
2874 __ioapic_write_entry(ioapic, pin, entry);
2875 spin_unlock_irqrestore(&ioapic_lock, flags);
2876
2877 return 0;
2878 }
2879
2880 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2881 {
2882 int i;
2883
2884 if (skip_ioapic_setup)
2885 return -1;
2886
2887 for (i = 0; i < mp_irq_entries; i++)
2888 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2889 mp_irqs[i].mpc_srcbusirq == bus_irq)
2890 break;
2891 if (i >= mp_irq_entries)
2892 return -1;
2893
2894 *trigger = irq_trigger(i);
2895 *polarity = irq_polarity(i);
2896 return 0;
2897 }
2898
2899 #endif /* CONFIG_ACPI */
2900
2901 static int __init parse_disable_timer_pin_1(char *arg)
2902 {
2903 disable_timer_pin_1 = 1;
2904 return 0;
2905 }
2906 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2907
2908 static int __init parse_enable_timer_pin_1(char *arg)
2909 {
2910 disable_timer_pin_1 = -1;
2911 return 0;
2912 }
2913 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2914
2915 static int __init parse_noapic(char *arg)
2916 {
2917 /* disable IO-APIC */
2918 disable_ioapic_setup();
2919 return 0;
2920 }
2921 early_param("noapic", parse_noapic);
2922
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