1 #include <linux/errno.h>
2 #include <linux/signal.h>
3 #include <linux/sched.h>
4 #include <linux/ioport.h>
5 #include <linux/interrupt.h>
6 #include <linux/slab.h>
7 #include <linux/random.h>
8 #include <linux/init.h>
9 #include <linux/kernel_stat.h>
10 #include <linux/sysdev.h>
11 #include <linux/bitops.h>
12
13 #include <asm/atomic.h>
14 #include <asm/system.h>
15 #include <asm/io.h>
16 #include <asm/timer.h>
17 #include <asm/pgtable.h>
18 #include <asm/delay.h>
19 #include <asm/desc.h>
20 #include <asm/apic.h>
21 #include <asm/arch_hooks.h>
22 #include <asm/i8259.h>
23
24 /*
25 * This is the 'legacy' 8259A Programmable Interrupt Controller,
26 * present in the majority of PC/AT boxes.
27 * plus some generic x86 specific things if generic specifics makes
28 * any sense at all.
29 */
30
31 static int i8259A_auto_eoi;
32 DEFINE_RAW_SPINLOCK(i8259A_lock);
33 static void mask_and_ack_8259A(unsigned int);
34
35 static struct irq_chip i8259A_chip = {
36 .name = "XT-PIC",
37 .mask = disable_8259A_irq,
38 .disable = disable_8259A_irq,
39 .unmask = enable_8259A_irq,
40 .mask_ack = mask_and_ack_8259A,
41 };
42
43 /*
44 * 8259A PIC functions to handle ISA devices:
45 */
46
47 /*
48 * This contains the irq mask for both 8259A irq controllers,
49 */
50 unsigned int cached_irq_mask = 0xffff;
51
52 /*
53 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
54 * boards the timer interrupt is not really connected to any IO-APIC pin,
55 * it's fed to the master 8259A's IR0 line only.
56 *
57 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
58 * this 'mixed mode' IRQ handling costs nothing because it's only used
59 * at IRQ setup time.
60 */
61 unsigned long io_apic_irqs;
62
63 void disable_8259A_irq(unsigned int irq)
64 {
65 unsigned int mask = 1 << irq;
66 unsigned long flags;
67
68 spin_lock_irqsave(&i8259A_lock, flags);
69 cached_irq_mask |= mask;
70 if (irq & 8)
71 outb(cached_slave_mask, PIC_SLAVE_IMR);
72 else
73 outb(cached_master_mask, PIC_MASTER_IMR);
74 spin_unlock_irqrestore(&i8259A_lock, flags);
75 }
76
77 void enable_8259A_irq(unsigned int irq)
78 {
79 unsigned int mask = ~(1 << irq);
80 unsigned long flags;
81
82 spin_lock_irqsave(&i8259A_lock, flags);
83 cached_irq_mask &= mask;
84 if (irq & 8)
85 outb(cached_slave_mask, PIC_SLAVE_IMR);
86 else
87 outb(cached_master_mask, PIC_MASTER_IMR);
88 spin_unlock_irqrestore(&i8259A_lock, flags);
89 }
90
91 int i8259A_irq_pending(unsigned int irq)
92 {
93 unsigned int mask = 1<<irq;
94 unsigned long flags;
95 int ret;
96
97 spin_lock_irqsave(&i8259A_lock, flags);
98 if (irq < 8)
99 ret = inb(PIC_MASTER_CMD) & mask;
100 else
101 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
102 spin_unlock_irqrestore(&i8259A_lock, flags);
103
104 return ret;
105 }
106
107 void make_8259A_irq(unsigned int irq)
108 {
109 disable_irq_nosync(irq);
110 io_apic_irqs &= ~(1<<irq);
111 set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
112 "XT");
113 enable_irq(irq);
114 }
115
116 /*
117 * This function assumes to be called rarely. Switching between
118 * 8259A registers is slow.
119 * This has to be protected by the irq controller spinlock
120 * before being called.
121 */
122 static inline int i8259A_irq_real(unsigned int irq)
123 {
124 int value;
125 int irqmask = 1<<irq;
126
127 if (irq < 8) {
128 outb(0x0B,PIC_MASTER_CMD); /* ISR register */
129 value = inb(PIC_MASTER_CMD) & irqmask;
130 outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
131 return value;
132 }
133 outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
134 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
135 outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
136 return value;
137 }
138
139 /*
140 * Careful! The 8259A is a fragile beast, it pretty
141 * much _has_ to be done exactly like this (mask it
142 * first, _then_ send the EOI, and the order of EOI
143 * to the two 8259s is important!
144 */
145 static void mask_and_ack_8259A(unsigned int irq)
146 {
147 unsigned int irqmask = 1 << irq;
148 unsigned long flags;
149
150 spin_lock_irqsave(&i8259A_lock, flags);
151 /*
152 * Lightweight spurious IRQ detection. We do not want
153 * to overdo spurious IRQ handling - it's usually a sign
154 * of hardware problems, so we only do the checks we can
155 * do without slowing down good hardware unnecessarily.
156 *
157 * Note that IRQ7 and IRQ15 (the two spurious IRQs
158 * usually resulting from the 8259A-1|2 PICs) occur
159 * even if the IRQ is masked in the 8259A. Thus we
160 * can check spurious 8259A IRQs without doing the
161 * quite slow i8259A_irq_real() call for every IRQ.
162 * This does not cover 100% of spurious interrupts,
163 * but should be enough to warn the user that there
164 * is something bad going on ...
165 */
166 if (cached_irq_mask & irqmask)
167 goto spurious_8259A_irq;
168 if (irq & 8)
169 outb(0x60+(irq&7),PIC_SLAVE_CMD); /* 'Specific EOI' to slave */
170 cached_irq_mask |= irqmask;
171
172 handle_real_irq:
173 if (irq & 8) {
174 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
175 outb(cached_slave_mask, PIC_SLAVE_IMR);
176 outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
177 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
178 } else {
179 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
180 outb(cached_master_mask, PIC_MASTER_IMR);
181 outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */
182 }
183 spin_unlock_irqrestore(&i8259A_lock, flags);
184 return;
185
186 spurious_8259A_irq:
187 /*
188 * this is the slow path - should happen rarely.
189 */
190 if (i8259A_irq_real(irq))
191 /*
192 * oops, the IRQ _is_ in service according to the
193 * 8259A - not spurious, go handle it.
194 */
195 goto handle_real_irq;
196
197 {
198 static int spurious_irq_mask;
199 /*
200 * At this point we can be sure the IRQ is spurious,
201 * lets ACK and report it. [once per IRQ]
202 */
203 if (!(spurious_irq_mask & irqmask)) {
204 printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
205 spurious_irq_mask |= irqmask;
206 }
207 atomic_inc(&irq_err_count);
208 /*
209 * Theoretically we do not have to handle this IRQ,
210 * but in Linux this does not cause problems and is
211 * simpler for us.
212 */
213 goto handle_real_irq;
214 }
215 }
216
217 static char irq_trigger[2];
218 /**
219 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
220 */
221 static void restore_ELCR(char *trigger)
222 {
223 outb(trigger[0], 0x4d0);
224 outb(trigger[1], 0x4d1);
225 }
226
227 static void save_ELCR(char *trigger)
228 {
229 /* IRQ 0,1,2,8,13 are marked as reserved */
230 trigger[0] = inb(0x4d0) & 0xF8;
231 trigger[1] = inb(0x4d1) & 0xDE;
232 }
233
234 static int i8259A_resume(struct sys_device *dev)
235 {
236 init_8259A(i8259A_auto_eoi);
237 restore_ELCR(irq_trigger);
238 return 0;
239 }
240
241 static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
242 {
243 save_ELCR(irq_trigger);
244 return 0;
245 }
246
247 static int i8259A_shutdown(struct sys_device *dev)
248 {
249 /* Put the i8259A into a quiescent state that
250 * the kernel initialization code can get it
251 * out of.
252 */
253 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
254 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
255 return 0;
256 }
257
258 static struct sysdev_class i8259_sysdev_class = {
259 .name = "i8259",
260 .suspend = i8259A_suspend,
261 .resume = i8259A_resume,
262 .shutdown = i8259A_shutdown,
263 };
264
265 static struct sys_device device_i8259A = {
266 .id = 0,
267 .cls = &i8259_sysdev_class,
268 };
269
270 static int __init i8259A_init_sysfs(void)
271 {
272 int error = sysdev_class_register(&i8259_sysdev_class);
273 if (!error)
274 error = sysdev_register(&device_i8259A);
275 return error;
276 }
277
278 device_initcall(i8259A_init_sysfs);
279
280 void init_8259A(int auto_eoi)
281 {
282 unsigned long flags;
283
284 i8259A_auto_eoi = auto_eoi;
285
286 spin_lock_irqsave(&i8259A_lock, flags);
287
288 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
289 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
290
291 /*
292 * outb_pic - this has to work on a wide range of PC hardware.
293 */
294 outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
295 outb_pic(0x20 + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
296 outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
297 if (!auto_eoi) /* master expects normal EOI */
298 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
299 else /* master does Auto EOI */
300 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
301
302 outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
303 outb_pic(0x20 + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
304 outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
305 outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
306 if (auto_eoi)
307 /*
308 * In AEOI mode we just have to mask the interrupt
309 * when acking.
310 */
311 i8259A_chip.mask_ack = disable_8259A_irq;
312 else
313 i8259A_chip.mask_ack = mask_and_ack_8259A;
314
315 udelay(100); /* wait for 8259A to initialize */
316
317 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
318 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
319
320 spin_unlock_irqrestore(&i8259A_lock, flags);
321 }
322
323 /*
324 * Note that on a 486, we don't want to do a SIGFPE on an irq13
325 * as the irq is unreliable, and exception 16 works correctly
326 * (ie as explained in the intel literature). On a 386, you
327 * can't use exception 16 due to bad IBM design, so we have to
328 * rely on the less exact irq13.
329 *
330 * Careful.. Not only is IRQ13 unreliable, but it is also
331 * leads to races. IBM designers who came up with it should
332 * be shot.
333 */
334
335
336 static irqreturn_t math_error_irq(int cpl, void *dev_id)
337 {
338 extern void math_error(void __user *);
339 outb(0,0xF0);
340 if (ignore_fpu_irq || !boot_cpu_data.hard_math)
341 return IRQ_NONE;
342 math_error((void __user *)get_irq_regs()->ip);
343 return IRQ_HANDLED;
344 }
345
346 /*
347 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
348 * so allow interrupt sharing.
349 */
350 static struct irqaction fpu_irq = {
351 .handler = math_error_irq,
352 .flags = IRQF_NODELAY,
353 .mask = CPU_MASK_NONE,
354 .name = "fpu",
355 };
356
357 void __init init_ISA_irqs (void)
358 {
359 int i;
360
361 #ifdef CONFIG_X86_LOCAL_APIC
362 init_bsp_APIC();
363 #endif
364 init_8259A(0);
365
366 /*
367 * 16 old-style INTA-cycle interrupts:
368 */
369 for (i = 0; i < 16; i++) {
370 set_irq_chip_and_handler_name(i, &i8259A_chip,
371 handle_level_irq, "XT");
372 }
373 }
374
375 /* Overridden in paravirt.c */
376 void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
377
378 void __init native_init_IRQ(void)
379 {
380 int i;
381
382 /* all the set up before the call gates are initialised */
383 pre_intr_init_hook();
384
385 /*
386 * Cover the whole vector space, no vector can escape
387 * us. (some of these will be overridden and become
388 * 'special' SMP interrupts)
389 */
390 for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
391 int vector = FIRST_EXTERNAL_VECTOR + i;
392 if (i >= NR_IRQS)
393 break;
394 /* SYSCALL_VECTOR was reserved in trap_init. */
395 if (!test_bit(vector, used_vectors))
396 set_intr_gate(vector, interrupt[i]);
397 }
398
399 /* setup after call gates are initialised (usually add in
400 * the architecture specific gates)
401 */
402 intr_init_hook();
403
404 /*
405 * External FPU? Set up irq13 if so, for
406 * original braindamaged IBM FERR coupling.
407 */
408 if (boot_cpu_data.hard_math && !cpu_has_fpu)
409 setup_irq(FPU_IRQ, &fpu_irq);
410
411 irq_ctx_init(smp_processor_id());
412 }
413
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