1 /*
2 * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
3 * M (part of the Centrino chipset).
4 *
5 * Since the original Pentium M, most new Intel CPUs support Enhanced
6 * SpeedStep.
7 *
8 * Despite the "SpeedStep" in the name, this is almost entirely unlike
9 * traditional SpeedStep.
10 *
11 * Modelled on speedstep.c
12 *
13 * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/cpufreq.h>
20 #include <linux/sched.h> /* current */
21 #include <linux/delay.h>
22 #include <linux/compiler.h>
23
24 #include <asm/msr.h>
25 #include <asm/processor.h>
26 #include <asm/cpufeature.h>
27
28 #define PFX "speedstep-centrino: "
29 #define MAINTAINER "cpufreq@lists.linux.org.uk"
30
31 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
32
33 #define INTEL_MSR_RANGE (0xffff)
34
35 struct cpu_id
36 {
37 __u8 x86; /* CPU family */
38 __u8 x86_model; /* model */
39 __u8 x86_mask; /* stepping */
40 };
41
42 enum {
43 CPU_BANIAS,
44 CPU_DOTHAN_A1,
45 CPU_DOTHAN_A2,
46 CPU_DOTHAN_B0,
47 CPU_MP4HT_D0,
48 CPU_MP4HT_E0,
49 };
50
51 static const struct cpu_id cpu_ids[] = {
52 [CPU_BANIAS] = { 6, 9, 5 },
53 [CPU_DOTHAN_A1] = { 6, 13, 1 },
54 [CPU_DOTHAN_A2] = { 6, 13, 2 },
55 [CPU_DOTHAN_B0] = { 6, 13, 6 },
56 [CPU_MP4HT_D0] = {15, 3, 4 },
57 [CPU_MP4HT_E0] = {15, 4, 1 },
58 };
59 #define N_IDS ARRAY_SIZE(cpu_ids)
60
61 struct cpu_model
62 {
63 const struct cpu_id *cpu_id;
64 const char *model_name;
65 unsigned max_freq; /* max clock in kHz */
66
67 struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
68 };
69 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x);
70
71 /* Operating points for current CPU */
72 static struct cpu_model *centrino_model[NR_CPUS];
73 static const struct cpu_id *centrino_cpu[NR_CPUS];
74
75 static struct cpufreq_driver centrino_driver;
76
77 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
78
79 /* Computes the correct form for IA32_PERF_CTL MSR for a particular
80 frequency/voltage operating point; frequency in MHz, volts in mV.
81 This is stored as "index" in the structure. */
82 #define OP(mhz, mv) \
83 { \
84 .frequency = (mhz) * 1000, \
85 .index = (((mhz)/100) << 8) | ((mv - 700) / 16) \
86 }
87
88 /*
89 * These voltage tables were derived from the Intel Pentium M
90 * datasheet, document 25261202.pdf, Table 5. I have verified they
91 * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
92 * M.
93 */
94
95 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
96 static struct cpufreq_frequency_table banias_900[] =
97 {
98 OP(600, 844),
99 OP(800, 988),
100 OP(900, 1004),
101 { .frequency = CPUFREQ_TABLE_END }
102 };
103
104 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
105 static struct cpufreq_frequency_table banias_1000[] =
106 {
107 OP(600, 844),
108 OP(800, 972),
109 OP(900, 988),
110 OP(1000, 1004),
111 { .frequency = CPUFREQ_TABLE_END }
112 };
113
114 /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
115 static struct cpufreq_frequency_table banias_1100[] =
116 {
117 OP( 600, 956),
118 OP( 800, 1020),
119 OP( 900, 1100),
120 OP(1000, 1164),
121 OP(1100, 1180),
122 { .frequency = CPUFREQ_TABLE_END }
123 };
124
125
126 /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
127 static struct cpufreq_frequency_table banias_1200[] =
128 {
129 OP( 600, 956),
130 OP( 800, 1004),
131 OP( 900, 1020),
132 OP(1000, 1100),
133 OP(1100, 1164),
134 OP(1200, 1180),
135 { .frequency = CPUFREQ_TABLE_END }
136 };
137
138 /* Intel Pentium M processor 1.30GHz (Banias) */
139 static struct cpufreq_frequency_table banias_1300[] =
140 {
141 OP( 600, 956),
142 OP( 800, 1260),
143 OP(1000, 1292),
144 OP(1200, 1356),
145 OP(1300, 1388),
146 { .frequency = CPUFREQ_TABLE_END }
147 };
148
149 /* Intel Pentium M processor 1.40GHz (Banias) */
150 static struct cpufreq_frequency_table banias_1400[] =
151 {
152 OP( 600, 956),
153 OP( 800, 1180),
154 OP(1000, 1308),
155 OP(1200, 1436),
156 OP(1400, 1484),
157 { .frequency = CPUFREQ_TABLE_END }
158 };
159
160 /* Intel Pentium M processor 1.50GHz (Banias) */
161 static struct cpufreq_frequency_table banias_1500[] =
162 {
163 OP( 600, 956),
164 OP( 800, 1116),
165 OP(1000, 1228),
166 OP(1200, 1356),
167 OP(1400, 1452),
168 OP(1500, 1484),
169 { .frequency = CPUFREQ_TABLE_END }
170 };
171
172 /* Intel Pentium M processor 1.60GHz (Banias) */
173 static struct cpufreq_frequency_table banias_1600[] =
174 {
175 OP( 600, 956),
176 OP( 800, 1036),
177 OP(1000, 1164),
178 OP(1200, 1276),
179 OP(1400, 1420),
180 OP(1600, 1484),
181 { .frequency = CPUFREQ_TABLE_END }
182 };
183
184 /* Intel Pentium M processor 1.70GHz (Banias) */
185 static struct cpufreq_frequency_table banias_1700[] =
186 {
187 OP( 600, 956),
188 OP( 800, 1004),
189 OP(1000, 1116),
190 OP(1200, 1228),
191 OP(1400, 1308),
192 OP(1700, 1484),
193 { .frequency = CPUFREQ_TABLE_END }
194 };
195 #undef OP
196
197 #define _BANIAS(cpuid, max, name) \
198 { .cpu_id = cpuid, \
199 .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
200 .max_freq = (max)*1000, \
201 .op_points = banias_##max, \
202 }
203 #define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
204
205 /* CPU models, their operating frequency range, and freq/voltage
206 operating points */
207 static struct cpu_model models[] =
208 {
209 _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
210 BANIAS(1000),
211 BANIAS(1100),
212 BANIAS(1200),
213 BANIAS(1300),
214 BANIAS(1400),
215 BANIAS(1500),
216 BANIAS(1600),
217 BANIAS(1700),
218
219 /* NULL model_name is a wildcard */
220 { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
221 { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
222 { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
223 { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
224 { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
225
226 { NULL, }
227 };
228 #undef _BANIAS
229 #undef BANIAS
230
231 static int centrino_cpu_init_table(struct cpufreq_policy *policy)
232 {
233 struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
234 struct cpu_model *model;
235
236 for(model = models; model->cpu_id != NULL; model++)
237 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
238 (model->model_name == NULL ||
239 strcmp(cpu->x86_model_id, model->model_name) == 0))
240 break;
241
242 if (model->cpu_id == NULL) {
243 /* No match at all */
244 dprintk("no support for CPU model \"%s\": "
245 "send /proc/cpuinfo to " MAINTAINER "\n",
246 cpu->x86_model_id);
247 return -ENOENT;
248 }
249
250 if (model->op_points == NULL) {
251 /* Matched a non-match */
252 dprintk("no table support for CPU model \"%s\"\n",
253 cpu->x86_model_id);
254 dprintk("try using the acpi-cpufreq driver\n");
255 return -ENOENT;
256 }
257
258 centrino_model[policy->cpu] = model;
259
260 dprintk("found \"%s\": max frequency: %dkHz\n",
261 model->model_name, model->max_freq);
262
263 return 0;
264 }
265
266 #else
267 static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; }
268 #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
269
270 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x)
271 {
272 if ((c->x86 == x->x86) &&
273 (c->x86_model == x->x86_model) &&
274 (c->x86_mask == x->x86_mask))
275 return 1;
276 return 0;
277 }
278
279 /* To be called only after centrino_model is initialized */
280 static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
281 {
282 int i;
283
284 /*
285 * Extract clock in kHz from PERF_CTL value
286 * for centrino, as some DSDTs are buggy.
287 * Ideally, this can be done using the acpi_data structure.
288 */
289 if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) ||
290 (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) ||
291 (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) {
292 msr = (msr >> 8) & 0xff;
293 return msr * 100000;
294 }
295
296 if ((!centrino_model[cpu]) || (!centrino_model[cpu]->op_points))
297 return 0;
298
299 msr &= 0xffff;
300 for (i=0;centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) {
301 if (msr == centrino_model[cpu]->op_points[i].index)
302 return centrino_model[cpu]->op_points[i].frequency;
303 }
304 if (failsafe)
305 return centrino_model[cpu]->op_points[i-1].frequency;
306 else
307 return 0;
308 }
309
310 /* Return the current CPU frequency in kHz */
311 static unsigned int get_cur_freq(unsigned int cpu)
312 {
313 unsigned l, h;
314 unsigned clock_freq;
315 cpumask_t saved_mask;
316
317 saved_mask = current->cpus_allowed;
318 set_cpus_allowed(current, cpumask_of_cpu(cpu));
319 if (smp_processor_id() != cpu)
320 return 0;
321
322 rdmsr(MSR_IA32_PERF_STATUS, l, h);
323 clock_freq = extract_clock(l, cpu, 0);
324
325 if (unlikely(clock_freq == 0)) {
326 /*
327 * On some CPUs, we can see transient MSR values (which are
328 * not present in _PSS), while CPU is doing some automatic
329 * P-state transition (like TM2). Get the last freq set
330 * in PERF_CTL.
331 */
332 rdmsr(MSR_IA32_PERF_CTL, l, h);
333 clock_freq = extract_clock(l, cpu, 1);
334 }
335
336 set_cpus_allowed(current, saved_mask);
337 return clock_freq;
338 }
339
340
341 static int centrino_cpu_init(struct cpufreq_policy *policy)
342 {
343 struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
344 unsigned freq;
345 unsigned l, h;
346 int ret;
347 int i;
348
349 /* Only Intel makes Enhanced Speedstep-capable CPUs */
350 if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST))
351 return -ENODEV;
352
353 if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
354 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
355
356 if (policy->cpu != 0)
357 return -ENODEV;
358
359 for (i = 0; i < N_IDS; i++)
360 if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
361 break;
362
363 if (i != N_IDS)
364 centrino_cpu[policy->cpu] = &cpu_ids[i];
365
366 if (!centrino_cpu[policy->cpu]) {
367 dprintk("found unsupported CPU with "
368 "Enhanced SpeedStep: send /proc/cpuinfo to "
369 MAINTAINER "\n");
370 return -ENODEV;
371 }
372
373 if (centrino_cpu_init_table(policy)) {
374 return -ENODEV;
375 }
376
377 /* Check to see if Enhanced SpeedStep is enabled, and try to
378 enable it if not. */
379 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
380
381 if (!(l & (1<<16))) {
382 l |= (1<<16);
383 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
384 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
385
386 /* check to see if it stuck */
387 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
388 if (!(l & (1<<16))) {
389 printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n");
390 return -ENODEV;
391 }
392 }
393
394 freq = get_cur_freq(policy->cpu);
395
396 policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */
397 policy->cur = freq;
398
399 dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
400
401 ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model[policy->cpu]->op_points);
402 if (ret)
403 return (ret);
404
405 cpufreq_frequency_table_get_attr(centrino_model[policy->cpu]->op_points, policy->cpu);
406
407 return 0;
408 }
409
410 static int centrino_cpu_exit(struct cpufreq_policy *policy)
411 {
412 unsigned int cpu = policy->cpu;
413
414 if (!centrino_model[cpu])
415 return -ENODEV;
416
417 cpufreq_frequency_table_put_attr(cpu);
418
419 centrino_model[cpu] = NULL;
420
421 return 0;
422 }
423
424 /**
425 * centrino_verify - verifies a new CPUFreq policy
426 * @policy: new policy
427 *
428 * Limit must be within this model's frequency range at least one
429 * border included.
430 */
431 static int centrino_verify (struct cpufreq_policy *policy)
432 {
433 return cpufreq_frequency_table_verify(policy, centrino_model[policy->cpu]->op_points);
434 }
435
436 /**
437 * centrino_setpolicy - set a new CPUFreq policy
438 * @policy: new policy
439 * @target_freq: the target frequency
440 * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
441 *
442 * Sets a new CPUFreq policy.
443 */
444 static int centrino_target (struct cpufreq_policy *policy,
445 unsigned int target_freq,
446 unsigned int relation)
447 {
448 unsigned int newstate = 0;
449 unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu;
450 struct cpufreq_freqs freqs;
451 cpumask_t online_policy_cpus;
452 cpumask_t saved_mask;
453 cpumask_t set_mask;
454 cpumask_t covered_cpus;
455 int retval = 0;
456 unsigned int j, k, first_cpu, tmp;
457
458 if (unlikely(centrino_model[cpu] == NULL))
459 return -ENODEV;
460
461 if (unlikely(cpufreq_frequency_table_target(policy,
462 centrino_model[cpu]->op_points,
463 target_freq,
464 relation,
465 &newstate))) {
466 return -EINVAL;
467 }
468
469 #ifdef CONFIG_HOTPLUG_CPU
470 /* cpufreq holds the hotplug lock, so we are safe from here on */
471 cpus_and(online_policy_cpus, cpu_online_map, policy->cpus);
472 #else
473 online_policy_cpus = policy->cpus;
474 #endif
475
476 saved_mask = current->cpus_allowed;
477 first_cpu = 1;
478 cpus_clear(covered_cpus);
479 for_each_cpu_mask(j, online_policy_cpus) {
480 /*
481 * Support for SMP systems.
482 * Make sure we are running on CPU that wants to change freq
483 */
484 cpus_clear(set_mask);
485 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
486 cpus_or(set_mask, set_mask, online_policy_cpus);
487 else
488 cpu_set(j, set_mask);
489
490 set_cpus_allowed(current, set_mask);
491 preempt_disable();
492 if (unlikely(!cpu_isset(smp_processor_id(), set_mask))) {
493 dprintk("couldn't limit to CPUs in this domain\n");
494 retval = -EAGAIN;
495 if (first_cpu) {
496 /* We haven't started the transition yet. */
497 goto migrate_end;
498 }
499 preempt_enable();
500 break;
501 }
502
503 msr = centrino_model[cpu]->op_points[newstate].index;
504
505 if (first_cpu) {
506 rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
507 if (msr == (oldmsr & 0xffff)) {
508 dprintk("no change needed - msr was and needs "
509 "to be %x\n", oldmsr);
510 retval = 0;
511 goto migrate_end;
512 }
513
514 freqs.old = extract_clock(oldmsr, cpu, 0);
515 freqs.new = extract_clock(msr, cpu, 0);
516
517 dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
518 target_freq, freqs.old, freqs.new, msr);
519
520 for_each_cpu_mask(k, online_policy_cpus) {
521 freqs.cpu = k;
522 cpufreq_notify_transition(&freqs,
523 CPUFREQ_PRECHANGE);
524 }
525
526 first_cpu = 0;
527 /* all but 16 LSB are reserved, treat them with care */
528 oldmsr &= ~0xffff;
529 msr &= 0xffff;
530 oldmsr |= msr;
531 }
532
533 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
534 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) {
535 preempt_enable();
536 break;
537 }
538
539 cpu_set(j, covered_cpus);
540 preempt_enable();
541 }
542
543 for_each_cpu_mask(k, online_policy_cpus) {
544 freqs.cpu = k;
545 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
546 }
547
548 if (unlikely(retval)) {
549 /*
550 * We have failed halfway through the frequency change.
551 * We have sent callbacks to policy->cpus and
552 * MSRs have already been written on coverd_cpus.
553 * Best effort undo..
554 */
555
556 if (!cpus_empty(covered_cpus)) {
557 for_each_cpu_mask(j, covered_cpus) {
558 set_cpus_allowed(current, cpumask_of_cpu(j));
559 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
560 }
561 }
562
563 tmp = freqs.new;
564 freqs.new = freqs.old;
565 freqs.old = tmp;
566 for_each_cpu_mask(j, online_policy_cpus) {
567 freqs.cpu = j;
568 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
569 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
570 }
571 }
572 set_cpus_allowed(current, saved_mask);
573 return 0;
574
575 migrate_end:
576 preempt_enable();
577 set_cpus_allowed(current, saved_mask);
578 return 0;
579 }
580
581 static struct freq_attr* centrino_attr[] = {
582 &cpufreq_freq_attr_scaling_available_freqs,
583 NULL,
584 };
585
586 static struct cpufreq_driver centrino_driver = {
587 .name = "centrino", /* should be speedstep-centrino,
588 but there's a 16 char limit */
589 .init = centrino_cpu_init,
590 .exit = centrino_cpu_exit,
591 .verify = centrino_verify,
592 .target = centrino_target,
593 .get = get_cur_freq,
594 .attr = centrino_attr,
595 .owner = THIS_MODULE,
596 };
597
598
599 /**
600 * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
601 *
602 * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
603 * unsupported devices, -ENOENT if there's no voltage table for this
604 * particular CPU model, -EINVAL on problems during initiatization,
605 * and zero on success.
606 *
607 * This is quite picky. Not only does the CPU have to advertise the
608 * "est" flag in the cpuid capability flags, we look for a specific
609 * CPU model and stepping, and we need to have the exact model name in
610 * our voltage tables. That is, be paranoid about not releasing
611 * someone's valuable magic smoke.
612 */
613 static int __init centrino_init(void)
614 {
615 struct cpuinfo_x86 *cpu = &cpu_data(0);
616
617 if (!cpu_has(cpu, X86_FEATURE_EST))
618 return -ENODEV;
619
620 return cpufreq_register_driver(¢rino_driver);
621 }
622
623 static void __exit centrino_exit(void)
624 {
625 cpufreq_unregister_driver(¢rino_driver);
626 }
627
628 MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
629 MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
630 MODULE_LICENSE ("GPL");
631
632 late_initcall(centrino_init);
633 module_exit(centrino_exit);
634
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