1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #ifdef CONFIG_ACPI
40 #include <acpi/acpi_bus.h>
41 #endif
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
45
46 #include <asm/idle.h>
47 #include <asm/io.h>
48 #include <asm/smp.h>
49 #include <asm/cpu.h>
50 #include <asm/desc.h>
51 #include <asm/proto.h>
52 #include <asm/acpi.h>
53 #include <asm/dma.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
56 #include <asm/nmi.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
61 #include <asm/hpet.h>
62 #include <asm/hw_irq.h>
63 #include <asm/uv/uv_hub.h>
64 #include <asm/uv/uv_irq.h>
65
66 #include <asm/apic.h>
67
68 #define __apicdebuginit(type) static type __init
69
70 /*
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
73 */
74 int sis_apic_bug = -1;
75
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
78
79 /*
80 * # of IRQ routing registers
81 */
82 int nr_ioapic_registers[MAX_IO_APICS];
83
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
86 int nr_ioapics;
87
88 /* MP IRQ source entries */
89 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
90
91 /* # of MP IRQ source entries */
92 int mp_irq_entries;
93
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type[MAX_MP_BUSSES];
96 #endif
97
98 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
99
100 int skip_ioapic_setup;
101
102 void arch_disable_smp_support(void)
103 {
104 #ifdef CONFIG_PCI
105 noioapicquirk = 1;
106 noioapicreroute = -1;
107 #endif
108 skip_ioapic_setup = 1;
109 }
110
111 static int __init parse_noapic(char *str)
112 {
113 /* disable IO-APIC */
114 arch_disable_smp_support();
115 return 0;
116 }
117 early_param("noapic", parse_noapic);
118
119 struct irq_pin_list;
120
121 /*
122 * This is performance-critical, we want to do it O(1)
123 *
124 * the indexing order of this array favors 1:1 mappings
125 * between pins and IRQs.
126 */
127
128 struct irq_pin_list {
129 int apic, pin;
130 struct irq_pin_list *next;
131 };
132
133 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
134 {
135 struct irq_pin_list *pin;
136
137 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
138
139 return pin;
140 }
141
142 struct irq_cfg {
143 struct irq_pin_list *irq_2_pin;
144 cpumask_var_t domain;
145 cpumask_var_t old_domain;
146 unsigned move_cleanup_count;
147 u8 vector;
148 u8 move_in_progress : 1;
149 };
150
151 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
152 #ifdef CONFIG_SPARSE_IRQ
153 static struct irq_cfg irq_cfgx[] = {
154 #else
155 static struct irq_cfg irq_cfgx[NR_IRQS] = {
156 #endif
157 [0] = { .vector = IRQ0_VECTOR, },
158 [1] = { .vector = IRQ1_VECTOR, },
159 [2] = { .vector = IRQ2_VECTOR, },
160 [3] = { .vector = IRQ3_VECTOR, },
161 [4] = { .vector = IRQ4_VECTOR, },
162 [5] = { .vector = IRQ5_VECTOR, },
163 [6] = { .vector = IRQ6_VECTOR, },
164 [7] = { .vector = IRQ7_VECTOR, },
165 [8] = { .vector = IRQ8_VECTOR, },
166 [9] = { .vector = IRQ9_VECTOR, },
167 [10] = { .vector = IRQ10_VECTOR, },
168 [11] = { .vector = IRQ11_VECTOR, },
169 [12] = { .vector = IRQ12_VECTOR, },
170 [13] = { .vector = IRQ13_VECTOR, },
171 [14] = { .vector = IRQ14_VECTOR, },
172 [15] = { .vector = IRQ15_VECTOR, },
173 };
174
175 int __init arch_early_irq_init(void)
176 {
177 struct irq_cfg *cfg;
178 struct irq_desc *desc;
179 int count;
180 int node;
181 int i;
182
183 cfg = irq_cfgx;
184 count = ARRAY_SIZE(irq_cfgx);
185 node= cpu_to_node(boot_cpu_id);
186
187 for (i = 0; i < count; i++) {
188 desc = irq_to_desc(i);
189 desc->chip_data = &cfg[i];
190 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
191 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
192 if (i < NR_IRQS_LEGACY)
193 cpumask_setall(cfg[i].domain);
194 }
195
196 return 0;
197 }
198
199 #ifdef CONFIG_SPARSE_IRQ
200 static struct irq_cfg *irq_cfg(unsigned int irq)
201 {
202 struct irq_cfg *cfg = NULL;
203 struct irq_desc *desc;
204
205 desc = irq_to_desc(irq);
206 if (desc)
207 cfg = desc->chip_data;
208
209 return cfg;
210 }
211
212 static struct irq_cfg *get_one_free_irq_cfg(int node)
213 {
214 struct irq_cfg *cfg;
215
216 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
217 if (cfg) {
218 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
219 kfree(cfg);
220 cfg = NULL;
221 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
222 GFP_ATOMIC, node)) {
223 free_cpumask_var(cfg->domain);
224 kfree(cfg);
225 cfg = NULL;
226 } else {
227 cpumask_clear(cfg->domain);
228 cpumask_clear(cfg->old_domain);
229 }
230 }
231
232 return cfg;
233 }
234
235 int arch_init_chip_data(struct irq_desc *desc, int node)
236 {
237 struct irq_cfg *cfg;
238
239 cfg = desc->chip_data;
240 if (!cfg) {
241 desc->chip_data = get_one_free_irq_cfg(node);
242 if (!desc->chip_data) {
243 printk(KERN_ERR "can not alloc irq_cfg\n");
244 BUG_ON(1);
245 }
246 }
247
248 return 0;
249 }
250
251 /* for move_irq_desc */
252 static void
253 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
254 {
255 struct irq_pin_list *old_entry, *head, *tail, *entry;
256
257 cfg->irq_2_pin = NULL;
258 old_entry = old_cfg->irq_2_pin;
259 if (!old_entry)
260 return;
261
262 entry = get_one_free_irq_2_pin(node);
263 if (!entry)
264 return;
265
266 entry->apic = old_entry->apic;
267 entry->pin = old_entry->pin;
268 head = entry;
269 tail = entry;
270 old_entry = old_entry->next;
271 while (old_entry) {
272 entry = get_one_free_irq_2_pin(node);
273 if (!entry) {
274 entry = head;
275 while (entry) {
276 head = entry->next;
277 kfree(entry);
278 entry = head;
279 }
280 /* still use the old one */
281 return;
282 }
283 entry->apic = old_entry->apic;
284 entry->pin = old_entry->pin;
285 tail->next = entry;
286 tail = entry;
287 old_entry = old_entry->next;
288 }
289
290 tail->next = NULL;
291 cfg->irq_2_pin = head;
292 }
293
294 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
295 {
296 struct irq_pin_list *entry, *next;
297
298 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
299 return;
300
301 entry = old_cfg->irq_2_pin;
302
303 while (entry) {
304 next = entry->next;
305 kfree(entry);
306 entry = next;
307 }
308 old_cfg->irq_2_pin = NULL;
309 }
310
311 void arch_init_copy_chip_data(struct irq_desc *old_desc,
312 struct irq_desc *desc, int node)
313 {
314 struct irq_cfg *cfg;
315 struct irq_cfg *old_cfg;
316
317 cfg = get_one_free_irq_cfg(node);
318
319 if (!cfg)
320 return;
321
322 desc->chip_data = cfg;
323
324 old_cfg = old_desc->chip_data;
325
326 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
327
328 init_copy_irq_2_pin(old_cfg, cfg, node);
329 }
330
331 static void free_irq_cfg(struct irq_cfg *old_cfg)
332 {
333 kfree(old_cfg);
334 }
335
336 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
337 {
338 struct irq_cfg *old_cfg, *cfg;
339
340 old_cfg = old_desc->chip_data;
341 cfg = desc->chip_data;
342
343 if (old_cfg == cfg)
344 return;
345
346 if (old_cfg) {
347 free_irq_2_pin(old_cfg, cfg);
348 free_irq_cfg(old_cfg);
349 old_desc->chip_data = NULL;
350 }
351 }
352 /* end for move_irq_desc */
353
354 #else
355 static struct irq_cfg *irq_cfg(unsigned int irq)
356 {
357 return irq < nr_irqs ? irq_cfgx + irq : NULL;
358 }
359
360 #endif
361
362 struct io_apic {
363 unsigned int index;
364 unsigned int unused[3];
365 unsigned int data;
366 unsigned int unused2[11];
367 unsigned int eoi;
368 };
369
370 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
371 {
372 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
373 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
374 }
375
376 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
377 {
378 struct io_apic __iomem *io_apic = io_apic_base(apic);
379 writel(vector, &io_apic->eoi);
380 }
381
382 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
383 {
384 struct io_apic __iomem *io_apic = io_apic_base(apic);
385 writel(reg, &io_apic->index);
386 return readl(&io_apic->data);
387 }
388
389 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
390 {
391 struct io_apic __iomem *io_apic = io_apic_base(apic);
392 writel(reg, &io_apic->index);
393 writel(value, &io_apic->data);
394 }
395
396 /*
397 * Re-write a value: to be used for read-modify-write
398 * cycles where the read already set up the index register.
399 *
400 * Older SiS APIC requires we rewrite the index register
401 */
402 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
403 {
404 struct io_apic __iomem *io_apic = io_apic_base(apic);
405
406 if (sis_apic_bug)
407 writel(reg, &io_apic->index);
408 writel(value, &io_apic->data);
409 }
410
411 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
412 {
413 struct irq_pin_list *entry;
414 unsigned long flags;
415
416 spin_lock_irqsave(&ioapic_lock, flags);
417 entry = cfg->irq_2_pin;
418 for (;;) {
419 unsigned int reg;
420 int pin;
421
422 if (!entry)
423 break;
424 pin = entry->pin;
425 reg = io_apic_read(entry->apic, 0x10 + pin*2);
426 /* Is the remote IRR bit set? */
427 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
428 spin_unlock_irqrestore(&ioapic_lock, flags);
429 return true;
430 }
431 if (!entry->next)
432 break;
433 entry = entry->next;
434 }
435 spin_unlock_irqrestore(&ioapic_lock, flags);
436
437 return false;
438 }
439
440 union entry_union {
441 struct { u32 w1, w2; };
442 struct IO_APIC_route_entry entry;
443 };
444
445 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
446 {
447 union entry_union eu;
448 unsigned long flags;
449 spin_lock_irqsave(&ioapic_lock, flags);
450 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
451 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
452 spin_unlock_irqrestore(&ioapic_lock, flags);
453 return eu.entry;
454 }
455
456 /*
457 * When we write a new IO APIC routing entry, we need to write the high
458 * word first! If the mask bit in the low word is clear, we will enable
459 * the interrupt, and we need to make sure the entry is fully populated
460 * before that happens.
461 */
462 static void
463 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
464 {
465 union entry_union eu = {{0, 0}};
466
467 eu.entry = e;
468 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
469 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
470 }
471
472 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
473 {
474 unsigned long flags;
475 spin_lock_irqsave(&ioapic_lock, flags);
476 __ioapic_write_entry(apic, pin, e);
477 spin_unlock_irqrestore(&ioapic_lock, flags);
478 }
479
480 /*
481 * When we mask an IO APIC routing entry, we need to write the low
482 * word first, in order to set the mask bit before we change the
483 * high bits!
484 */
485 static void ioapic_mask_entry(int apic, int pin)
486 {
487 unsigned long flags;
488 union entry_union eu = { .entry.mask = 1 };
489
490 spin_lock_irqsave(&ioapic_lock, flags);
491 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
492 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
493 spin_unlock_irqrestore(&ioapic_lock, flags);
494 }
495
496 /*
497 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
498 * shared ISA-space IRQs, so we have to support them. We are super
499 * fast in the common case, and fast for shared ISA-space IRQs.
500 */
501 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
502 {
503 struct irq_pin_list *entry;
504
505 entry = cfg->irq_2_pin;
506 if (!entry) {
507 entry = get_one_free_irq_2_pin(node);
508 if (!entry) {
509 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
510 apic, pin);
511 return;
512 }
513 cfg->irq_2_pin = entry;
514 entry->apic = apic;
515 entry->pin = pin;
516 return;
517 }
518
519 while (entry->next) {
520 /* not again, please */
521 if (entry->apic == apic && entry->pin == pin)
522 return;
523
524 entry = entry->next;
525 }
526
527 entry->next = get_one_free_irq_2_pin(node);
528 entry = entry->next;
529 entry->apic = apic;
530 entry->pin = pin;
531 }
532
533 /*
534 * Reroute an IRQ to a different pin.
535 */
536 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
537 int oldapic, int oldpin,
538 int newapic, int newpin)
539 {
540 struct irq_pin_list *entry = cfg->irq_2_pin;
541 int replaced = 0;
542
543 while (entry) {
544 if (entry->apic == oldapic && entry->pin == oldpin) {
545 entry->apic = newapic;
546 entry->pin = newpin;
547 replaced = 1;
548 /* every one is different, right? */
549 break;
550 }
551 entry = entry->next;
552 }
553
554 /* why? call replace before add? */
555 if (!replaced)
556 add_pin_to_irq_node(cfg, node, newapic, newpin);
557 }
558
559 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
560 int mask_and, int mask_or,
561 void (*final)(struct irq_pin_list *entry))
562 {
563 int pin;
564 struct irq_pin_list *entry;
565
566 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
567 unsigned int reg;
568 pin = entry->pin;
569 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
570 reg &= mask_and;
571 reg |= mask_or;
572 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
573 if (final)
574 final(entry);
575 }
576 }
577
578 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
579 {
580 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
581 }
582
583 #ifdef CONFIG_X86_64
584 static void io_apic_sync(struct irq_pin_list *entry)
585 {
586 /*
587 * Synchronize the IO-APIC and the CPU by doing
588 * a dummy read from the IO-APIC
589 */
590 struct io_apic __iomem *io_apic;
591 io_apic = io_apic_base(entry->apic);
592 readl(&io_apic->data);
593 }
594
595 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
596 {
597 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
598 }
599 #else /* CONFIG_X86_32 */
600 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
601 {
602 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
603 }
604
605 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
606 {
607 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
608 IO_APIC_REDIR_MASKED, NULL);
609 }
610
611 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
612 {
613 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
614 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
615 }
616 #endif /* CONFIG_X86_32 */
617
618 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
619 {
620 struct irq_cfg *cfg = desc->chip_data;
621 unsigned long flags;
622
623 BUG_ON(!cfg);
624
625 spin_lock_irqsave(&ioapic_lock, flags);
626 __mask_IO_APIC_irq(cfg);
627 spin_unlock_irqrestore(&ioapic_lock, flags);
628 }
629
630 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
631 {
632 struct irq_cfg *cfg = desc->chip_data;
633 unsigned long flags;
634
635 spin_lock_irqsave(&ioapic_lock, flags);
636 __unmask_IO_APIC_irq(cfg);
637 spin_unlock_irqrestore(&ioapic_lock, flags);
638 }
639
640 static void mask_IO_APIC_irq(unsigned int irq)
641 {
642 struct irq_desc *desc = irq_to_desc(irq);
643
644 mask_IO_APIC_irq_desc(desc);
645 }
646 static void unmask_IO_APIC_irq(unsigned int irq)
647 {
648 struct irq_desc *desc = irq_to_desc(irq);
649
650 unmask_IO_APIC_irq_desc(desc);
651 }
652
653 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
654 {
655 struct IO_APIC_route_entry entry;
656
657 /* Check delivery_mode to be sure we're not clearing an SMI pin */
658 entry = ioapic_read_entry(apic, pin);
659 if (entry.delivery_mode == dest_SMI)
660 return;
661 /*
662 * Disable it in the IO-APIC irq-routing table:
663 */
664 ioapic_mask_entry(apic, pin);
665 }
666
667 static void clear_IO_APIC (void)
668 {
669 int apic, pin;
670
671 for (apic = 0; apic < nr_ioapics; apic++)
672 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
673 clear_IO_APIC_pin(apic, pin);
674 }
675
676 #ifdef CONFIG_X86_32
677 /*
678 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
679 * specific CPU-side IRQs.
680 */
681
682 #define MAX_PIRQS 8
683 static int pirq_entries[MAX_PIRQS] = {
684 [0 ... MAX_PIRQS - 1] = -1
685 };
686
687 static int __init ioapic_pirq_setup(char *str)
688 {
689 int i, max;
690 int ints[MAX_PIRQS+1];
691
692 get_options(str, ARRAY_SIZE(ints), ints);
693
694 apic_printk(APIC_VERBOSE, KERN_INFO
695 "PIRQ redirection, working around broken MP-BIOS.\n");
696 max = MAX_PIRQS;
697 if (ints[0] < MAX_PIRQS)
698 max = ints[0];
699
700 for (i = 0; i < max; i++) {
701 apic_printk(APIC_VERBOSE, KERN_DEBUG
702 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
703 /*
704 * PIRQs are mapped upside down, usually.
705 */
706 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
707 }
708 return 1;
709 }
710
711 __setup("pirq=", ioapic_pirq_setup);
712 #endif /* CONFIG_X86_32 */
713
714 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
715 {
716 int apic;
717 struct IO_APIC_route_entry **ioapic_entries;
718
719 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
720 GFP_ATOMIC);
721 if (!ioapic_entries)
722 return 0;
723
724 for (apic = 0; apic < nr_ioapics; apic++) {
725 ioapic_entries[apic] =
726 kzalloc(sizeof(struct IO_APIC_route_entry) *
727 nr_ioapic_registers[apic], GFP_ATOMIC);
728 if (!ioapic_entries[apic])
729 goto nomem;
730 }
731
732 return ioapic_entries;
733
734 nomem:
735 while (--apic >= 0)
736 kfree(ioapic_entries[apic]);
737 kfree(ioapic_entries);
738
739 return 0;
740 }
741
742 /*
743 * Saves all the IO-APIC RTE's
744 */
745 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
746 {
747 int apic, pin;
748
749 if (!ioapic_entries)
750 return -ENOMEM;
751
752 for (apic = 0; apic < nr_ioapics; apic++) {
753 if (!ioapic_entries[apic])
754 return -ENOMEM;
755
756 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
757 ioapic_entries[apic][pin] =
758 ioapic_read_entry(apic, pin);
759 }
760
761 return 0;
762 }
763
764 /*
765 * Mask all IO APIC entries.
766 */
767 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
768 {
769 int apic, pin;
770
771 if (!ioapic_entries)
772 return;
773
774 for (apic = 0; apic < nr_ioapics; apic++) {
775 if (!ioapic_entries[apic])
776 break;
777
778 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
779 struct IO_APIC_route_entry entry;
780
781 entry = ioapic_entries[apic][pin];
782 if (!entry.mask) {
783 entry.mask = 1;
784 ioapic_write_entry(apic, pin, entry);
785 }
786 }
787 }
788 }
789
790 /*
791 * Restore IO APIC entries which was saved in ioapic_entries.
792 */
793 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
794 {
795 int apic, pin;
796
797 if (!ioapic_entries)
798 return -ENOMEM;
799
800 for (apic = 0; apic < nr_ioapics; apic++) {
801 if (!ioapic_entries[apic])
802 return -ENOMEM;
803
804 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
805 ioapic_write_entry(apic, pin,
806 ioapic_entries[apic][pin]);
807 }
808 return 0;
809 }
810
811 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
812 {
813 int apic;
814
815 for (apic = 0; apic < nr_ioapics; apic++)
816 kfree(ioapic_entries[apic]);
817
818 kfree(ioapic_entries);
819 }
820
821 /*
822 * Find the IRQ entry number of a certain pin.
823 */
824 static int find_irq_entry(int apic, int pin, int type)
825 {
826 int i;
827
828 for (i = 0; i < mp_irq_entries; i++)
829 if (mp_irqs[i].irqtype == type &&
830 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
831 mp_irqs[i].dstapic == MP_APIC_ALL) &&
832 mp_irqs[i].dstirq == pin)
833 return i;
834
835 return -1;
836 }
837
838 /*
839 * Find the pin to which IRQ[irq] (ISA) is connected
840 */
841 static int __init find_isa_irq_pin(int irq, int type)
842 {
843 int i;
844
845 for (i = 0; i < mp_irq_entries; i++) {
846 int lbus = mp_irqs[i].srcbus;
847
848 if (test_bit(lbus, mp_bus_not_pci) &&
849 (mp_irqs[i].irqtype == type) &&
850 (mp_irqs[i].srcbusirq == irq))
851
852 return mp_irqs[i].dstirq;
853 }
854 return -1;
855 }
856
857 static int __init find_isa_irq_apic(int irq, int type)
858 {
859 int i;
860
861 for (i = 0; i < mp_irq_entries; i++) {
862 int lbus = mp_irqs[i].srcbus;
863
864 if (test_bit(lbus, mp_bus_not_pci) &&
865 (mp_irqs[i].irqtype == type) &&
866 (mp_irqs[i].srcbusirq == irq))
867 break;
868 }
869 if (i < mp_irq_entries) {
870 int apic;
871 for(apic = 0; apic < nr_ioapics; apic++) {
872 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
873 return apic;
874 }
875 }
876
877 return -1;
878 }
879
880 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
881 /*
882 * EISA Edge/Level control register, ELCR
883 */
884 static int EISA_ELCR(unsigned int irq)
885 {
886 if (irq < NR_IRQS_LEGACY) {
887 unsigned int port = 0x4d0 + (irq >> 3);
888 return (inb(port) >> (irq & 7)) & 1;
889 }
890 apic_printk(APIC_VERBOSE, KERN_INFO
891 "Broken MPtable reports ISA irq %d\n", irq);
892 return 0;
893 }
894
895 #endif
896
897 /* ISA interrupts are always polarity zero edge triggered,
898 * when listed as conforming in the MP table. */
899
900 #define default_ISA_trigger(idx) (0)
901 #define default_ISA_polarity(idx) (0)
902
903 /* EISA interrupts are always polarity zero and can be edge or level
904 * trigger depending on the ELCR value. If an interrupt is listed as
905 * EISA conforming in the MP table, that means its trigger type must
906 * be read in from the ELCR */
907
908 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
909 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
910
911 /* PCI interrupts are always polarity one level triggered,
912 * when listed as conforming in the MP table. */
913
914 #define default_PCI_trigger(idx) (1)
915 #define default_PCI_polarity(idx) (1)
916
917 /* MCA interrupts are always polarity zero level triggered,
918 * when listed as conforming in the MP table. */
919
920 #define default_MCA_trigger(idx) (1)
921 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
922
923 static int MPBIOS_polarity(int idx)
924 {
925 int bus = mp_irqs[idx].srcbus;
926 int polarity;
927
928 /*
929 * Determine IRQ line polarity (high active or low active):
930 */
931 switch (mp_irqs[idx].irqflag & 3)
932 {
933 case 0: /* conforms, ie. bus-type dependent polarity */
934 if (test_bit(bus, mp_bus_not_pci))
935 polarity = default_ISA_polarity(idx);
936 else
937 polarity = default_PCI_polarity(idx);
938 break;
939 case 1: /* high active */
940 {
941 polarity = 0;
942 break;
943 }
944 case 2: /* reserved */
945 {
946 printk(KERN_WARNING "broken BIOS!!\n");
947 polarity = 1;
948 break;
949 }
950 case 3: /* low active */
951 {
952 polarity = 1;
953 break;
954 }
955 default: /* invalid */
956 {
957 printk(KERN_WARNING "broken BIOS!!\n");
958 polarity = 1;
959 break;
960 }
961 }
962 return polarity;
963 }
964
965 static int MPBIOS_trigger(int idx)
966 {
967 int bus = mp_irqs[idx].srcbus;
968 int trigger;
969
970 /*
971 * Determine IRQ trigger mode (edge or level sensitive):
972 */
973 switch ((mp_irqs[idx].irqflag>>2) & 3)
974 {
975 case 0: /* conforms, ie. bus-type dependent */
976 if (test_bit(bus, mp_bus_not_pci))
977 trigger = default_ISA_trigger(idx);
978 else
979 trigger = default_PCI_trigger(idx);
980 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
981 switch (mp_bus_id_to_type[bus]) {
982 case MP_BUS_ISA: /* ISA pin */
983 {
984 /* set before the switch */
985 break;
986 }
987 case MP_BUS_EISA: /* EISA pin */
988 {
989 trigger = default_EISA_trigger(idx);
990 break;
991 }
992 case MP_BUS_PCI: /* PCI pin */
993 {
994 /* set before the switch */
995 break;
996 }
997 case MP_BUS_MCA: /* MCA pin */
998 {
999 trigger = default_MCA_trigger(idx);
1000 break;
1001 }
1002 default:
1003 {
1004 printk(KERN_WARNING "broken BIOS!!\n");
1005 trigger = 1;
1006 break;
1007 }
1008 }
1009 #endif
1010 break;
1011 case 1: /* edge */
1012 {
1013 trigger = 0;
1014 break;
1015 }
1016 case 2: /* reserved */
1017 {
1018 printk(KERN_WARNING "broken BIOS!!\n");
1019 trigger = 1;
1020 break;
1021 }
1022 case 3: /* level */
1023 {
1024 trigger = 1;
1025 break;
1026 }
1027 default: /* invalid */
1028 {
1029 printk(KERN_WARNING "broken BIOS!!\n");
1030 trigger = 0;
1031 break;
1032 }
1033 }
1034 return trigger;
1035 }
1036
1037 static inline int irq_polarity(int idx)
1038 {
1039 return MPBIOS_polarity(idx);
1040 }
1041
1042 static inline int irq_trigger(int idx)
1043 {
1044 return MPBIOS_trigger(idx);
1045 }
1046
1047 int (*ioapic_renumber_irq)(int ioapic, int irq);
1048 static int pin_2_irq(int idx, int apic, int pin)
1049 {
1050 int irq, i;
1051 int bus = mp_irqs[idx].srcbus;
1052
1053 /*
1054 * Debugging check, we are in big trouble if this message pops up!
1055 */
1056 if (mp_irqs[idx].dstirq != pin)
1057 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1058
1059 if (test_bit(bus, mp_bus_not_pci)) {
1060 irq = mp_irqs[idx].srcbusirq;
1061 } else {
1062 /*
1063 * PCI IRQs are mapped in order
1064 */
1065 i = irq = 0;
1066 while (i < apic)
1067 irq += nr_ioapic_registers[i++];
1068 irq += pin;
1069 /*
1070 * For MPS mode, so far only needed by ES7000 platform
1071 */
1072 if (ioapic_renumber_irq)
1073 irq = ioapic_renumber_irq(apic, irq);
1074 }
1075
1076 #ifdef CONFIG_X86_32
1077 /*
1078 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1079 */
1080 if ((pin >= 16) && (pin <= 23)) {
1081 if (pirq_entries[pin-16] != -1) {
1082 if (!pirq_entries[pin-16]) {
1083 apic_printk(APIC_VERBOSE, KERN_DEBUG
1084 "disabling PIRQ%d\n", pin-16);
1085 } else {
1086 irq = pirq_entries[pin-16];
1087 apic_printk(APIC_VERBOSE, KERN_DEBUG
1088 "using PIRQ%d -> IRQ %d\n",
1089 pin-16, irq);
1090 }
1091 }
1092 }
1093 #endif
1094
1095 return irq;
1096 }
1097
1098 /*
1099 * Find a specific PCI IRQ entry.
1100 * Not an __init, possibly needed by modules
1101 */
1102 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1103 struct io_apic_irq_attr *irq_attr)
1104 {
1105 int apic, i, best_guess = -1;
1106
1107 apic_printk(APIC_DEBUG,
1108 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1109 bus, slot, pin);
1110 if (test_bit(bus, mp_bus_not_pci)) {
1111 apic_printk(APIC_VERBOSE,
1112 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1113 return -1;
1114 }
1115 for (i = 0; i < mp_irq_entries; i++) {
1116 int lbus = mp_irqs[i].srcbus;
1117
1118 for (apic = 0; apic < nr_ioapics; apic++)
1119 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1120 mp_irqs[i].dstapic == MP_APIC_ALL)
1121 break;
1122
1123 if (!test_bit(lbus, mp_bus_not_pci) &&
1124 !mp_irqs[i].irqtype &&
1125 (bus == lbus) &&
1126 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1127 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1128
1129 if (!(apic || IO_APIC_IRQ(irq)))
1130 continue;
1131
1132 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1133 set_io_apic_irq_attr(irq_attr, apic,
1134 mp_irqs[i].dstirq,
1135 irq_trigger(i),
1136 irq_polarity(i));
1137 return irq;
1138 }
1139 /*
1140 * Use the first all-but-pin matching entry as a
1141 * best-guess fuzzy result for broken mptables.
1142 */
1143 if (best_guess < 0) {
1144 set_io_apic_irq_attr(irq_attr, apic,
1145 mp_irqs[i].dstirq,
1146 irq_trigger(i),
1147 irq_polarity(i));
1148 best_guess = irq;
1149 }
1150 }
1151 }
1152 return best_guess;
1153 }
1154 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1155
1156 void lock_vector_lock(void)
1157 {
1158 /* Used to the online set of cpus does not change
1159 * during assign_irq_vector.
1160 */
1161 spin_lock(&vector_lock);
1162 }
1163
1164 void unlock_vector_lock(void)
1165 {
1166 spin_unlock(&vector_lock);
1167 }
1168
1169 static int
1170 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1171 {
1172 /*
1173 * NOTE! The local APIC isn't very good at handling
1174 * multiple interrupts at the same interrupt level.
1175 * As the interrupt level is determined by taking the
1176 * vector number and shifting that right by 4, we
1177 * want to spread these out a bit so that they don't
1178 * all fall in the same interrupt level.
1179 *
1180 * Also, we've got to be careful not to trash gate
1181 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1182 */
1183 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1184 unsigned int old_vector;
1185 int cpu, err;
1186 cpumask_var_t tmp_mask;
1187
1188 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1189 return -EBUSY;
1190
1191 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1192 return -ENOMEM;
1193
1194 old_vector = cfg->vector;
1195 if (old_vector) {
1196 cpumask_and(tmp_mask, mask, cpu_online_mask);
1197 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1198 if (!cpumask_empty(tmp_mask)) {
1199 free_cpumask_var(tmp_mask);
1200 return 0;
1201 }
1202 }
1203
1204 /* Only try and allocate irqs on cpus that are present */
1205 err = -ENOSPC;
1206 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1207 int new_cpu;
1208 int vector, offset;
1209
1210 apic->vector_allocation_domain(cpu, tmp_mask);
1211
1212 vector = current_vector;
1213 offset = current_offset;
1214 next:
1215 vector += 8;
1216 if (vector >= first_system_vector) {
1217 /* If out of vectors on large boxen, must share them. */
1218 offset = (offset + 1) % 8;
1219 vector = FIRST_DEVICE_VECTOR + offset;
1220 }
1221 if (unlikely(current_vector == vector))
1222 continue;
1223
1224 if (test_bit(vector, used_vectors))
1225 goto next;
1226
1227 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1228 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1229 goto next;
1230 /* Found one! */
1231 current_vector = vector;
1232 current_offset = offset;
1233 if (old_vector) {
1234 cfg->move_in_progress = 1;
1235 cpumask_copy(cfg->old_domain, cfg->domain);
1236 }
1237 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1238 per_cpu(vector_irq, new_cpu)[vector] = irq;
1239 cfg->vector = vector;
1240 cpumask_copy(cfg->domain, tmp_mask);
1241 err = 0;
1242 break;
1243 }
1244 free_cpumask_var(tmp_mask);
1245 return err;
1246 }
1247
1248 static int
1249 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1250 {
1251 int err;
1252 unsigned long flags;
1253
1254 spin_lock_irqsave(&vector_lock, flags);
1255 err = __assign_irq_vector(irq, cfg, mask);
1256 spin_unlock_irqrestore(&vector_lock, flags);
1257 return err;
1258 }
1259
1260 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1261 {
1262 int cpu, vector;
1263
1264 BUG_ON(!cfg->vector);
1265
1266 vector = cfg->vector;
1267 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1268 per_cpu(vector_irq, cpu)[vector] = -1;
1269
1270 cfg->vector = 0;
1271 cpumask_clear(cfg->domain);
1272
1273 if (likely(!cfg->move_in_progress))
1274 return;
1275 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1276 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1277 vector++) {
1278 if (per_cpu(vector_irq, cpu)[vector] != irq)
1279 continue;
1280 per_cpu(vector_irq, cpu)[vector] = -1;
1281 break;
1282 }
1283 }
1284 cfg->move_in_progress = 0;
1285 }
1286
1287 void __setup_vector_irq(int cpu)
1288 {
1289 /* Initialize vector_irq on a new cpu */
1290 /* This function must be called with vector_lock held */
1291 int irq, vector;
1292 struct irq_cfg *cfg;
1293 struct irq_desc *desc;
1294
1295 /* Mark the inuse vectors */
1296 for_each_irq_desc(irq, desc) {
1297 cfg = desc->chip_data;
1298 if (!cpumask_test_cpu(cpu, cfg->domain))
1299 continue;
1300 vector = cfg->vector;
1301 per_cpu(vector_irq, cpu)[vector] = irq;
1302 }
1303 /* Mark the free vectors */
1304 for (vector = 0; vector < NR_VECTORS; ++vector) {
1305 irq = per_cpu(vector_irq, cpu)[vector];
1306 if (irq < 0)
1307 continue;
1308
1309 cfg = irq_cfg(irq);
1310 if (!cpumask_test_cpu(cpu, cfg->domain))
1311 per_cpu(vector_irq, cpu)[vector] = -1;
1312 }
1313 }
1314
1315 static struct irq_chip ioapic_chip;
1316 static struct irq_chip ir_ioapic_chip;
1317
1318 #define IOAPIC_AUTO -1
1319 #define IOAPIC_EDGE 0
1320 #define IOAPIC_LEVEL 1
1321
1322 #ifdef CONFIG_X86_32
1323 static inline int IO_APIC_irq_trigger(int irq)
1324 {
1325 int apic, idx, pin;
1326
1327 for (apic = 0; apic < nr_ioapics; apic++) {
1328 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1329 idx = find_irq_entry(apic, pin, mp_INT);
1330 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1331 return irq_trigger(idx);
1332 }
1333 }
1334 /*
1335 * nonexistent IRQs are edge default
1336 */
1337 return 0;
1338 }
1339 #else
1340 static inline int IO_APIC_irq_trigger(int irq)
1341 {
1342 return 1;
1343 }
1344 #endif
1345
1346 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1347 {
1348
1349 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1350 trigger == IOAPIC_LEVEL)
1351 desc->status |= IRQ_LEVEL;
1352 else
1353 desc->status &= ~IRQ_LEVEL;
1354
1355 if (irq_remapped(irq)) {
1356 desc->status |= IRQ_MOVE_PCNTXT;
1357 if (trigger)
1358 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1359 handle_fasteoi_irq,
1360 "fasteoi");
1361 else
1362 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1363 handle_edge_irq, "edge");
1364 return;
1365 }
1366
1367 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1368 trigger == IOAPIC_LEVEL)
1369 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1370 handle_fasteoi_irq,
1371 "fasteoi");
1372 else
1373 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1374 handle_edge_irq, "edge");
1375 }
1376
1377 int setup_ioapic_entry(int apic_id, int irq,
1378 struct IO_APIC_route_entry *entry,
1379 unsigned int destination, int trigger,
1380 int polarity, int vector, int pin)
1381 {
1382 /*
1383 * add it to the IO-APIC irq-routing table:
1384 */
1385 memset(entry,0,sizeof(*entry));
1386
1387 if (intr_remapping_enabled) {
1388 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1389 struct irte irte;
1390 struct IR_IO_APIC_route_entry *ir_entry =
1391 (struct IR_IO_APIC_route_entry *) entry;
1392 int index;
1393
1394 if (!iommu)
1395 panic("No mapping iommu for ioapic %d\n", apic_id);
1396
1397 index = alloc_irte(iommu, irq, 1);
1398 if (index < 0)
1399 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1400
1401 memset(&irte, 0, sizeof(irte));
1402
1403 irte.present = 1;
1404 irte.dst_mode = apic->irq_dest_mode;
1405 /*
1406 * Trigger mode in the IRTE will always be edge, and the
1407 * actual level or edge trigger will be setup in the IO-APIC
1408 * RTE. This will help simplify level triggered irq migration.
1409 * For more details, see the comments above explainig IO-APIC
1410 * irq migration in the presence of interrupt-remapping.
1411 */
1412 irte.trigger_mode = 0;
1413 irte.dlvry_mode = apic->irq_delivery_mode;
1414 irte.vector = vector;
1415 irte.dest_id = IRTE_DEST(destination);
1416
1417 /* Set source-id of interrupt request */
1418 set_ioapic_sid(&irte, apic_id);
1419
1420 modify_irte(irq, &irte);
1421
1422 ir_entry->index2 = (index >> 15) & 0x1;
1423 ir_entry->zero = 0;
1424 ir_entry->format = 1;
1425 ir_entry->index = (index & 0x7fff);
1426 /*
1427 * IO-APIC RTE will be configured with virtual vector.
1428 * irq handler will do the explicit EOI to the io-apic.
1429 */
1430 ir_entry->vector = pin;
1431 } else {
1432 entry->delivery_mode = apic->irq_delivery_mode;
1433 entry->dest_mode = apic->irq_dest_mode;
1434 entry->dest = destination;
1435 entry->vector = vector;
1436 }
1437
1438 entry->mask = 0; /* enable IRQ */
1439 entry->trigger = trigger;
1440 entry->polarity = polarity;
1441
1442 /* Mask level triggered irqs.
1443 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1444 */
1445 if (trigger)
1446 entry->mask = 1;
1447 return 0;
1448 }
1449
1450 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1451 int trigger, int polarity)
1452 {
1453 struct irq_cfg *cfg;
1454 struct IO_APIC_route_entry entry;
1455 unsigned int dest;
1456
1457 if (!IO_APIC_IRQ(irq))
1458 return;
1459
1460 cfg = desc->chip_data;
1461
1462 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1463 return;
1464
1465 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1466
1467 apic_printk(APIC_VERBOSE,KERN_DEBUG
1468 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1469 "IRQ %d Mode:%i Active:%i)\n",
1470 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1471 irq, trigger, polarity);
1472
1473
1474 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1475 dest, trigger, polarity, cfg->vector, pin)) {
1476 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1477 mp_ioapics[apic_id].apicid, pin);
1478 __clear_irq_vector(irq, cfg);
1479 return;
1480 }
1481
1482 ioapic_register_intr(irq, desc, trigger);
1483 if (irq < NR_IRQS_LEGACY)
1484 disable_8259A_irq(irq);
1485
1486 ioapic_write_entry(apic_id, pin, entry);
1487 }
1488
1489 static struct {
1490 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1491 } mp_ioapic_routing[MAX_IO_APICS];
1492
1493 static void __init setup_IO_APIC_irqs(void)
1494 {
1495 int apic_id = 0, pin, idx, irq;
1496 int notcon = 0;
1497 struct irq_desc *desc;
1498 struct irq_cfg *cfg;
1499 int node = cpu_to_node(boot_cpu_id);
1500
1501 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1502
1503 #ifdef CONFIG_ACPI
1504 if (!acpi_disabled && acpi_ioapic) {
1505 apic_id = mp_find_ioapic(0);
1506 if (apic_id < 0)
1507 apic_id = 0;
1508 }
1509 #endif
1510
1511 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1512 idx = find_irq_entry(apic_id, pin, mp_INT);
1513 if (idx == -1) {
1514 if (!notcon) {
1515 notcon = 1;
1516 apic_printk(APIC_VERBOSE,
1517 KERN_DEBUG " %d-%d",
1518 mp_ioapics[apic_id].apicid, pin);
1519 } else
1520 apic_printk(APIC_VERBOSE, " %d-%d",
1521 mp_ioapics[apic_id].apicid, pin);
1522 continue;
1523 }
1524 if (notcon) {
1525 apic_printk(APIC_VERBOSE,
1526 " (apicid-pin) not connected\n");
1527 notcon = 0;
1528 }
1529
1530 irq = pin_2_irq(idx, apic_id, pin);
1531
1532 /*
1533 * Skip the timer IRQ if there's a quirk handler
1534 * installed and if it returns 1:
1535 */
1536 if (apic->multi_timer_check &&
1537 apic->multi_timer_check(apic_id, irq))
1538 continue;
1539
1540 desc = irq_to_desc_alloc_node(irq, node);
1541 if (!desc) {
1542 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1543 continue;
1544 }
1545 cfg = desc->chip_data;
1546 add_pin_to_irq_node(cfg, node, apic_id, pin);
1547 /*
1548 * don't mark it in pin_programmed, so later acpi could
1549 * set it correctly when irq < 16
1550 */
1551 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1552 irq_trigger(idx), irq_polarity(idx));
1553 }
1554
1555 if (notcon)
1556 apic_printk(APIC_VERBOSE,
1557 " (apicid-pin) not connected\n");
1558 }
1559
1560 /*
1561 * for the gsit that is not in first ioapic
1562 * but could not use acpi_register_gsi()
1563 * like some special sci in IBM x3330
1564 */
1565 void setup_IO_APIC_irq_extra(u32 gsi)
1566 {
1567 int apic_id = 0, pin, idx, irq;
1568 int node = cpu_to_node(boot_cpu_id);
1569 struct irq_desc *desc;
1570 struct irq_cfg *cfg;
1571
1572 /*
1573 * Convert 'gsi' to 'ioapic.pin'.
1574 */
1575 apic_id = mp_find_ioapic(gsi);
1576 if (apic_id < 0)
1577 return;
1578
1579 pin = mp_find_ioapic_pin(apic_id, gsi);
1580 idx = find_irq_entry(apic_id, pin, mp_INT);
1581 if (idx == -1)
1582 return;
1583
1584 irq = pin_2_irq(idx, apic_id, pin);
1585 #ifdef CONFIG_SPARSE_IRQ
1586 desc = irq_to_desc(irq);
1587 if (desc)
1588 return;
1589 #endif
1590 desc = irq_to_desc_alloc_node(irq, node);
1591 if (!desc) {
1592 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1593 return;
1594 }
1595
1596 cfg = desc->chip_data;
1597 add_pin_to_irq_node(cfg, node, apic_id, pin);
1598
1599 if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
1600 pr_debug("Pin %d-%d already programmed\n",
1601 mp_ioapics[apic_id].apicid, pin);
1602 return;
1603 }
1604 set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
1605
1606 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1607 irq_trigger(idx), irq_polarity(idx));
1608 }
1609
1610 /*
1611 * Set up the timer pin, possibly with the 8259A-master behind.
1612 */
1613 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1614 int vector)
1615 {
1616 struct IO_APIC_route_entry entry;
1617
1618 if (intr_remapping_enabled)
1619 return;
1620
1621 memset(&entry, 0, sizeof(entry));
1622
1623 /*
1624 * We use logical delivery to get the timer IRQ
1625 * to the first CPU.
1626 */
1627 entry.dest_mode = apic->irq_dest_mode;
1628 entry.mask = 0; /* don't mask IRQ for edge */
1629 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1630 entry.delivery_mode = apic->irq_delivery_mode;
1631 entry.polarity = 0;
1632 entry.trigger = 0;
1633 entry.vector = vector;
1634
1635 /*
1636 * The timer IRQ doesn't have to know that behind the
1637 * scene we may have a 8259A-master in AEOI mode ...
1638 */
1639 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1640
1641 /*
1642 * Add it to the IO-APIC irq-routing table:
1643 */
1644 ioapic_write_entry(apic_id, pin, entry);
1645 }
1646
1647
1648 __apicdebuginit(void) print_IO_APIC(void)
1649 {
1650 int apic, i;
1651 union IO_APIC_reg_00 reg_00;
1652 union IO_APIC_reg_01 reg_01;
1653 union IO_APIC_reg_02 reg_02;
1654 union IO_APIC_reg_03 reg_03;
1655 unsigned long flags;
1656 struct irq_cfg *cfg;
1657 struct irq_desc *desc;
1658 unsigned int irq;
1659
1660 if (apic_verbosity == APIC_QUIET)
1661 return;
1662
1663 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1664 for (i = 0; i < nr_ioapics; i++)
1665 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1666 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1667
1668 /*
1669 * We are a bit conservative about what we expect. We have to
1670 * know about every hardware change ASAP.
1671 */
1672 printk(KERN_INFO "testing the IO APIC.......................\n");
1673
1674 for (apic = 0; apic < nr_ioapics; apic++) {
1675
1676 spin_lock_irqsave(&ioapic_lock, flags);
1677 reg_00.raw = io_apic_read(apic, 0);
1678 reg_01.raw = io_apic_read(apic, 1);
1679 if (reg_01.bits.version >= 0x10)
1680 reg_02.raw = io_apic_read(apic, 2);
1681 if (reg_01.bits.version >= 0x20)
1682 reg_03.raw = io_apic_read(apic, 3);
1683 spin_unlock_irqrestore(&ioapic_lock, flags);
1684
1685 printk("\n");
1686 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1687 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1688 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1689 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1690 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1691
1692 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1693 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1694
1695 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1696 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1697
1698 /*
1699 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1700 * but the value of reg_02 is read as the previous read register
1701 * value, so ignore it if reg_02 == reg_01.
1702 */
1703 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1704 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1705 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1706 }
1707
1708 /*
1709 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1710 * or reg_03, but the value of reg_0[23] is read as the previous read
1711 * register value, so ignore it if reg_03 == reg_0[12].
1712 */
1713 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1714 reg_03.raw != reg_01.raw) {
1715 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1716 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1717 }
1718
1719 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1720
1721 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1722 " Stat Dmod Deli Vect: \n");
1723
1724 for (i = 0; i <= reg_01.bits.entries; i++) {
1725 struct IO_APIC_route_entry entry;
1726
1727 entry = ioapic_read_entry(apic, i);
1728
1729 printk(KERN_DEBUG " %02x %03X ",
1730 i,
1731 entry.dest
1732 );
1733
1734 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1735 entry.mask,
1736 entry.trigger,
1737 entry.irr,
1738 entry.polarity,
1739 entry.delivery_status,
1740 entry.dest_mode,
1741 entry.delivery_mode,
1742 entry.vector
1743 );
1744 }
1745 }
1746 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1747 for_each_irq_desc(irq, desc) {
1748 struct irq_pin_list *entry;
1749
1750 cfg = desc->chip_data;
1751 entry = cfg->irq_2_pin;
1752 if (!entry)
1753 continue;
1754 printk(KERN_DEBUG "IRQ%d ", irq);
1755 for (;;) {
1756 printk("-> %d:%d", entry->apic, entry->pin);
1757 if (!entry->next)
1758 break;
1759 entry = entry->next;
1760 }
1761 printk("\n");
1762 }
1763
1764 printk(KERN_INFO ".................................... done.\n");
1765
1766 return;
1767 }
1768
1769 __apicdebuginit(void) print_APIC_field(int base)
1770 {
1771 int i;
1772
1773 if (apic_verbosity == APIC_QUIET)
1774 return;
1775
1776 printk(KERN_DEBUG);
1777
1778 for (i = 0; i < 8; i++)
1779 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1780
1781 printk(KERN_CONT "\n");
1782 }
1783
1784 __apicdebuginit(void) print_local_APIC(void *dummy)
1785 {
1786 unsigned int i, v, ver, maxlvt;
1787 u64 icr;
1788
1789 if (apic_verbosity == APIC_QUIET)
1790 return;
1791
1792 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1793 smp_processor_id(), hard_smp_processor_id());
1794 v = apic_read(APIC_ID);
1795 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1796 v = apic_read(APIC_LVR);
1797 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1798 ver = GET_APIC_VERSION(v);
1799 maxlvt = lapic_get_maxlvt();
1800
1801 v = apic_read(APIC_TASKPRI);
1802 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1803
1804 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1805 if (!APIC_XAPIC(ver)) {
1806 v = apic_read(APIC_ARBPRI);
1807 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1808 v & APIC_ARBPRI_MASK);
1809 }
1810 v = apic_read(APIC_PROCPRI);
1811 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1812 }
1813
1814 /*
1815 * Remote read supported only in the 82489DX and local APIC for
1816 * Pentium processors.
1817 */
1818 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1819 v = apic_read(APIC_RRR);
1820 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1821 }
1822
1823 v = apic_read(APIC_LDR);
1824 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1825 if (!x2apic_enabled()) {
1826 v = apic_read(APIC_DFR);
1827 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1828 }
1829 v = apic_read(APIC_SPIV);
1830 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1831
1832 printk(KERN_DEBUG "... APIC ISR field:\n");
1833 print_APIC_field(APIC_ISR);
1834 printk(KERN_DEBUG "... APIC TMR field:\n");
1835 print_APIC_field(APIC_TMR);
1836 printk(KERN_DEBUG "... APIC IRR field:\n");
1837 print_APIC_field(APIC_IRR);
1838
1839 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1840 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1841 apic_write(APIC_ESR, 0);
1842
1843 v = apic_read(APIC_ESR);
1844 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1845 }
1846
1847 icr = apic_icr_read();
1848 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1849 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1850
1851 v = apic_read(APIC_LVTT);
1852 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1853
1854 if (maxlvt > 3) { /* PC is LVT#4. */
1855 v = apic_read(APIC_LVTPC);
1856 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1857 }
1858 v = apic_read(APIC_LVT0);
1859 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1860 v = apic_read(APIC_LVT1);
1861 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1862
1863 if (maxlvt > 2) { /* ERR is LVT#3. */
1864 v = apic_read(APIC_LVTERR);
1865 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1866 }
1867
1868 v = apic_read(APIC_TMICT);
1869 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1870 v = apic_read(APIC_TMCCT);
1871 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1872 v = apic_read(APIC_TDCR);
1873 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1874
1875 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1876 v = apic_read(APIC_EFEAT);
1877 maxlvt = (v >> 16) & 0xff;
1878 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1879 v = apic_read(APIC_ECTRL);
1880 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1881 for (i = 0; i < maxlvt; i++) {
1882 v = apic_read(APIC_EILVTn(i));
1883 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1884 }
1885 }
1886 printk("\n");
1887 }
1888
1889 __apicdebuginit(void) print_all_local_APICs(void)
1890 {
1891 int cpu;
1892
1893 preempt_disable();
1894 for_each_online_cpu(cpu)
1895 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1896 preempt_enable();
1897 }
1898
1899 __apicdebuginit(void) print_PIC(void)
1900 {
1901 unsigned int v;
1902 unsigned long flags;
1903
1904 if (apic_verbosity == APIC_QUIET)
1905 return;
1906
1907 printk(KERN_DEBUG "\nprinting PIC contents\n");
1908
1909 spin_lock_irqsave(&i8259A_lock, flags);
1910
1911 v = inb(0xa1) << 8 | inb(0x21);
1912 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1913
1914 v = inb(0xa0) << 8 | inb(0x20);
1915 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1916
1917 outb(0x0b,0xa0);
1918 outb(0x0b,0x20);
1919 v = inb(0xa0) << 8 | inb(0x20);
1920 outb(0x0a,0xa0);
1921 outb(0x0a,0x20);
1922
1923 spin_unlock_irqrestore(&i8259A_lock, flags);
1924
1925 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1926
1927 v = inb(0x4d1) << 8 | inb(0x4d0);
1928 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1929 }
1930
1931 __apicdebuginit(int) print_all_ICs(void)
1932 {
1933 print_PIC();
1934
1935 /* don't print out if apic is not there */
1936 if (!cpu_has_apic || disable_apic)
1937 return 0;
1938
1939 print_all_local_APICs();
1940 print_IO_APIC();
1941
1942 return 0;
1943 }
1944
1945 fs_initcall(print_all_ICs);
1946
1947
1948 /* Where if anywhere is the i8259 connect in external int mode */
1949 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1950
1951 void __init enable_IO_APIC(void)
1952 {
1953 union IO_APIC_reg_01 reg_01;
1954 int i8259_apic, i8259_pin;
1955 int apic;
1956 unsigned long flags;
1957
1958 /*
1959 * The number of IO-APIC IRQ registers (== #pins):
1960 */
1961 for (apic = 0; apic < nr_ioapics; apic++) {
1962 spin_lock_irqsave(&ioapic_lock, flags);
1963 reg_01.raw = io_apic_read(apic, 1);
1964 spin_unlock_irqrestore(&ioapic_lock, flags);
1965 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1966 }
1967 for(apic = 0; apic < nr_ioapics; apic++) {
1968 int pin;
1969 /* See if any of the pins is in ExtINT mode */
1970 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1971 struct IO_APIC_route_entry entry;
1972 entry = ioapic_read_entry(apic, pin);
1973
1974 /* If the interrupt line is enabled and in ExtInt mode
1975 * I have found the pin where the i8259 is connected.
1976 */
1977 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1978 ioapic_i8259.apic = apic;
1979 ioapic_i8259.pin = pin;
1980 goto found_i8259;
1981 }
1982 }
1983 }
1984 found_i8259:
1985 /* Look to see what if the MP table has reported the ExtINT */
1986 /* If we could not find the appropriate pin by looking at the ioapic
1987 * the i8259 probably is not connected the ioapic but give the
1988 * mptable a chance anyway.
1989 */
1990 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1991 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1992 /* Trust the MP table if nothing is setup in the hardware */
1993 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1994 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1995 ioapic_i8259.pin = i8259_pin;
1996 ioapic_i8259.apic = i8259_apic;
1997 }
1998 /* Complain if the MP table and the hardware disagree */
1999 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2000 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2001 {
2002 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2003 }
2004
2005 /*
2006 * Do not trust the IO-APIC being empty at bootup
2007 */
2008 clear_IO_APIC();
2009 }
2010
2011 /*
2012 * Not an __init, needed by the reboot code
2013 */
2014 void disable_IO_APIC(void)
2015 {
2016 /*
2017 * Clear the IO-APIC before rebooting:
2018 */
2019 clear_IO_APIC();
2020
2021 /*
2022 * If the i8259 is routed through an IOAPIC
2023 * Put that IOAPIC in virtual wire mode
2024 * so legacy interrupts can be delivered.
2025 *
2026 * With interrupt-remapping, for now we will use virtual wire A mode,
2027 * as virtual wire B is little complex (need to configure both
2028 * IOAPIC RTE aswell as interrupt-remapping table entry).
2029 * As this gets called during crash dump, keep this simple for now.
2030 */
2031 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2032 struct IO_APIC_route_entry entry;
2033
2034 memset(&entry, 0, sizeof(entry));
2035 entry.mask = 0; /* Enabled */
2036 entry.trigger = 0; /* Edge */
2037 entry.irr = 0;
2038 entry.polarity = 0; /* High */
2039 entry.delivery_status = 0;
2040 entry.dest_mode = 0; /* Physical */
2041 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2042 entry.vector = 0;
2043 entry.dest = read_apic_id();
2044
2045 /*
2046 * Add it to the IO-APIC irq-routing table:
2047 */
2048 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2049 }
2050
2051 /*
2052 * Use virtual wire A mode when interrupt remapping is enabled.
2053 */
2054 if (cpu_has_apic)
2055 disconnect_bsp_APIC(!intr_remapping_enabled &&
2056 ioapic_i8259.pin != -1);
2057 }
2058
2059 #ifdef CONFIG_X86_32
2060 /*
2061 * function to set the IO-APIC physical IDs based on the
2062 * values stored in the MPC table.
2063 *
2064 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2065 */
2066
2067 static void __init setup_ioapic_ids_from_mpc(void)
2068 {
2069 union IO_APIC_reg_00 reg_00;
2070 physid_mask_t phys_id_present_map;
2071 int apic_id;
2072 int i;
2073 unsigned char old_id;
2074 unsigned long flags;
2075
2076 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2077 return;
2078
2079 /*
2080 * Don't check I/O APIC IDs for xAPIC systems. They have
2081 * no meaning without the serial APIC bus.
2082 */
2083 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2084 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2085 return;
2086 /*
2087 * This is broken; anything with a real cpu count has to
2088 * circumvent this idiocy regardless.
2089 */
2090 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2091
2092 /*
2093 * Set the IOAPIC ID to the value stored in the MPC table.
2094 */
2095 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2096
2097 /* Read the register 0 value */
2098 spin_lock_irqsave(&ioapic_lock, flags);
2099 reg_00.raw = io_apic_read(apic_id, 0);
2100 spin_unlock_irqrestore(&ioapic_lock, flags);
2101
2102 old_id = mp_ioapics[apic_id].apicid;
2103
2104 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2105 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2106 apic_id, mp_ioapics[apic_id].apicid);
2107 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2108 reg_00.bits.ID);
2109 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2110 }
2111
2112 /*
2113 * Sanity check, is the ID really free? Every APIC in a
2114 * system must have a unique ID or we get lots of nice
2115 * 'stuck on smp_invalidate_needed IPI wait' messages.
2116 */
2117 if (apic->check_apicid_used(phys_id_present_map,
2118 mp_ioapics[apic_id].apicid)) {
2119 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2120 apic_id, mp_ioapics[apic_id].apicid);
2121 for (i = 0; i < get_physical_broadcast(); i++)
2122 if (!physid_isset(i, phys_id_present_map))
2123 break;
2124 if (i >= get_physical_broadcast())
2125 panic("Max APIC ID exceeded!\n");
2126 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2127 i);
2128 physid_set(i, phys_id_present_map);
2129 mp_ioapics[apic_id].apicid = i;
2130 } else {
2131 physid_mask_t tmp;
2132 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2133 apic_printk(APIC_VERBOSE, "Setting %d in the "
2134 "phys_id_present_map\n",
2135 mp_ioapics[apic_id].apicid);
2136 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2137 }
2138
2139
2140 /*
2141 * We need to adjust the IRQ routing table
2142 * if the ID changed.
2143 */
2144 if (old_id != mp_ioapics[apic_id].apicid)
2145 for (i = 0; i < mp_irq_entries; i++)
2146 if (mp_irqs[i].dstapic == old_id)
2147 mp_irqs[i].dstapic
2148 = mp_ioapics[apic_id].apicid;
2149
2150 /*
2151 * Read the right value from the MPC table and
2152 * write it into the ID register.
2153 */
2154 apic_printk(APIC_VERBOSE, KERN_INFO
2155 "...changing IO-APIC physical APIC ID to %d ...",
2156 mp_ioapics[apic_id].apicid);
2157
2158 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2159 spin_lock_irqsave(&ioapic_lock, flags);
2160 io_apic_write(apic_id, 0, reg_00.raw);
2161 spin_unlock_irqrestore(&ioapic_lock, flags);
2162
2163 /*
2164 * Sanity check
2165 */
2166 spin_lock_irqsave(&ioapic_lock, flags);
2167 reg_00.raw = io_apic_read(apic_id, 0);
2168 spin_unlock_irqrestore(&ioapic_lock, flags);
2169 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2170 printk("could not set ID!\n");
2171 else
2172 apic_printk(APIC_VERBOSE, " ok.\n");
2173 }
2174 }
2175 #endif
2176
2177 int no_timer_check __initdata;
2178
2179 static int __init notimercheck(char *s)
2180 {
2181 no_timer_check = 1;
2182 return 1;
2183 }
2184 __setup("no_timer_check", notimercheck);
2185
2186 /*
2187 * There is a nasty bug in some older SMP boards, their mptable lies
2188 * about the timer IRQ. We do the following to work around the situation:
2189 *
2190 * - timer IRQ defaults to IO-APIC IRQ
2191 * - if this function detects that timer IRQs are defunct, then we fall
2192 * back to ISA timer IRQs
2193 */
2194 static int __init timer_irq_works(void)
2195 {
2196 unsigned long t1 = jiffies;
2197 unsigned long flags;
2198
2199 if (no_timer_check)
2200 return 1;
2201
2202 local_save_flags(flags);
2203 local_irq_enable();
2204 /* Let ten ticks pass... */
2205 mdelay((10 * 1000) / HZ);
2206 local_irq_restore(flags);
2207
2208 /*
2209 * Expect a few ticks at least, to be sure some possible
2210 * glue logic does not lock up after one or two first
2211 * ticks in a non-ExtINT mode. Also the local APIC
2212 * might have cached one ExtINT interrupt. Finally, at
2213 * least one tick may be lost due to delays.
2214 */
2215
2216 /* jiffies wrap? */
2217 if (time_after(jiffies, t1 + 4))
2218 return 1;
2219 return 0;
2220 }
2221
2222 /*
2223 * In the SMP+IOAPIC case it might happen that there are an unspecified
2224 * number of pending IRQ events unhandled. These cases are very rare,
2225 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2226 * better to do it this way as thus we do not have to be aware of
2227 * 'pending' interrupts in the IRQ path, except at this point.
2228 */
2229 /*
2230 * Edge triggered needs to resend any interrupt
2231 * that was delayed but this is now handled in the device
2232 * independent code.
2233 */
2234
2235 /*
2236 * Starting up a edge-triggered IO-APIC interrupt is
2237 * nasty - we need to make sure that we get the edge.
2238 * If it is already asserted for some reason, we need
2239 * return 1 to indicate that is was pending.
2240 *
2241 * This is not complete - we should be able to fake
2242 * an edge even if it isn't on the 8259A...
2243 */
2244
2245 static unsigned int startup_ioapic_irq(unsigned int irq)
2246 {
2247 int was_pending = 0;
2248 unsigned long flags;
2249 struct irq_cfg *cfg;
2250
2251 spin_lock_irqsave(&ioapic_lock, flags);
2252 if (irq < NR_IRQS_LEGACY) {
2253 disable_8259A_irq(irq);
2254 if (i8259A_irq_pending(irq))
2255 was_pending = 1;
2256 }
2257 cfg = irq_cfg(irq);
2258 __unmask_IO_APIC_irq(cfg);
2259 spin_unlock_irqrestore(&ioapic_lock, flags);
2260
2261 return was_pending;
2262 }
2263
2264 #ifdef CONFIG_X86_64
2265 static int ioapic_retrigger_irq(unsigned int irq)
2266 {
2267
2268 struct irq_cfg *cfg = irq_cfg(irq);
2269 unsigned long flags;
2270
2271 spin_lock_irqsave(&vector_lock, flags);
2272 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2273 spin_unlock_irqrestore(&vector_lock, flags);
2274
2275 return 1;
2276 }
2277 #else
2278 static int ioapic_retrigger_irq(unsigned int irq)
2279 {
2280 apic->send_IPI_self(irq_cfg(irq)->vector);
2281
2282 return 1;
2283 }
2284 #endif
2285
2286 /*
2287 * Level and edge triggered IO-APIC interrupts need different handling,
2288 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2289 * handled with the level-triggered descriptor, but that one has slightly
2290 * more overhead. Level-triggered interrupts cannot be handled with the
2291 * edge-triggered handler, without risking IRQ storms and other ugly
2292 * races.
2293 */
2294
2295 #ifdef CONFIG_SMP
2296 static void send_cleanup_vector(struct irq_cfg *cfg)
2297 {
2298 cpumask_var_t cleanup_mask;
2299
2300 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2301 unsigned int i;
2302 cfg->move_cleanup_count = 0;
2303 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2304 cfg->move_cleanup_count++;
2305 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2306 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2307 } else {
2308 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2309 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
2310 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2311 free_cpumask_var(cleanup_mask);
2312 }
2313 cfg->move_in_progress = 0;
2314 }
2315
2316 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2317 {
2318 int apic, pin;
2319 struct irq_pin_list *entry;
2320 u8 vector = cfg->vector;
2321
2322 entry = cfg->irq_2_pin;
2323 for (;;) {
2324 unsigned int reg;
2325
2326 if (!entry)
2327 break;
2328
2329 apic = entry->apic;
2330 pin = entry->pin;
2331 /*
2332 * With interrupt-remapping, destination information comes
2333 * from interrupt-remapping table entry.
2334 */
2335 if (!irq_remapped(irq))
2336 io_apic_write(apic, 0x11 + pin*2, dest);
2337 reg = io_apic_read(apic, 0x10 + pin*2);
2338 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2339 reg |= vector;
2340 io_apic_modify(apic, 0x10 + pin*2, reg);
2341 if (!entry->next)
2342 break;
2343 entry = entry->next;
2344 }
2345 }
2346
2347 static int
2348 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
2349
2350 /*
2351 * Either sets desc->affinity to a valid value, and returns
2352 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2353 * leaves desc->affinity untouched.
2354 */
2355 static unsigned int
2356 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
2357 {
2358 struct irq_cfg *cfg;
2359 unsigned int irq;
2360
2361 if (!cpumask_intersects(mask, cpu_online_mask))
2362 return BAD_APICID;
2363
2364 irq = desc->irq;
2365 cfg = desc->chip_data;
2366 if (assign_irq_vector(irq, cfg, mask))
2367 return BAD_APICID;
2368
2369 cpumask_copy(desc->affinity, mask);
2370
2371 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2372 }
2373
2374 static int
2375 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2376 {
2377 struct irq_cfg *cfg;
2378 unsigned long flags;
2379 unsigned int dest;
2380 unsigned int irq;
2381 int ret = -1;
2382
2383 irq = desc->irq;
2384 cfg = desc->chip_data;
2385
2386 spin_lock_irqsave(&ioapic_lock, flags);
2387 dest = set_desc_affinity(desc, mask);
2388 if (dest != BAD_APICID) {
2389 /* Only the high 8 bits are valid. */
2390 dest = SET_APIC_LOGICAL_ID(dest);
2391 __target_IO_APIC_irq(irq, dest, cfg);
2392 ret = 0;
2393 }
2394 spin_unlock_irqrestore(&ioapic_lock, flags);
2395
2396 return ret;
2397 }
2398
2399 static int
2400 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2401 {
2402 struct irq_desc *desc;
2403
2404 desc = irq_to_desc(irq);
2405
2406 return set_ioapic_affinity_irq_desc(desc, mask);
2407 }
2408
2409 #ifdef CONFIG_INTR_REMAP
2410
2411 /*
2412 * Migrate the IO-APIC irq in the presence of intr-remapping.
2413 *
2414 * For both level and edge triggered, irq migration is a simple atomic
2415 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2416 *
2417 * For level triggered, we eliminate the io-apic RTE modification (with the
2418 * updated vector information), by using a virtual vector (io-apic pin number).
2419 * Real vector that is used for interrupting cpu will be coming from
2420 * the interrupt-remapping table entry.
2421 */
2422 static int
2423 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2424 {
2425 struct irq_cfg *cfg;
2426 struct irte irte;
2427 unsigned int dest;
2428 unsigned int irq;
2429 int ret = -1;
2430
2431 if (!cpumask_intersects(mask, cpu_online_mask))
2432 return ret;
2433
2434 irq = desc->irq;
2435 if (get_irte(irq, &irte))
2436 return ret;
2437
2438 cfg = desc->chip_data;
2439 if (assign_irq_vector(irq, cfg, mask))
2440 return ret;
2441
2442 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2443
2444 irte.vector = cfg->vector;
2445 irte.dest_id = IRTE_DEST(dest);
2446
2447 /*
2448 * Modified the IRTE and flushes the Interrupt entry cache.
2449 */
2450 modify_irte(irq, &irte);
2451
2452 if (cfg->move_in_progress)
2453 send_cleanup_vector(cfg);
2454
2455 cpumask_copy(desc->affinity, mask);
2456
2457 return 0;
2458 }
2459
2460 /*
2461 * Migrates the IRQ destination in the process context.
2462 */
2463 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2464 const struct cpumask *mask)
2465 {
2466 return migrate_ioapic_irq_desc(desc, mask);
2467 }
2468 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2469 const struct cpumask *mask)
2470 {
2471 struct irq_desc *desc = irq_to_desc(irq);
2472
2473 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2474 }
2475 #else
2476 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2477 const struct cpumask *mask)
2478 {
2479 return 0;
2480 }
2481 #endif
2482
2483 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2484 {
2485 unsigned vector, me;
2486
2487 ack_APIC_irq();
2488 exit_idle();
2489 irq_enter();
2490
2491 me = smp_processor_id();
2492 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2493 unsigned int irq;
2494 unsigned int irr;
2495 struct irq_desc *desc;
2496 struct irq_cfg *cfg;
2497 irq = __get_cpu_var(vector_irq)[vector];
2498
2499 if (irq == -1)
2500 continue;
2501
2502 desc = irq_to_desc(irq);
2503 if (!desc)
2504 continue;
2505
2506 cfg = irq_cfg(irq);
2507 spin_lock(&desc->lock);
2508 if (!cfg->move_cleanup_count)
2509 goto unlock;
2510
2511 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2512 goto unlock;
2513
2514 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2515 /*
2516 * Check if the vector that needs to be cleanedup is
2517 * registered at the cpu's IRR. If so, then this is not
2518 * the best time to clean it up. Lets clean it up in the
2519 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2520 * to myself.
2521 */
2522 if (irr & (1 << (vector % 32))) {
2523 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2524 goto unlock;
2525 }
2526 __get_cpu_var(vector_irq)[vector] = -1;
2527 cfg->move_cleanup_count--;
2528 unlock:
2529 spin_unlock(&desc->lock);
2530 }
2531
2532 irq_exit();
2533 }
2534
2535 static void irq_complete_move(struct irq_desc **descp)
2536 {
2537 struct irq_desc *desc = *descp;
2538 struct irq_cfg *cfg = desc->chip_data;
2539 unsigned vector, me;
2540
2541 if (likely(!cfg->move_in_progress))
2542 return;
2543
2544 vector = ~get_irq_regs()->orig_ax;
2545 me = smp_processor_id();
2546
2547 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2548 send_cleanup_vector(cfg);
2549 }
2550 #else
2551 static inline void irq_complete_move(struct irq_desc **descp) {}
2552 #endif
2553
2554 static void ack_apic_edge(unsigned int irq)
2555 {
2556 struct irq_desc *desc = irq_to_desc(irq);
2557
2558 irq_complete_move(&desc);
2559 move_native_irq(irq);
2560 ack_APIC_irq();
2561 }
2562
2563 atomic_t irq_mis_count;
2564
2565 static void ack_apic_level(unsigned int irq)
2566 {
2567 struct irq_desc *desc = irq_to_desc(irq);
2568
2569 #ifdef CONFIG_X86_32
2570 unsigned long v;
2571 int i;
2572 #endif
2573 struct irq_cfg *cfg;
2574 int do_unmask_irq = 0;
2575
2576 irq_complete_move(&desc);
2577 #ifdef CONFIG_GENERIC_PENDING_IRQ
2578 /* If we are moving the irq we need to mask it */
2579 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2580 do_unmask_irq = 1;
2581 mask_IO_APIC_irq_desc(desc);
2582 }
2583 #endif
2584
2585 #ifdef CONFIG_X86_32
2586 /*
2587 * It appears there is an erratum which affects at least version 0x11
2588 * of I/O APIC (that's the 82093AA and cores integrated into various
2589 * chipsets). Under certain conditions a level-triggered interrupt is
2590 * erroneously delivered as edge-triggered one but the respective IRR
2591 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2592 * message but it will never arrive and further interrupts are blocked
2593 * from the source. The exact reason is so far unknown, but the
2594 * phenomenon was observed when two consecutive interrupt requests
2595 * from a given source get delivered to the same CPU and the source is
2596 * temporarily disabled in between.
2597 *
2598 * A workaround is to simulate an EOI message manually. We achieve it
2599 * by setting the trigger mode to edge and then to level when the edge
2600 * trigger mode gets detected in the TMR of a local APIC for a
2601 * level-triggered interrupt. We mask the source for the time of the
2602 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2603 * The idea is from Manfred Spraul. --macro
2604 */
2605 cfg = desc->chip_data;
2606 i = cfg->vector;
2607
2608 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2609 #endif
2610
2611 /*
2612 * We must acknowledge the irq before we move it or the acknowledge will
2613 * not propagate properly.
2614 */
2615 ack_APIC_irq();
2616
2617 /* Now we can move and renable the irq */
2618 if (unlikely(do_unmask_irq)) {
2619 /* Only migrate the irq if the ack has been received.
2620 *
2621 * On rare occasions the broadcast level triggered ack gets
2622 * delayed going to ioapics, and if we reprogram the
2623 * vector while Remote IRR is still set the irq will never
2624 * fire again.
2625 *
2626 * To prevent this scenario we read the Remote IRR bit
2627 * of the ioapic. This has two effects.
2628 * - On any sane system the read of the ioapic will
2629 * flush writes (and acks) going to the ioapic from
2630 * this cpu.
2631 * - We get to see if the ACK has actually been delivered.
2632 *
2633 * Based on failed experiments of reprogramming the
2634 * ioapic entry from outside of irq context starting
2635 * with masking the ioapic entry and then polling until
2636 * Remote IRR was clear before reprogramming the
2637 * ioapic I don't trust the Remote IRR bit to be
2638 * completey accurate.
2639 *
2640 * However there appears to be no other way to plug
2641 * this race, so if the Remote IRR bit is not
2642 * accurate and is causing problems then it is a hardware bug
2643 * and you can go talk to the chipset vendor about it.
2644 */
2645 cfg = desc->chip_data;
2646 if (!io_apic_level_ack_pending(cfg))
2647 move_masked_irq(irq);
2648 unmask_IO_APIC_irq_desc(desc);
2649 }
2650
2651 #ifdef CONFIG_X86_32
2652 if (!(v & (1 << (i & 0x1f)))) {
2653 atomic_inc(&irq_mis_count);
2654 spin_lock(&ioapic_lock);
2655 __mask_and_edge_IO_APIC_irq(cfg);
2656 __unmask_and_level_IO_APIC_irq(cfg);
2657 spin_unlock(&ioapic_lock);
2658 }
2659 #endif
2660 }
2661
2662 #ifdef CONFIG_INTR_REMAP
2663 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2664 {
2665 int apic, pin;
2666 struct irq_pin_list *entry;
2667
2668 entry = cfg->irq_2_pin;
2669 for (;;) {
2670
2671 if (!entry)
2672 break;
2673
2674 apic = entry->apic;
2675 pin = entry->pin;
2676 io_apic_eoi(apic, pin);
2677 entry = entry->next;
2678 }
2679 }
2680
2681 static void
2682 eoi_ioapic_irq(struct irq_desc *desc)
2683 {
2684 struct irq_cfg *cfg;
2685 unsigned long flags;
2686 unsigned int irq;
2687
2688 irq = desc->irq;
2689 cfg = desc->chip_data;
2690
2691 spin_lock_irqsave(&ioapic_lock, flags);
2692 __eoi_ioapic_irq(irq, cfg);
2693 spin_unlock_irqrestore(&ioapic_lock, flags);
2694 }
2695
2696 static void ir_ack_apic_edge(unsigned int irq)
2697 {
2698 ack_APIC_irq();
2699 }
2700
2701 static void ir_ack_apic_level(unsigned int irq)
2702 {
2703 struct irq_desc *desc = irq_to_desc(irq);
2704
2705 ack_APIC_irq();
2706 eoi_ioapic_irq(desc);
2707 }
2708 #endif /* CONFIG_INTR_REMAP */
2709
2710 static struct irq_chip ioapic_chip __read_mostly = {
2711 .name = "IO-APIC",
2712 .startup = startup_ioapic_irq,
2713 .mask = mask_IO_APIC_irq,
2714 .unmask = unmask_IO_APIC_irq,
2715 .ack = ack_apic_edge,
2716 .eoi = ack_apic_level,
2717 #ifdef CONFIG_SMP
2718 .set_affinity = set_ioapic_affinity_irq,
2719 #endif
2720 .retrigger = ioapic_retrigger_irq,
2721 };
2722
2723 static struct irq_chip ir_ioapic_chip __read_mostly = {
2724 .name = "IR-IO-APIC",
2725 .startup = startup_ioapic_irq,
2726 .mask = mask_IO_APIC_irq,
2727 .unmask = unmask_IO_APIC_irq,
2728 #ifdef CONFIG_INTR_REMAP
2729 .ack = ir_ack_apic_edge,
2730 .eoi = ir_ack_apic_level,
2731 #ifdef CONFIG_SMP
2732 .set_affinity = set_ir_ioapic_affinity_irq,
2733 #endif
2734 #endif
2735 .retrigger = ioapic_retrigger_irq,
2736 };
2737
2738 static inline void init_IO_APIC_traps(void)
2739 {
2740 int irq;
2741 struct irq_desc *desc;
2742 struct irq_cfg *cfg;
2743
2744 /*
2745 * NOTE! The local APIC isn't very good at handling
2746 * multiple interrupts at the same interrupt level.
2747 * As the interrupt level is determined by taking the
2748 * vector number and shifting that right by 4, we
2749 * want to spread these out a bit so that they don't
2750 * all fall in the same interrupt level.
2751 *
2752 * Also, we've got to be careful not to trash gate
2753 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2754 */
2755 for_each_irq_desc(irq, desc) {
2756 cfg = desc->chip_data;
2757 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2758 /*
2759 * Hmm.. We don't have an entry for this,
2760 * so default to an old-fashioned 8259
2761 * interrupt if we can..
2762 */
2763 if (irq < NR_IRQS_LEGACY)
2764 make_8259A_irq(irq);
2765 else
2766 /* Strange. Oh, well.. */
2767 desc->chip = &no_irq_chip;
2768 }
2769 }
2770 }
2771
2772 /*
2773 * The local APIC irq-chip implementation:
2774 */
2775
2776 static void mask_lapic_irq(unsigned int irq)
2777 {
2778 unsigned long v;
2779
2780 v = apic_read(APIC_LVT0);
2781 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2782 }
2783
2784 static void unmask_lapic_irq(unsigned int irq)
2785 {
2786 unsigned long v;
2787
2788 v = apic_read(APIC_LVT0);
2789 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2790 }
2791
2792 static void ack_lapic_irq(unsigned int irq)
2793 {
2794 ack_APIC_irq();
2795 }
2796
2797 static struct irq_chip lapic_chip __read_mostly = {
2798 .name = "local-APIC",
2799 .mask = mask_lapic_irq,
2800 .unmask = unmask_lapic_irq,
2801 .ack = ack_lapic_irq,
2802 };
2803
2804 static void lapic_register_intr(int irq, struct irq_desc *desc)
2805 {
2806 desc->status &= ~IRQ_LEVEL;
2807 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2808 "edge");
2809 }
2810
2811 static void __init setup_nmi(void)
2812 {
2813 /*
2814 * Dirty trick to enable the NMI watchdog ...
2815 * We put the 8259A master into AEOI mode and
2816 * unmask on all local APICs LVT0 as NMI.
2817 *
2818 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2819 * is from Maciej W. Rozycki - so we do not have to EOI from
2820 * the NMI handler or the timer interrupt.
2821 */
2822 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2823
2824 enable_NMI_through_LVT0();
2825
2826 apic_printk(APIC_VERBOSE, " done.\n");
2827 }
2828
2829 /*
2830 * This looks a bit hackish but it's about the only one way of sending
2831 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2832 * not support the ExtINT mode, unfortunately. We need to send these
2833 * cycles as some i82489DX-based boards have glue logic that keeps the
2834 * 8259A interrupt line asserted until INTA. --macro
2835 */
2836 static inline void __init unlock_ExtINT_logic(void)
2837 {
2838 int apic, pin, i;
2839 struct IO_APIC_route_entry entry0, entry1;
2840 unsigned char save_control, save_freq_select;
2841
2842 pin = find_isa_irq_pin(8, mp_INT);
2843 if (pin == -1) {
2844 WARN_ON_ONCE(1);
2845 return;
2846 }
2847 apic = find_isa_irq_apic(8, mp_INT);
2848 if (apic == -1) {
2849 WARN_ON_ONCE(1);
2850 return;
2851 }
2852
2853 entry0 = ioapic_read_entry(apic, pin);
2854 clear_IO_APIC_pin(apic, pin);
2855
2856 memset(&entry1, 0, sizeof(entry1));
2857
2858 entry1.dest_mode = 0; /* physical delivery */
2859 entry1.mask = 0; /* unmask IRQ now */
2860 entry1.dest = hard_smp_processor_id();
2861 entry1.delivery_mode = dest_ExtINT;
2862 entry1.polarity = entry0.polarity;
2863 entry1.trigger = 0;
2864 entry1.vector = 0;
2865
2866 ioapic_write_entry(apic, pin, entry1);
2867
2868 save_control = CMOS_READ(RTC_CONTROL);
2869 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2870 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2871 RTC_FREQ_SELECT);
2872 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2873
2874 i = 100;
2875 while (i-- > 0) {
2876 mdelay(10);
2877 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2878 i -= 10;
2879 }
2880
2881 CMOS_WRITE(save_control, RTC_CONTROL);
2882 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2883 clear_IO_APIC_pin(apic, pin);
2884
2885 ioapic_write_entry(apic, pin, entry0);
2886 }
2887
2888 static int disable_timer_pin_1 __initdata;
2889 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2890 static int __init disable_timer_pin_setup(char *arg)
2891 {
2892 disable_timer_pin_1 = 1;
2893 return 0;
2894 }
2895 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2896
2897 int timer_through_8259 __initdata;
2898
2899 /*
2900 * This code may look a bit paranoid, but it's supposed to cooperate with
2901 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2902 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2903 * fanatically on his truly buggy board.
2904 *
2905 * FIXME: really need to revamp this for all platforms.
2906 */
2907 static inline void __init check_timer(void)
2908 {
2909 struct irq_desc *desc = irq_to_desc(0);
2910 struct irq_cfg *cfg = desc->chip_data;
2911 int node = cpu_to_node(boot_cpu_id);
2912 int apic1, pin1, apic2, pin2;
2913 unsigned long flags;
2914 int no_pin1 = 0;
2915
2916 local_irq_save(flags);
2917
2918 /*
2919 * get/set the timer IRQ vector:
2920 */
2921 disable_8259A_irq(0);
2922 assign_irq_vector(0, cfg, apic->target_cpus());
2923
2924 /*
2925 * As IRQ0 is to be enabled in the 8259A, the virtual
2926 * wire has to be disabled in the local APIC. Also
2927 * timer interrupts need to be acknowledged manually in
2928 * the 8259A for the i82489DX when using the NMI
2929 * watchdog as that APIC treats NMIs as level-triggered.
2930 * The AEOI mode will finish them in the 8259A
2931 * automatically.
2932 */
2933 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2934 init_8259A(1);
2935 #ifdef CONFIG_X86_32
2936 {
2937 unsigned int ver;
2938
2939 ver = apic_read(APIC_LVR);
2940 ver = GET_APIC_VERSION(ver);
2941 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2942 }
2943 #endif
2944
2945 pin1 = find_isa_irq_pin(0, mp_INT);
2946 apic1 = find_isa_irq_apic(0, mp_INT);
2947 pin2 = ioapic_i8259.pin;
2948 apic2 = ioapic_i8259.apic;
2949
2950 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2951 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2952 cfg->vector, apic1, pin1, apic2, pin2);
2953
2954 /*
2955 * Some BIOS writers are clueless and report the ExtINTA
2956 * I/O APIC input from the cascaded 8259A as the timer
2957 * interrupt input. So just in case, if only one pin
2958 * was found above, try it both directly and through the
2959 * 8259A.
2960 */
2961 if (pin1 == -1) {
2962 if (intr_remapping_enabled)
2963 panic("BIOS bug: timer not connected to IO-APIC");
2964 pin1 = pin2;
2965 apic1 = apic2;
2966 no_pin1 = 1;
2967 } else if (pin2 == -1) {
2968 pin2 = pin1;
2969 apic2 = apic1;
2970 }
2971
2972 if (pin1 != -1) {
2973 /*
2974 * Ok, does IRQ0 through the IOAPIC work?
2975 */
2976 if (no_pin1) {
2977 add_pin_to_irq_node(cfg, node, apic1, pin1);
2978 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2979 } else {
2980 /* for edge trigger, setup_IO_APIC_irq already
2981 * leave it unmasked.
2982 * so only need to unmask if it is level-trigger
2983 * do we really have level trigger timer?
2984 */
2985 int idx;
2986 idx = find_irq_entry(apic1, pin1, mp_INT);
2987 if (idx != -1 && irq_trigger(idx))
2988 unmask_IO_APIC_irq_desc(desc);
2989 }
2990 if (timer_irq_works()) {
2991 if (nmi_watchdog == NMI_IO_APIC) {
2992 setup_nmi();
2993 enable_8259A_irq(0);
2994 }
2995 if (disable_timer_pin_1 > 0)
2996 clear_IO_APIC_pin(0, pin1);
2997 goto out;
2998 }
2999 if (intr_remapping_enabled)
3000 panic("timer doesn't work through Interrupt-remapped IO-APIC");
3001 local_irq_disable();
3002 clear_IO_APIC_pin(apic1, pin1);
3003 if (!no_pin1)
3004 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
3005 "8254 timer not connected to IO-APIC\n");
3006
3007 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
3008 "(IRQ0) through the 8259A ...\n");
3009 apic_printk(APIC_QUIET, KERN_INFO
3010 "..... (found apic %d pin %d) ...\n", apic2, pin2);
3011 /*
3012 * legacy devices should be connected to IO APIC #0
3013 */
3014 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
3015 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
3016 enable_8259A_irq(0);
3017 if (timer_irq_works()) {
3018 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
3019 timer_through_8259 = 1;
3020 if (nmi_watchdog == NMI_IO_APIC) {
3021 disable_8259A_irq(0);
3022 setup_nmi();
3023 enable_8259A_irq(0);
3024 }
3025 goto out;
3026 }
3027 /*
3028 * Cleanup, just in case ...
3029 */
3030 local_irq_disable();
3031 disable_8259A_irq(0);
3032 clear_IO_APIC_pin(apic2, pin2);
3033 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
3034 }
3035
3036 if (nmi_watchdog == NMI_IO_APIC) {
3037 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
3038 "through the IO-APIC - disabling NMI Watchdog!\n");
3039 nmi_watchdog = NMI_NONE;
3040 }
3041 #ifdef CONFIG_X86_32
3042 timer_ack = 0;
3043 #endif
3044
3045 apic_printk(APIC_QUIET, KERN_INFO
3046 "...trying to set up timer as Virtual Wire IRQ...\n");
3047
3048 lapic_register_intr(0, desc);
3049 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3050 enable_8259A_irq(0);
3051
3052 if (timer_irq_works()) {
3053 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3054 goto out;
3055 }
3056 local_irq_disable();
3057 disable_8259A_irq(0);
3058 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3059 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3060
3061 apic_printk(APIC_QUIET, KERN_INFO
3062 "...trying to set up timer as ExtINT IRQ...\n");
3063
3064 init_8259A(0);
3065 make_8259A_irq(0);
3066 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3067
3068 unlock_ExtINT_logic();
3069
3070 if (timer_irq_works()) {
3071 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3072 goto out;
3073 }
3074 local_irq_disable();
3075 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3076 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3077 "report. Then try booting with the 'noapic' option.\n");
3078 out:
3079 local_irq_restore(flags);
3080 }
3081
3082 /*
3083 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3084 * to devices. However there may be an I/O APIC pin available for
3085 * this interrupt regardless. The pin may be left unconnected, but
3086 * typically it will be reused as an ExtINT cascade interrupt for
3087 * the master 8259A. In the MPS case such a pin will normally be
3088 * reported as an ExtINT interrupt in the MP table. With ACPI
3089 * there is no provision for ExtINT interrupts, and in the absence
3090 * of an override it would be treated as an ordinary ISA I/O APIC
3091 * interrupt, that is edge-triggered and unmasked by default. We
3092 * used to do this, but it caused problems on some systems because
3093 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3094 * the same ExtINT cascade interrupt to drive the local APIC of the
3095 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3096 * the I/O APIC in all cases now. No actual device should request
3097 * it anyway. --macro
3098 */
3099 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3100
3101 void __init setup_IO_APIC(void)
3102 {
3103
3104 /*
3105 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3106 */
3107
3108 io_apic_irqs = ~PIC_IRQS;
3109
3110 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3111 /*
3112 * Set up IO-APIC IRQ routing.
3113 */
3114 #ifdef CONFIG_X86_32
3115 if (!acpi_ioapic)
3116 setup_ioapic_ids_from_mpc();
3117 #endif
3118 sync_Arb_IDs();
3119 setup_IO_APIC_irqs();
3120 init_IO_APIC_traps();
3121 check_timer();
3122 }
3123
3124 /*
3125 * Called after all the initialization is done. If we didnt find any
3126 * APIC bugs then we can allow the modify fast path
3127 */
3128
3129 static int __init io_apic_bug_finalize(void)
3130 {
3131 if (sis_apic_bug == -1)
3132 sis_apic_bug = 0;
3133 return 0;
3134 }
3135
3136 late_initcall(io_apic_bug_finalize);
3137
3138 struct sysfs_ioapic_data {
3139 struct sys_device dev;
3140 struct IO_APIC_route_entry entry[0];
3141 };
3142 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3143
3144 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3145 {
3146 struct IO_APIC_route_entry *entry;
3147 struct sysfs_ioapic_data *data;
3148 int i;
3149
3150 data = container_of(dev, struct sysfs_ioapic_data, dev);
3151 entry = data->entry;
3152 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3153 *entry = ioapic_read_entry(dev->id, i);
3154
3155 return 0;
3156 }
3157
3158 static int ioapic_resume(struct sys_device *dev)
3159 {
3160 struct IO_APIC_route_entry *entry;
3161 struct sysfs_ioapic_data *data;
3162 unsigned long flags;
3163 union IO_APIC_reg_00 reg_00;
3164 int i;
3165
3166 data = container_of(dev, struct sysfs_ioapic_data, dev);
3167 entry = data->entry;
3168
3169 spin_lock_irqsave(&ioapic_lock, flags);
3170 reg_00.raw = io_apic_read(dev->id, 0);
3171 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3172 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3173 io_apic_write(dev->id, 0, reg_00.raw);
3174 }
3175 spin_unlock_irqrestore(&ioapic_lock, flags);
3176 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3177 ioapic_write_entry(dev->id, i, entry[i]);
3178
3179 return 0;
3180 }
3181
3182 static struct sysdev_class ioapic_sysdev_class = {
3183 .name = "ioapic",
3184 .suspend = ioapic_suspend,
3185 .resume = ioapic_resume,
3186 };
3187
3188 static int __init ioapic_init_sysfs(void)
3189 {
3190 struct sys_device * dev;
3191 int i, size, error;
3192
3193 error = sysdev_class_register(&ioapic_sysdev_class);
3194 if (error)
3195 return error;
3196
3197 for (i = 0; i < nr_ioapics; i++ ) {
3198 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3199 * sizeof(struct IO_APIC_route_entry);
3200 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3201 if (!mp_ioapic_data[i]) {
3202 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3203 continue;
3204 }
3205 dev = &mp_ioapic_data[i]->dev;
3206 dev->id = i;
3207 dev->cls = &ioapic_sysdev_class;
3208 error = sysdev_register(dev);
3209 if (error) {
3210 kfree(mp_ioapic_data[i]);
3211 mp_ioapic_data[i] = NULL;
3212 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3213 continue;
3214 }
3215 }
3216
3217 return 0;
3218 }
3219
3220 device_initcall(ioapic_init_sysfs);
3221
3222 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3223 /*
3224 * Dynamic irq allocate and deallocation
3225 */
3226 unsigned int create_irq_nr(unsigned int irq_want, int node)
3227 {
3228 /* Allocate an unused irq */
3229 unsigned int irq;
3230 unsigned int new;
3231 unsigned long flags;
3232 struct irq_cfg *cfg_new = NULL;
3233 struct irq_desc *desc_new = NULL;
3234
3235 irq = 0;
3236 if (irq_want < nr_irqs_gsi)
3237 irq_want = nr_irqs_gsi;
3238
3239 spin_lock_irqsave(&vector_lock, flags);
3240 for (new = irq_want; new < nr_irqs; new++) {
3241 desc_new = irq_to_desc_alloc_node(new, node);
3242 if (!desc_new) {
3243 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3244 continue;
3245 }
3246 cfg_new = desc_new->chip_data;
3247
3248 if (cfg_new->vector != 0)
3249 continue;
3250
3251 desc_new = move_irq_desc(desc_new, node);
3252
3253 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3254 irq = new;
3255 break;
3256 }
3257 spin_unlock_irqrestore(&vector_lock, flags);
3258
3259 if (irq > 0) {
3260 dynamic_irq_init(irq);
3261 /* restore it, in case dynamic_irq_init clear it */
3262 if (desc_new)
3263 desc_new->chip_data = cfg_new;
3264 }
3265 return irq;
3266 }
3267
3268 int create_irq(void)
3269 {
3270 int node = cpu_to_node(boot_cpu_id);
3271 unsigned int irq_want;
3272 int irq;
3273
3274 irq_want = nr_irqs_gsi;
3275 irq = create_irq_nr(irq_want, node);
3276
3277 if (irq == 0)
3278 irq = -1;
3279
3280 return irq;
3281 }
3282
3283 void destroy_irq(unsigned int irq)
3284 {
3285 unsigned long flags;
3286 struct irq_cfg *cfg;
3287 struct irq_desc *desc;
3288
3289 /* store it, in case dynamic_irq_cleanup clear it */
3290 desc = irq_to_desc(irq);
3291 cfg = desc->chip_data;
3292 dynamic_irq_cleanup(irq);
3293 /* connect back irq_cfg */
3294 if (desc)
3295 desc->chip_data = cfg;
3296
3297 free_irte(irq);
3298 spin_lock_irqsave(&vector_lock, flags);
3299 __clear_irq_vector(irq, cfg);
3300 spin_unlock_irqrestore(&vector_lock, flags);
3301 }
3302
3303 /*
3304 * MSI message composition
3305 */
3306 #ifdef CONFIG_PCI_MSI
3307 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3308 {
3309 struct irq_cfg *cfg;
3310 int err;
3311 unsigned dest;
3312
3313 if (disable_apic)
3314 return -ENXIO;
3315
3316 cfg = irq_cfg(irq);
3317 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3318 if (err)
3319 return err;
3320
3321 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3322
3323 if (irq_remapped(irq)) {
3324 struct irte irte;
3325 int ir_index;
3326 u16 sub_handle;
3327
3328 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3329 BUG_ON(ir_index == -1);
3330
3331 memset (&irte, 0, sizeof(irte));
3332
3333 irte.present = 1;
3334 irte.dst_mode = apic->irq_dest_mode;
3335 irte.trigger_mode = 0; /* edge */
3336 irte.dlvry_mode = apic->irq_delivery_mode;
3337 irte.vector = cfg->vector;
3338 irte.dest_id = IRTE_DEST(dest);
3339
3340 /* Set source-id of interrupt request */
3341 set_msi_sid(&irte, pdev);
3342
3343 modify_irte(irq, &irte);
3344
3345 msg->address_hi = MSI_ADDR_BASE_HI;
3346 msg->data = sub_handle;
3347 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3348 MSI_ADDR_IR_SHV |
3349 MSI_ADDR_IR_INDEX1(ir_index) |
3350 MSI_ADDR_IR_INDEX2(ir_index);
3351 } else {
3352 if (x2apic_enabled())
3353 msg->address_hi = MSI_ADDR_BASE_HI |
3354 MSI_ADDR_EXT_DEST_ID(dest);
3355 else
3356 msg->address_hi = MSI_ADDR_BASE_HI;
3357
3358 msg->address_lo =
3359 MSI_ADDR_BASE_LO |
3360 ((apic->irq_dest_mode == 0) ?
3361 MSI_ADDR_DEST_MODE_PHYSICAL:
3362 MSI_ADDR_DEST_MODE_LOGICAL) |
3363 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3364 MSI_ADDR_REDIRECTION_CPU:
3365 MSI_ADDR_REDIRECTION_LOWPRI) |
3366 MSI_ADDR_DEST_ID(dest);
3367
3368 msg->data =
3369 MSI_DATA_TRIGGER_EDGE |
3370 MSI_DATA_LEVEL_ASSERT |
3371 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3372 MSI_DATA_DELIVERY_FIXED:
3373 MSI_DATA_DELIVERY_LOWPRI) |
3374 MSI_DATA_VECTOR(cfg->vector);
3375 }
3376 return err;
3377 }
3378
3379 #ifdef CONFIG_SMP
3380 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3381 {
3382 struct irq_desc *desc = irq_to_desc(irq);
3383 struct irq_cfg *cfg;
3384 struct msi_msg msg;
3385 unsigned int dest;
3386
3387 dest = set_desc_affinity(desc, mask);
3388 if (dest == BAD_APICID)
3389 return -1;
3390
3391 cfg = desc->chip_data;
3392
3393 read_msi_msg_desc(desc, &msg);
3394
3395 msg.data &= ~MSI_DATA_VECTOR_MASK;
3396 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3397 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3398 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3399
3400 write_msi_msg_desc(desc, &msg);
3401
3402 return 0;
3403 }
3404 #ifdef CONFIG_INTR_REMAP
3405 /*
3406 * Migrate the MSI irq to another cpumask. This migration is
3407 * done in the process context using interrupt-remapping hardware.
3408 */
3409 static int
3410 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3411 {
3412 struct irq_desc *desc = irq_to_desc(irq);
3413 struct irq_cfg *cfg = desc->chip_data;
3414 unsigned int dest;
3415 struct irte irte;
3416
3417 if (get_irte(irq, &irte))
3418 return -1;
3419
3420 dest = set_desc_affinity(desc, mask);
3421 if (dest == BAD_APICID)
3422 return -1;
3423
3424 irte.vector = cfg->vector;
3425 irte.dest_id = IRTE_DEST(dest);
3426
3427 /*
3428 * atomically update the IRTE with the new destination and vector.
3429 */
3430 modify_irte(irq, &irte);
3431
3432 /*
3433 * After this point, all the interrupts will start arriving
3434 * at the new destination. So, time to cleanup the previous
3435 * vector allocation.
3436 */
3437 if (cfg->move_in_progress)
3438 send_cleanup_vector(cfg);
3439
3440 return 0;
3441 }
3442
3443 #endif
3444 #endif /* CONFIG_SMP */
3445
3446 /*
3447 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3448 * which implement the MSI or MSI-X Capability Structure.
3449 */
3450 static struct irq_chip msi_chip = {
3451 .name = "PCI-MSI",
3452 .unmask = unmask_msi_irq,
3453 .mask = mask_msi_irq,
3454 .ack = ack_apic_edge,
3455 #ifdef CONFIG_SMP
3456 .set_affinity = set_msi_irq_affinity,
3457 #endif
3458 .retrigger = ioapic_retrigger_irq,
3459 };
3460
3461 static struct irq_chip msi_ir_chip = {
3462 .name = "IR-PCI-MSI",
3463 .unmask = unmask_msi_irq,
3464 .mask = mask_msi_irq,
3465 #ifdef CONFIG_INTR_REMAP
3466 .ack = ir_ack_apic_edge,
3467 #ifdef CONFIG_SMP
3468 .set_affinity = ir_set_msi_irq_affinity,
3469 #endif
3470 #endif
3471 .retrigger = ioapic_retrigger_irq,
3472 };
3473
3474 /*
3475 * Map the PCI dev to the corresponding remapping hardware unit
3476 * and allocate 'nvec' consecutive interrupt-remapping table entries
3477 * in it.
3478 */
3479 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3480 {
3481 struct intel_iommu *iommu;
3482 int index;
3483
3484 iommu = map_dev_to_ir(dev);
3485 if (!iommu) {
3486 printk(KERN_ERR
3487 "Unable to map PCI %s to iommu\n", pci_name(dev));
3488 return -ENOENT;
3489 }
3490
3491 index = alloc_irte(iommu, irq, nvec);
3492 if (index < 0) {
3493 printk(KERN_ERR
3494 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3495 pci_name(dev));
3496 return -ENOSPC;
3497 }
3498 return index;
3499 }
3500
3501 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3502 {
3503 int ret;
3504 struct msi_msg msg;
3505
3506 ret = msi_compose_msg(dev, irq, &msg);
3507 if (ret < 0)
3508 return ret;
3509
3510 set_irq_msi(irq, msidesc);
3511 write_msi_msg(irq, &msg);
3512
3513 if (irq_remapped(irq)) {
3514 struct irq_desc *desc = irq_to_desc(irq);
3515 /*
3516 * irq migration in process context
3517 */
3518 desc->status |= IRQ_MOVE_PCNTXT;
3519 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3520 } else
3521 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3522
3523 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3524
3525 return 0;
3526 }
3527
3528 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3529 {
3530 unsigned int irq;
3531 int ret, sub_handle;
3532 struct msi_desc *msidesc;
3533 unsigned int irq_want;
3534 struct intel_iommu *iommu = NULL;
3535 int index = 0;
3536 int node;
3537
3538 /* x86 doesn't support multiple MSI yet */
3539 if (type == PCI_CAP_ID_MSI && nvec > 1)
3540 return 1;
3541
3542 node = dev_to_node(&dev->dev);
3543 irq_want = nr_irqs_gsi;
3544 sub_handle = 0;
3545 list_for_each_entry(msidesc, &dev->msi_list, list) {
3546 irq = create_irq_nr(irq_want, node);
3547 if (irq == 0)
3548 return -1;
3549 irq_want = irq + 1;
3550 if (!intr_remapping_enabled)
3551 goto no_ir;
3552
3553 if (!sub_handle) {
3554 /*
3555 * allocate the consecutive block of IRTE's
3556 * for 'nvec'
3557 */
3558 index = msi_alloc_irte(dev, irq, nvec);
3559 if (index < 0) {
3560 ret = index;
3561 goto error;
3562 }
3563 } else {
3564 iommu = map_dev_to_ir(dev);
3565 if (!iommu) {
3566 ret = -ENOENT;
3567 goto error;
3568 }
3569 /*
3570 * setup the mapping between the irq and the IRTE
3571 * base index, the sub_handle pointing to the
3572 * appropriate interrupt remap table entry.
3573 */
3574 set_irte_irq(irq, iommu, index, sub_handle);
3575 }
3576 no_ir:
3577 ret = setup_msi_irq(dev, msidesc, irq);
3578 if (ret < 0)
3579 goto error;
3580 sub_handle++;
3581 }
3582 return 0;
3583
3584 error:
3585 destroy_irq(irq);
3586 return ret;
3587 }
3588
3589 void arch_teardown_msi_irq(unsigned int irq)
3590 {
3591 destroy_irq(irq);
3592 }
3593
3594 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3595 #ifdef CONFIG_SMP
3596 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3597 {
3598 struct irq_desc *desc = irq_to_desc(irq);
3599 struct irq_cfg *cfg;
3600 struct msi_msg msg;
3601 unsigned int dest;
3602
3603 dest = set_desc_affinity(desc, mask);
3604 if (dest == BAD_APICID)
3605 return -1;
3606
3607 cfg = desc->chip_data;
3608
3609 dmar_msi_read(irq, &msg);
3610
3611 msg.data &= ~MSI_DATA_VECTOR_MASK;
3612 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3613 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3614 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3615
3616 dmar_msi_write(irq, &msg);
3617
3618 return 0;
3619 }
3620
3621 #endif /* CONFIG_SMP */
3622
3623 static struct irq_chip dmar_msi_type = {
3624 .name = "DMAR_MSI",
3625 .unmask = dmar_msi_unmask,
3626 .mask = dmar_msi_mask,
3627 .ack = ack_apic_edge,
3628 #ifdef CONFIG_SMP
3629 .set_affinity = dmar_msi_set_affinity,
3630 #endif
3631 .retrigger = ioapic_retrigger_irq,
3632 };
3633
3634 int arch_setup_dmar_msi(unsigned int irq)
3635 {
3636 int ret;
3637 struct msi_msg msg;
3638
3639 ret = msi_compose_msg(NULL, irq, &msg);
3640 if (ret < 0)
3641 return ret;
3642 dmar_msi_write(irq, &msg);
3643 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3644 "edge");
3645 return 0;
3646 }
3647 #endif
3648
3649 #ifdef CONFIG_HPET_TIMER
3650
3651 #ifdef CONFIG_SMP
3652 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3653 {
3654 struct irq_desc *desc = irq_to_desc(irq);
3655 struct irq_cfg *cfg;
3656 struct msi_msg msg;
3657 unsigned int dest;
3658
3659 dest = set_desc_affinity(desc, mask);
3660 if (dest == BAD_APICID)
3661 return -1;
3662
3663 cfg = desc->chip_data;
3664
3665 hpet_msi_read(irq, &msg);
3666
3667 msg.data &= ~MSI_DATA_VECTOR_MASK;
3668 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3669 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3670 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3671
3672 hpet_msi_write(irq, &msg);
3673
3674 return 0;
3675 }
3676
3677 #endif /* CONFIG_SMP */
3678
3679 static struct irq_chip hpet_msi_type = {
3680 .name = "HPET_MSI",
3681 .unmask = hpet_msi_unmask,
3682 .mask = hpet_msi_mask,
3683 .ack = ack_apic_edge,
3684 #ifdef CONFIG_SMP
3685 .set_affinity = hpet_msi_set_affinity,
3686 #endif
3687 .retrigger = ioapic_retrigger_irq,
3688 };
3689
3690 int arch_setup_hpet_msi(unsigned int irq)
3691 {
3692 int ret;
3693 struct msi_msg msg;
3694 struct irq_desc *desc = irq_to_desc(irq);
3695
3696 ret = msi_compose_msg(NULL, irq, &msg);
3697 if (ret < 0)
3698 return ret;
3699
3700 hpet_msi_write(irq, &msg);
3701 desc->status |= IRQ_MOVE_PCNTXT;
3702 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3703 "edge");
3704
3705 return 0;
3706 }
3707 #endif
3708
3709 #endif /* CONFIG_PCI_MSI */
3710 /*
3711 * Hypertransport interrupt support
3712 */
3713 #ifdef CONFIG_HT_IRQ
3714
3715 #ifdef CONFIG_SMP
3716
3717 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3718 {
3719 struct ht_irq_msg msg;
3720 fetch_ht_irq_msg(irq, &msg);
3721
3722 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3723 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3724
3725 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3726 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3727
3728 write_ht_irq_msg(irq, &msg);
3729 }
3730
3731 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3732 {
3733 struct irq_desc *desc = irq_to_desc(irq);
3734 struct irq_cfg *cfg;
3735 unsigned int dest;
3736
3737 dest = set_desc_affinity(desc, mask);
3738 if (dest == BAD_APICID)
3739 return -1;
3740
3741 cfg = desc->chip_data;
3742
3743 target_ht_irq(irq, dest, cfg->vector);
3744
3745 return 0;
3746 }
3747
3748 #endif
3749
3750 static struct irq_chip ht_irq_chip = {
3751 .name = "PCI-HT",
3752 .mask = mask_ht_irq,
3753 .unmask = unmask_ht_irq,
3754 .ack = ack_apic_edge,
3755 #ifdef CONFIG_SMP
3756 .set_affinity = set_ht_irq_affinity,
3757 #endif
3758 .retrigger = ioapic_retrigger_irq,
3759 };
3760
3761 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3762 {
3763 struct irq_cfg *cfg;
3764 int err;
3765
3766 if (disable_apic)
3767 return -ENXIO;
3768
3769 cfg = irq_cfg(irq);
3770 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3771 if (!err) {
3772 struct ht_irq_msg msg;
3773 unsigned dest;
3774
3775 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3776 apic->target_cpus());
3777
3778 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3779
3780 msg.address_lo =
3781 HT_IRQ_LOW_BASE |
3782 HT_IRQ_LOW_DEST_ID(dest) |
3783 HT_IRQ_LOW_VECTOR(cfg->vector) |
3784 ((apic->irq_dest_mode == 0) ?
3785 HT_IRQ_LOW_DM_PHYSICAL :
3786 HT_IRQ_LOW_DM_LOGICAL) |
3787 HT_IRQ_LOW_RQEOI_EDGE |
3788 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3789 HT_IRQ_LOW_MT_FIXED :
3790 HT_IRQ_LOW_MT_ARBITRATED) |
3791 HT_IRQ_LOW_IRQ_MASKED;
3792
3793 write_ht_irq_msg(irq, &msg);
3794
3795 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3796 handle_edge_irq, "edge");
3797
3798 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3799 }
3800 return err;
3801 }
3802 #endif /* CONFIG_HT_IRQ */
3803
3804 #ifdef CONFIG_X86_UV
3805 /*
3806 * Re-target the irq to the specified CPU and enable the specified MMR located
3807 * on the specified blade to allow the sending of MSIs to the specified CPU.
3808 */
3809 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3810 unsigned long mmr_offset)
3811 {
3812 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3813 struct irq_cfg *cfg;
3814 int mmr_pnode;
3815 unsigned long mmr_value;
3816 struct uv_IO_APIC_route_entry *entry;
3817 unsigned long flags;
3818 int err;
3819
3820 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3821
3822 cfg = irq_cfg(irq);
3823
3824 err = assign_irq_vector(irq, cfg, eligible_cpu);
3825 if (err != 0)
3826 return err;
3827
3828 spin_lock_irqsave(&vector_lock, flags);
3829 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3830 irq_name);
3831 spin_unlock_irqrestore(&vector_lock, flags);
3832
3833 mmr_value = 0;
3834 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3835 entry->vector = cfg->vector;
3836 entry->delivery_mode = apic->irq_delivery_mode;
3837 entry->dest_mode = apic->irq_dest_mode;
3838 entry->polarity = 0;
3839 entry->trigger = 0;
3840 entry->mask = 0;
3841 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3842
3843 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3844 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3845
3846 if (cfg->move_in_progress)
3847 send_cleanup_vector(cfg);
3848
3849 return irq;
3850 }
3851
3852 /*
3853 * Disable the specified MMR located on the specified blade so that MSIs are
3854 * longer allowed to be sent.
3855 */
3856 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3857 {
3858 unsigned long mmr_value;
3859 struct uv_IO_APIC_route_entry *entry;
3860 int mmr_pnode;
3861
3862 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3863
3864 mmr_value = 0;
3865 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3866 entry->mask = 1;
3867
3868 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3869 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3870 }
3871 #endif /* CONFIG_X86_64 */
3872
3873 int __init io_apic_get_redir_entries (int ioapic)
3874 {
3875 union IO_APIC_reg_01 reg_01;
3876 unsigned long flags;
3877
3878 spin_lock_irqsave(&ioapic_lock, flags);
3879 reg_01.raw = io_apic_read(ioapic, 1);
3880 spin_unlock_irqrestore(&ioapic_lock, flags);
3881
3882 return reg_01.bits.entries;
3883 }
3884
3885 void __init probe_nr_irqs_gsi(void)
3886 {
3887 int nr = 0;
3888
3889 nr = acpi_probe_gsi();
3890 if (nr > nr_irqs_gsi) {
3891 nr_irqs_gsi = nr;
3892 } else {
3893 /* for acpi=off or acpi is not compiled in */
3894 int idx;
3895
3896 nr = 0;
3897 for (idx = 0; idx < nr_ioapics; idx++)
3898 nr += io_apic_get_redir_entries(idx) + 1;
3899
3900 if (nr > nr_irqs_gsi)
3901 nr_irqs_gsi = nr;
3902 }
3903
3904 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3905 }
3906
3907 #ifdef CONFIG_SPARSE_IRQ
3908 int __init arch_probe_nr_irqs(void)
3909 {
3910 int nr;
3911
3912 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3913 nr_irqs = NR_VECTORS * nr_cpu_ids;
3914
3915 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3916 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3917 /*
3918 * for MSI and HT dyn irq
3919 */
3920 nr += nr_irqs_gsi * 16;
3921 #endif
3922 if (nr < nr_irqs)
3923 nr_irqs = nr;
3924
3925 return 0;
3926 }
3927 #endif
3928
3929 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3930 struct io_apic_irq_attr *irq_attr)
3931 {
3932 struct irq_desc *desc;
3933 struct irq_cfg *cfg;
3934 int node;
3935 int ioapic, pin;
3936 int trigger, polarity;
3937
3938 ioapic = irq_attr->ioapic;
3939 if (!IO_APIC_IRQ(irq)) {
3940 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3941 ioapic);
3942 return -EINVAL;
3943 }
3944
3945 if (dev)
3946 node = dev_to_node(dev);
3947 else
3948 node = cpu_to_node(boot_cpu_id);
3949
3950 desc = irq_to_desc_alloc_node(irq, node);
3951 if (!desc) {
3952 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3953 return 0;
3954 }
3955
3956 pin = irq_attr->ioapic_pin;
3957 trigger = irq_attr->trigger;
3958 polarity = irq_attr->polarity;
3959
3960 /*
3961 * IRQs < 16 are already in the irq_2_pin[] map
3962 */
3963 if (irq >= NR_IRQS_LEGACY) {
3964 cfg = desc->chip_data;
3965 add_pin_to_irq_node(cfg, node, ioapic, pin);
3966 }
3967
3968 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3969
3970 return 0;
3971 }
3972
3973 int io_apic_set_pci_routing(struct device *dev, int irq,
3974 struct io_apic_irq_attr *irq_attr)
3975 {
3976 int ioapic, pin;
3977 /*
3978 * Avoid pin reprogramming. PRTs typically include entries
3979 * with redundant pin->gsi mappings (but unique PCI devices);
3980 * we only program the IOAPIC on the first.
3981 */
3982 ioapic = irq_attr->ioapic;
3983 pin = irq_attr->ioapic_pin;
3984 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3985 pr_debug("Pin %d-%d already programmed\n",
3986 mp_ioapics[ioapic].apicid, pin);
3987 return 0;
3988 }
3989 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3990
3991 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3992 }
3993
3994 /* --------------------------------------------------------------------------
3995 ACPI-based IOAPIC Configuration
3996 -------------------------------------------------------------------------- */
3997
3998 #ifdef CONFIG_ACPI
3999
4000 #ifdef CONFIG_X86_32
4001 int __init io_apic_get_unique_id(int ioapic, int apic_id)
4002 {
4003 union IO_APIC_reg_00 reg_00;
4004 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
4005 physid_mask_t tmp;
4006 unsigned long flags;
4007 int i = 0;
4008
4009 /*
4010 * The P4 platform supports up to 256 APIC IDs on two separate APIC
4011 * buses (one for LAPICs, one for IOAPICs), where predecessors only
4012 * supports up to 16 on one shared APIC bus.
4013 *
4014 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
4015 * advantage of new APIC bus architecture.
4016 */
4017
4018 if (physids_empty(apic_id_map))
4019 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
4020
4021 spin_lock_irqsave(&ioapic_lock, flags);
4022 reg_00.raw = io_apic_read(ioapic, 0);
4023 spin_unlock_irqrestore(&ioapic_lock, flags);
4024
4025 if (apic_id >= get_physical_broadcast()) {
4026 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
4027 "%d\n", ioapic, apic_id, reg_00.bits.ID);
4028 apic_id = reg_00.bits.ID;
4029 }
4030
4031 /*
4032 * Every APIC in a system must have a unique ID or we get lots of nice
4033 * 'stuck on smp_invalidate_needed IPI wait' messages.
4034 */
4035 if (apic->check_apicid_used(apic_id_map, apic_id)) {
4036
4037 for (i = 0; i < get_physical_broadcast(); i++) {
4038 if (!apic->check_apicid_used(apic_id_map, i))
4039 break;
4040 }
4041
4042 if (i == get_physical_broadcast())
4043 panic("Max apic_id exceeded!\n");
4044
4045 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
4046 "trying %d\n", ioapic, apic_id, i);
4047
4048 apic_id = i;
4049 }
4050
4051 tmp = apic->apicid_to_cpu_present(apic_id);
4052 physids_or(apic_id_map, apic_id_map, tmp);
4053
4054 if (reg_00.bits.ID != apic_id) {
4055 reg_00.bits.ID = apic_id;
4056
4057 spin_lock_irqsave(&ioapic_lock, flags);
4058 io_apic_write(ioapic, 0, reg_00.raw);
4059 reg_00.raw = io_apic_read(ioapic, 0);
4060 spin_unlock_irqrestore(&ioapic_lock, flags);
4061
4062 /* Sanity check */
4063 if (reg_00.bits.ID != apic_id) {
4064 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
4065 return -1;
4066 }
4067 }
4068
4069 apic_printk(APIC_VERBOSE, KERN_INFO
4070 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
4071
4072 return apic_id;
4073 }
4074 #endif
4075
4076 int __init io_apic_get_version(int ioapic)
4077 {
4078 union IO_APIC_reg_01 reg_01;
4079 unsigned long flags;
4080
4081 spin_lock_irqsave(&ioapic_lock, flags);
4082 reg_01.raw = io_apic_read(ioapic, 1);
4083 spin_unlock_irqrestore(&ioapic_lock, flags);
4084
4085 return reg_01.bits.version;
4086 }
4087
4088 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4089 {
4090 int i;
4091
4092 if (skip_ioapic_setup)
4093 return -1;
4094
4095 for (i = 0; i < mp_irq_entries; i++)
4096 if (mp_irqs[i].irqtype == mp_INT &&
4097 mp_irqs[i].srcbusirq == bus_irq)
4098 break;
4099 if (i >= mp_irq_entries)
4100 return -1;
4101
4102 *trigger = irq_trigger(i);
4103 *polarity = irq_polarity(i);
4104 return 0;
4105 }
4106
4107 #endif /* CONFIG_ACPI */
4108
4109 /*
4110 * This function currently is only a helper for the i386 smp boot process where
4111 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4112 * so mask in all cases should simply be apic->target_cpus()
4113 */
4114 #ifdef CONFIG_SMP
4115 void __init setup_ioapic_dest(void)
4116 {
4117 int pin, ioapic = 0, irq, irq_entry;
4118 struct irq_desc *desc;
4119 const struct cpumask *mask;
4120
4121 if (skip_ioapic_setup == 1)
4122 return;
4123
4124 #ifdef CONFIG_ACPI
4125 if (!acpi_disabled && acpi_ioapic) {
4126 ioapic = mp_find_ioapic(0);
4127 if (ioapic < 0)
4128 ioapic = 0;
4129 }
4130 #endif
4131
4132 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4133 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4134 if (irq_entry == -1)
4135 continue;
4136 irq = pin_2_irq(irq_entry, ioapic, pin);
4137
4138 desc = irq_to_desc(irq);
4139
4140 /*
4141 * Honour affinities which have been set in early boot
4142 */
4143 if (desc->status &
4144 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4145 mask = desc->affinity;
4146 else
4147 mask = apic->target_cpus();
4148
4149 if (intr_remapping_enabled)
4150 set_ir_ioapic_affinity_irq_desc(desc, mask);
4151 else
4152 set_ioapic_affinity_irq_desc(desc, mask);
4153 }
4154
4155 }
4156 #endif
4157
4158 #define IOAPIC_RESOURCE_NAME_SIZE 11
4159
4160 static struct resource *ioapic_resources;
4161
4162 static struct resource * __init ioapic_setup_resources(void)
4163 {
4164 unsigned long n;
4165 struct resource *res;
4166 char *mem;
4167 int i;
4168
4169 if (nr_ioapics <= 0)
4170 return NULL;
4171
4172 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4173 n *= nr_ioapics;
4174
4175 mem = alloc_bootmem(n);
4176 res = (void *)mem;
4177
4178 if (mem != NULL) {
4179 mem += sizeof(struct resource) * nr_ioapics;
4180
4181 for (i = 0; i < nr_ioapics; i++) {
4182 res[i].name = mem;
4183 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4184 sprintf(mem, "IOAPIC %u", i);
4185 mem += IOAPIC_RESOURCE_NAME_SIZE;
4186 }
4187 }
4188
4189 ioapic_resources = res;
4190
4191 return res;
4192 }
4193
4194 void __init ioapic_init_mappings(void)
4195 {
4196 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4197 struct resource *ioapic_res;
4198 int i;
4199
4200 ioapic_res = ioapic_setup_resources();
4201 for (i = 0; i < nr_ioapics; i++) {
4202 if (smp_found_config) {
4203 ioapic_phys = mp_ioapics[i].apicaddr;
4204 #ifdef CONFIG_X86_32
4205 if (!ioapic_phys) {
4206 printk(KERN_ERR
4207 "WARNING: bogus zero IO-APIC "
4208 "address found in MPTABLE, "
4209 "disabling IO/APIC support!\n");
4210 smp_found_config = 0;
4211 skip_ioapic_setup = 1;
4212 goto fake_ioapic_page;
4213 }
4214 #endif
4215 } else {
4216 #ifdef CONFIG_X86_32
4217 fake_ioapic_page:
4218 #endif
4219 ioapic_phys = (unsigned long)
4220 alloc_bootmem_pages(PAGE_SIZE);
4221 ioapic_phys = __pa(ioapic_phys);
4222 }
4223 set_fixmap_nocache(idx, ioapic_phys);
4224 apic_printk(APIC_VERBOSE,
4225 "mapped IOAPIC to %08lx (%08lx)\n",
4226 __fix_to_virt(idx), ioapic_phys);
4227 idx++;
4228
4229 if (ioapic_res != NULL) {
4230 ioapic_res->start = ioapic_phys;
4231 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4232 ioapic_res++;
4233 }
4234 }
4235 }
4236
4237 void __init ioapic_insert_resources(void)
4238 {
4239 int i;
4240 struct resource *r = ioapic_resources;
4241
4242 if (!r) {
4243 if (nr_ioapics > 0)
4244 printk(KERN_ERR
4245 "IO APIC resources couldn't be allocated.\n");
4246 return;
4247 }
4248
4249 for (i = 0; i < nr_ioapics; i++) {
4250 insert_resource(&iomem_resource, r);
4251 r++;
4252 }
4253 }
4254
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