1 #ifndef __SVM_H
2 #define __SVM_H
3
4 enum {
5 INTERCEPT_INTR,
6 INTERCEPT_NMI,
7 INTERCEPT_SMI,
8 INTERCEPT_INIT,
9 INTERCEPT_VINTR,
10 INTERCEPT_SELECTIVE_CR0,
11 INTERCEPT_STORE_IDTR,
12 INTERCEPT_STORE_GDTR,
13 INTERCEPT_STORE_LDTR,
14 INTERCEPT_STORE_TR,
15 INTERCEPT_LOAD_IDTR,
16 INTERCEPT_LOAD_GDTR,
17 INTERCEPT_LOAD_LDTR,
18 INTERCEPT_LOAD_TR,
19 INTERCEPT_RDTSC,
20 INTERCEPT_RDPMC,
21 INTERCEPT_PUSHF,
22 INTERCEPT_POPF,
23 INTERCEPT_CPUID,
24 INTERCEPT_RSM,
25 INTERCEPT_IRET,
26 INTERCEPT_INTn,
27 INTERCEPT_INVD,
28 INTERCEPT_PAUSE,
29 INTERCEPT_HLT,
30 INTERCEPT_INVLPG,
31 INTERCEPT_INVLPGA,
32 INTERCEPT_IOIO_PROT,
33 INTERCEPT_MSR_PROT,
34 INTERCEPT_TASK_SWITCH,
35 INTERCEPT_FERR_FREEZE,
36 INTERCEPT_SHUTDOWN,
37 INTERCEPT_VMRUN,
38 INTERCEPT_VMMCALL,
39 INTERCEPT_VMLOAD,
40 INTERCEPT_VMSAVE,
41 INTERCEPT_STGI,
42 INTERCEPT_CLGI,
43 INTERCEPT_SKINIT,
44 INTERCEPT_RDTSCP,
45 INTERCEPT_ICEBP,
46 INTERCEPT_WBINVD,
47 INTERCEPT_MONITOR,
48 INTERCEPT_MWAIT,
49 INTERCEPT_MWAIT_COND,
50 };
51
52
53 struct __attribute__ ((__packed__)) vmcb_control_area {
54 u16 intercept_cr_read;
55 u16 intercept_cr_write;
56 u16 intercept_dr_read;
57 u16 intercept_dr_write;
58 u32 intercept_exceptions;
59 u64 intercept;
60 u8 reserved_1[44];
61 u64 iopm_base_pa;
62 u64 msrpm_base_pa;
63 u64 tsc_offset;
64 u32 asid;
65 u8 tlb_ctl;
66 u8 reserved_2[3];
67 u32 int_ctl;
68 u32 int_vector;
69 u32 int_state;
70 u8 reserved_3[4];
71 u32 exit_code;
72 u32 exit_code_hi;
73 u64 exit_info_1;
74 u64 exit_info_2;
75 u32 exit_int_info;
76 u32 exit_int_info_err;
77 u64 nested_ctl;
78 u8 reserved_4[16];
79 u32 event_inj;
80 u32 event_inj_err;
81 u64 nested_cr3;
82 u64 lbr_ctl;
83 u8 reserved_5[832];
84 };
85
86
87 #define TLB_CONTROL_DO_NOTHING 0
88 #define TLB_CONTROL_FLUSH_ALL_ASID 1
89
90 #define V_TPR_MASK 0x0f
91
92 #define V_IRQ_SHIFT 8
93 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
94
95 #define V_INTR_PRIO_SHIFT 16
96 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
97
98 #define V_IGN_TPR_SHIFT 20
99 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
100
101 #define V_INTR_MASKING_SHIFT 24
102 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
103
104 #define SVM_INTERRUPT_SHADOW_MASK 1
105
106 #define SVM_IOIO_STR_SHIFT 2
107 #define SVM_IOIO_REP_SHIFT 3
108 #define SVM_IOIO_SIZE_SHIFT 4
109 #define SVM_IOIO_ASIZE_SHIFT 7
110
111 #define SVM_IOIO_TYPE_MASK 1
112 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
113 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
114 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
115 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
116
117 struct __attribute__ ((__packed__)) vmcb_seg {
118 u16 selector;
119 u16 attrib;
120 u32 limit;
121 u64 base;
122 };
123
124 struct __attribute__ ((__packed__)) vmcb_save_area {
125 struct vmcb_seg es;
126 struct vmcb_seg cs;
127 struct vmcb_seg ss;
128 struct vmcb_seg ds;
129 struct vmcb_seg fs;
130 struct vmcb_seg gs;
131 struct vmcb_seg gdtr;
132 struct vmcb_seg ldtr;
133 struct vmcb_seg idtr;
134 struct vmcb_seg tr;
135 u8 reserved_1[43];
136 u8 cpl;
137 u8 reserved_2[4];
138 u64 efer;
139 u8 reserved_3[112];
140 u64 cr4;
141 u64 cr3;
142 u64 cr0;
143 u64 dr7;
144 u64 dr6;
145 u64 rflags;
146 u64 rip;
147 u8 reserved_4[88];
148 u64 rsp;
149 u8 reserved_5[24];
150 u64 rax;
151 u64 star;
152 u64 lstar;
153 u64 cstar;
154 u64 sfmask;
155 u64 kernel_gs_base;
156 u64 sysenter_cs;
157 u64 sysenter_esp;
158 u64 sysenter_eip;
159 u64 cr2;
160 u8 reserved_6[32];
161 u64 g_pat;
162 u64 dbgctl;
163 u64 br_from;
164 u64 br_to;
165 u64 last_excp_from;
166 u64 last_excp_to;
167 };
168
169 struct __attribute__ ((__packed__)) vmcb {
170 struct vmcb_control_area control;
171 struct vmcb_save_area save;
172 };
173
174 #define SVM_CPUID_FEATURE_SHIFT 2
175 #define SVM_CPUID_FUNC 0x8000000a
176
177 #define SVM_VM_CR_SVM_DISABLE 4
178
179 #define SVM_SELECTOR_S_SHIFT 4
180 #define SVM_SELECTOR_DPL_SHIFT 5
181 #define SVM_SELECTOR_P_SHIFT 7
182 #define SVM_SELECTOR_AVL_SHIFT 8
183 #define SVM_SELECTOR_L_SHIFT 9
184 #define SVM_SELECTOR_DB_SHIFT 10
185 #define SVM_SELECTOR_G_SHIFT 11
186
187 #define SVM_SELECTOR_TYPE_MASK (0xf)
188 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
189 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
190 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
191 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
192 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
193 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
194 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
195
196 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
197 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
198 #define SVM_SELECTOR_CODE_MASK (1 << 3)
199
200 #define INTERCEPT_CR0_MASK 1
201 #define INTERCEPT_CR3_MASK (1 << 3)
202 #define INTERCEPT_CR4_MASK (1 << 4)
203 #define INTERCEPT_CR8_MASK (1 << 8)
204
205 #define INTERCEPT_DR0_MASK 1
206 #define INTERCEPT_DR1_MASK (1 << 1)
207 #define INTERCEPT_DR2_MASK (1 << 2)
208 #define INTERCEPT_DR3_MASK (1 << 3)
209 #define INTERCEPT_DR4_MASK (1 << 4)
210 #define INTERCEPT_DR5_MASK (1 << 5)
211 #define INTERCEPT_DR6_MASK (1 << 6)
212 #define INTERCEPT_DR7_MASK (1 << 7)
213
214 #define SVM_EVTINJ_VEC_MASK 0xff
215
216 #define SVM_EVTINJ_TYPE_SHIFT 8
217 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
218
219 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
220 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
221 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
222 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
223
224 #define SVM_EVTINJ_VALID (1 << 31)
225 #define SVM_EVTINJ_VALID_ERR (1 << 11)
226
227 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
228 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
229
230 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
231 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
232 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
233 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
234
235 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
236 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
237
238 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
239 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
240
241 #define SVM_EXIT_READ_CR0 0x000
242 #define SVM_EXIT_READ_CR3 0x003
243 #define SVM_EXIT_READ_CR4 0x004
244 #define SVM_EXIT_READ_CR8 0x008
245 #define SVM_EXIT_WRITE_CR0 0x010
246 #define SVM_EXIT_WRITE_CR3 0x013
247 #define SVM_EXIT_WRITE_CR4 0x014
248 #define SVM_EXIT_WRITE_CR8 0x018
249 #define SVM_EXIT_READ_DR0 0x020
250 #define SVM_EXIT_READ_DR1 0x021
251 #define SVM_EXIT_READ_DR2 0x022
252 #define SVM_EXIT_READ_DR3 0x023
253 #define SVM_EXIT_READ_DR4 0x024
254 #define SVM_EXIT_READ_DR5 0x025
255 #define SVM_EXIT_READ_DR6 0x026
256 #define SVM_EXIT_READ_DR7 0x027
257 #define SVM_EXIT_WRITE_DR0 0x030
258 #define SVM_EXIT_WRITE_DR1 0x031
259 #define SVM_EXIT_WRITE_DR2 0x032
260 #define SVM_EXIT_WRITE_DR3 0x033
261 #define SVM_EXIT_WRITE_DR4 0x034
262 #define SVM_EXIT_WRITE_DR5 0x035
263 #define SVM_EXIT_WRITE_DR6 0x036
264 #define SVM_EXIT_WRITE_DR7 0x037
265 #define SVM_EXIT_EXCP_BASE 0x040
266 #define SVM_EXIT_INTR 0x060
267 #define SVM_EXIT_NMI 0x061
268 #define SVM_EXIT_SMI 0x062
269 #define SVM_EXIT_INIT 0x063
270 #define SVM_EXIT_VINTR 0x064
271 #define SVM_EXIT_CR0_SEL_WRITE 0x065
272 #define SVM_EXIT_IDTR_READ 0x066
273 #define SVM_EXIT_GDTR_READ 0x067
274 #define SVM_EXIT_LDTR_READ 0x068
275 #define SVM_EXIT_TR_READ 0x069
276 #define SVM_EXIT_IDTR_WRITE 0x06a
277 #define SVM_EXIT_GDTR_WRITE 0x06b
278 #define SVM_EXIT_LDTR_WRITE 0x06c
279 #define SVM_EXIT_TR_WRITE 0x06d
280 #define SVM_EXIT_RDTSC 0x06e
281 #define SVM_EXIT_RDPMC 0x06f
282 #define SVM_EXIT_PUSHF 0x070
283 #define SVM_EXIT_POPF 0x071
284 #define SVM_EXIT_CPUID 0x072
285 #define SVM_EXIT_RSM 0x073
286 #define SVM_EXIT_IRET 0x074
287 #define SVM_EXIT_SWINT 0x075
288 #define SVM_EXIT_INVD 0x076
289 #define SVM_EXIT_PAUSE 0x077
290 #define SVM_EXIT_HLT 0x078
291 #define SVM_EXIT_INVLPG 0x079
292 #define SVM_EXIT_INVLPGA 0x07a
293 #define SVM_EXIT_IOIO 0x07b
294 #define SVM_EXIT_MSR 0x07c
295 #define SVM_EXIT_TASK_SWITCH 0x07d
296 #define SVM_EXIT_FERR_FREEZE 0x07e
297 #define SVM_EXIT_SHUTDOWN 0x07f
298 #define SVM_EXIT_VMRUN 0x080
299 #define SVM_EXIT_VMMCALL 0x081
300 #define SVM_EXIT_VMLOAD 0x082
301 #define SVM_EXIT_VMSAVE 0x083
302 #define SVM_EXIT_STGI 0x084
303 #define SVM_EXIT_CLGI 0x085
304 #define SVM_EXIT_SKINIT 0x086
305 #define SVM_EXIT_RDTSCP 0x087
306 #define SVM_EXIT_ICEBP 0x088
307 #define SVM_EXIT_WBINVD 0x089
308 #define SVM_EXIT_MONITOR 0x08a
309 #define SVM_EXIT_MWAIT 0x08b
310 #define SVM_EXIT_MWAIT_COND 0x08c
311 #define SVM_EXIT_NPF 0x400
312
313 #define SVM_EXIT_ERR -1
314
315 #define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */
316
317 #define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
318 #define SVM_VMRUN ".byte 0x0f, 0x01, 0xd8"
319 #define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
320 #define SVM_CLGI ".byte 0x0f, 0x01, 0xdd"
321 #define SVM_STGI ".byte 0x0f, 0x01, 0xdc"
322 #define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"
323
324 #endif
325
326
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