1 #ifndef _ASM_X86_IRQ_VECTORS_H
2 #define _ASM_X86_IRQ_VECTORS_H
3
4 /*
5 * Linux IRQ vector layout.
6 *
7 * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can
8 * be defined by Linux. They are used as a jump table by the CPU when a
9 * given vector is triggered - by a CPU-external, CPU-internal or
10 * software-triggered event.
11 *
12 * Linux sets the kernel code address each entry jumps to early during
13 * bootup, and never changes them. This is the general layout of the
14 * IDT entries:
15 *
16 * Vectors 0 ... 31 : system traps and exceptions - hardcoded events
17 * Vectors 32 ... 127 : device interrupts
18 * Vector 128 : legacy int80 syscall interface
19 * Vectors 129 ... 237 : device interrupts
20 * Vectors 238 ... 255 : special interrupts
21 *
22 * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table.
23 *
24 * This file enumerates the exact layout of them:
25 */
26
27 #define NMI_VECTOR 0x02
28 #define MCE_VECTOR 0x12
29
30 /*
31 * IDT vectors usable for external interrupt sources start
32 * at 0x20:
33 */
34 #define FIRST_EXTERNAL_VECTOR 0x20
35
36 #ifdef CONFIG_X86_32
37 # define SYSCALL_VECTOR 0x80
38 # define IA32_SYSCALL_VECTOR 0x80
39 #else
40 # define IA32_SYSCALL_VECTOR 0x80
41 #endif
42
43 /*
44 * Reserve the lowest usable priority level 0x20 - 0x2f for triggering
45 * cleanup after irq migration.
46 */
47 #define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR
48
49 /*
50 * Vectors 0x30-0x3f are used for ISA interrupts.
51 */
52 #define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR + 0x10)
53
54 #define IRQ1_VECTOR (IRQ0_VECTOR + 1)
55 #define IRQ2_VECTOR (IRQ0_VECTOR + 2)
56 #define IRQ3_VECTOR (IRQ0_VECTOR + 3)
57 #define IRQ4_VECTOR (IRQ0_VECTOR + 4)
58 #define IRQ5_VECTOR (IRQ0_VECTOR + 5)
59 #define IRQ6_VECTOR (IRQ0_VECTOR + 6)
60 #define IRQ7_VECTOR (IRQ0_VECTOR + 7)
61 #define IRQ8_VECTOR (IRQ0_VECTOR + 8)
62 #define IRQ9_VECTOR (IRQ0_VECTOR + 9)
63 #define IRQ10_VECTOR (IRQ0_VECTOR + 10)
64 #define IRQ11_VECTOR (IRQ0_VECTOR + 11)
65 #define IRQ12_VECTOR (IRQ0_VECTOR + 12)
66 #define IRQ13_VECTOR (IRQ0_VECTOR + 13)
67 #define IRQ14_VECTOR (IRQ0_VECTOR + 14)
68 #define IRQ15_VECTOR (IRQ0_VECTOR + 15)
69
70 /*
71 * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
72 *
73 * some of the following vectors are 'rare', they are merged
74 * into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
75 * TLB, reschedule and local APIC vectors are performance-critical.
76 */
77
78 #define SPURIOUS_APIC_VECTOR 0xff
79 /*
80 * Sanity check
81 */
82 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
83 # error SPURIOUS_APIC_VECTOR definition error
84 #endif
85
86 #define ERROR_APIC_VECTOR 0xfe
87 #define RESCHEDULE_VECTOR 0xfd
88 #define CALL_FUNCTION_VECTOR 0xfc
89 #define CALL_FUNCTION_SINGLE_VECTOR 0xfb
90 #define THERMAL_APIC_VECTOR 0xfa
91 #define THRESHOLD_APIC_VECTOR 0xf9
92 #define REBOOT_VECTOR 0xf8
93
94 /* f0-f7 used for spreading out TLB flushes: */
95 #define INVALIDATE_TLB_VECTOR_END 0xf7
96 #define INVALIDATE_TLB_VECTOR_START 0xf0
97 #define NUM_INVALIDATE_TLB_VECTORS 8
98
99 /*
100 * Local APIC timer IRQ vector is on a different priority level,
101 * to work around the 'lost local interrupt if more than 2 IRQ
102 * sources per level' errata.
103 */
104 #define LOCAL_TIMER_VECTOR 0xef
105
106 /*
107 * Generic system vector for platform specific use
108 */
109 #define GENERIC_INTERRUPT_VECTOR 0xed
110
111 /*
112 * Performance monitoring pending work vector:
113 */
114 #define LOCAL_PENDING_VECTOR 0xec
115
116 #define UV_BAU_MESSAGE 0xec
117
118 /*
119 * Self IPI vector for machine checks
120 */
121 #define MCE_SELF_VECTOR 0xeb
122
123 /*
124 * First APIC vector available to drivers: (vectors 0x30-0xee) we
125 * start at 0x31(0x41) to spread out vectors evenly between priority
126 * levels. (0x80 is the syscall vector)
127 */
128 #define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2)
129
130 #define NR_VECTORS 256
131
132 #define FPU_IRQ 13
133
134 #define FIRST_VM86_IRQ 3
135 #define LAST_VM86_IRQ 15
136
137 #ifndef __ASSEMBLY__
138 static inline int invalid_vm86_irq(int irq)
139 {
140 return irq < FIRST_VM86_IRQ || irq > LAST_VM86_IRQ;
141 }
142 #endif
143
144 /*
145 * Size the maximum number of interrupts.
146 *
147 * If the irq_desc[] array has a sparse layout, we can size things
148 * generously - it scales up linearly with the maximum number of CPUs,
149 * and the maximum number of IO-APICs, whichever is higher.
150 *
151 * In other cases we size more conservatively, to not create too large
152 * static arrays.
153 */
154
155 #define NR_IRQS_LEGACY 16
156
157 #define CPU_VECTOR_LIMIT ( 8 * NR_CPUS )
158 #define IO_APIC_VECTOR_LIMIT ( 32 * MAX_IO_APICS )
159
160 #ifdef CONFIG_X86_IO_APIC
161 # ifdef CONFIG_SPARSE_IRQ
162 # define NR_IRQS \
163 (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \
164 (NR_VECTORS + CPU_VECTOR_LIMIT) : \
165 (NR_VECTORS + IO_APIC_VECTOR_LIMIT))
166 # else
167 # if NR_CPUS < MAX_IO_APICS
168 # define NR_IRQS (NR_VECTORS + 4*CPU_VECTOR_LIMIT)
169 # else
170 # define NR_IRQS (NR_VECTORS + IO_APIC_VECTOR_LIMIT)
171 # endif
172 # endif
173 #else /* !CONFIG_X86_IO_APIC: */
174 # define NR_IRQS NR_IRQS_LEGACY
175 #endif
176
177 #endif /* _ASM_X86_IRQ_VECTORS_H */
178
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