1 /**
2 * @file nmi_int.c
3 *
4 * @remark Copyright 2002 OProfile authors
5 * @remark Read the file COPYING
6 *
7 * @author John Levon <levon@movementarian.org>
8 */
9
10 #include <linux/init.h>
11 #include <linux/notifier.h>
12 #include <linux/smp.h>
13 #include <linux/oprofile.h>
14 #include <linux/sysdev.h>
15 #include <linux/slab.h>
16 #include <asm/nmi.h>
17 #include <asm/msr.h>
18 #include <asm/apic.h>
19
20 #include "op_counter.h"
21 #include "op_x86_model.h"
22
23 static struct op_x86_model_spec const * model;
24 static struct op_msrs cpu_msrs[NR_CPUS];
25 static unsigned long saved_lvtpc[NR_CPUS];
26
27 static int nmi_start(void);
28 static void nmi_stop(void);
29
30 /* 0 == registered but off, 1 == registered and on */
31 static int nmi_enabled = 0;
32
33 #ifdef CONFIG_PM
34
35 static int nmi_suspend(struct sys_device *dev, u32 state)
36 {
37 if (nmi_enabled == 1)
38 nmi_stop();
39 return 0;
40 }
41
42
43 static int nmi_resume(struct sys_device *dev)
44 {
45 if (nmi_enabled == 1)
46 nmi_start();
47 return 0;
48 }
49
50
51 static struct sysdev_class oprofile_sysclass = {
52 set_kset_name("oprofile"),
53 .resume = nmi_resume,
54 .suspend = nmi_suspend,
55 };
56
57
58 static struct sys_device device_oprofile = {
59 .id = 0,
60 .cls = &oprofile_sysclass,
61 };
62
63
64 static int __init init_driverfs(void)
65 {
66 int error;
67 if (!(error = sysdev_class_register(&oprofile_sysclass)))
68 error = sysdev_register(&device_oprofile);
69 return error;
70 }
71
72
73 static void exit_driverfs(void)
74 {
75 sysdev_unregister(&device_oprofile);
76 sysdev_class_unregister(&oprofile_sysclass);
77 }
78
79 #else
80 #define init_driverfs() do { } while (0)
81 #define exit_driverfs() do { } while (0)
82 #endif /* CONFIG_PM */
83
84
85 static int nmi_callback(struct pt_regs * regs, int cpu)
86 {
87 return model->check_ctrs(regs, &cpu_msrs[cpu]);
88 }
89
90
91 static void nmi_cpu_save_registers(struct op_msrs * msrs)
92 {
93 unsigned int const nr_ctrs = model->num_counters;
94 unsigned int const nr_ctrls = model->num_controls;
95 struct op_msr * counters = msrs->counters;
96 struct op_msr * controls = msrs->controls;
97 unsigned int i;
98
99 for (i = 0; i < nr_ctrs; ++i) {
100 rdmsr(counters[i].addr,
101 counters[i].saved.low,
102 counters[i].saved.high);
103 }
104
105 for (i = 0; i < nr_ctrls; ++i) {
106 rdmsr(controls[i].addr,
107 controls[i].saved.low,
108 controls[i].saved.high);
109 }
110 }
111
112
113 static void nmi_save_registers(void * dummy)
114 {
115 int cpu = smp_processor_id();
116 struct op_msrs * msrs = &cpu_msrs[cpu];
117 model->fill_in_addresses(msrs);
118 nmi_cpu_save_registers(msrs);
119 }
120
121
122 static void free_msrs(void)
123 {
124 int i;
125 for (i = 0; i < NR_CPUS; ++i) {
126 kfree(cpu_msrs[i].counters);
127 cpu_msrs[i].counters = NULL;
128 kfree(cpu_msrs[i].controls);
129 cpu_msrs[i].controls = NULL;
130 }
131 }
132
133
134 static int allocate_msrs(void)
135 {
136 int success = 1;
137 size_t controls_size = sizeof(struct op_msr) * model->num_controls;
138 size_t counters_size = sizeof(struct op_msr) * model->num_counters;
139
140 int i;
141 for (i = 0; i < NR_CPUS; ++i) {
142 if (!cpu_online(i))
143 continue;
144
145 cpu_msrs[i].counters = kmalloc(counters_size, GFP_KERNEL);
146 if (!cpu_msrs[i].counters) {
147 success = 0;
148 break;
149 }
150 cpu_msrs[i].controls = kmalloc(controls_size, GFP_KERNEL);
151 if (!cpu_msrs[i].controls) {
152 success = 0;
153 break;
154 }
155 }
156
157 if (!success)
158 free_msrs();
159
160 return success;
161 }
162
163
164 static void nmi_cpu_setup(void * dummy)
165 {
166 int cpu = smp_processor_id();
167 struct op_msrs * msrs = &cpu_msrs[cpu];
168 spin_lock(&oprofilefs_lock);
169 model->setup_ctrs(msrs);
170 spin_unlock(&oprofilefs_lock);
171 saved_lvtpc[cpu] = apic_read(APIC_LVTPC);
172 apic_write(APIC_LVTPC, APIC_DM_NMI);
173 }
174
175
176 static int nmi_setup(void)
177 {
178 if (!allocate_msrs())
179 return -ENOMEM;
180
181 /* We walk a thin line between law and rape here.
182 * We need to be careful to install our NMI handler
183 * without actually triggering any NMIs as this will
184 * break the core code horrifically.
185 */
186 if (reserve_lapic_nmi() < 0) {
187 free_msrs();
188 return -EBUSY;
189 }
190 /* We need to serialize save and setup for HT because the subset
191 * of msrs are distinct for save and setup operations
192 */
193 on_each_cpu(nmi_save_registers, NULL, 0, 1);
194 on_each_cpu(nmi_cpu_setup, NULL, 0, 1);
195 set_nmi_callback(nmi_callback);
196 nmi_enabled = 1;
197 return 0;
198 }
199
200
201 static void nmi_restore_registers(struct op_msrs * msrs)
202 {
203 unsigned int const nr_ctrs = model->num_counters;
204 unsigned int const nr_ctrls = model->num_controls;
205 struct op_msr * counters = msrs->counters;
206 struct op_msr * controls = msrs->controls;
207 unsigned int i;
208
209 for (i = 0; i < nr_ctrls; ++i) {
210 wrmsr(controls[i].addr,
211 controls[i].saved.low,
212 controls[i].saved.high);
213 }
214
215 for (i = 0; i < nr_ctrs; ++i) {
216 wrmsr(counters[i].addr,
217 counters[i].saved.low,
218 counters[i].saved.high);
219 }
220 }
221
222
223 static void nmi_cpu_shutdown(void * dummy)
224 {
225 unsigned int v;
226 int cpu = smp_processor_id();
227 struct op_msrs * msrs = &cpu_msrs[cpu];
228
229 /* restoring APIC_LVTPC can trigger an apic error because the delivery
230 * mode and vector nr combination can be illegal. That's by design: on
231 * power on apic lvt contain a zero vector nr which are legal only for
232 * NMI delivery mode. So inhibit apic err before restoring lvtpc
233 */
234 v = apic_read(APIC_LVTERR);
235 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
236 apic_write(APIC_LVTPC, saved_lvtpc[cpu]);
237 apic_write(APIC_LVTERR, v);
238 nmi_restore_registers(msrs);
239 }
240
241
242 static void nmi_shutdown(void)
243 {
244 nmi_enabled = 0;
245 on_each_cpu(nmi_cpu_shutdown, NULL, 0, 1);
246 unset_nmi_callback();
247 release_lapic_nmi();
248 free_msrs();
249 }
250
251
252 static void nmi_cpu_start(void * dummy)
253 {
254 struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()];
255 model->start(msrs);
256 }
257
258
259 static int nmi_start(void)
260 {
261 on_each_cpu(nmi_cpu_start, NULL, 0, 1);
262 return 0;
263 }
264
265
266 static void nmi_cpu_stop(void * dummy)
267 {
268 struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()];
269 model->stop(msrs);
270 }
271
272
273 static void nmi_stop(void)
274 {
275 on_each_cpu(nmi_cpu_stop, NULL, 0, 1);
276 }
277
278
279 struct op_counter_config counter_config[OP_MAX_COUNTER];
280
281 static int nmi_create_files(struct super_block * sb, struct dentry * root)
282 {
283 unsigned int i;
284
285 for (i = 0; i < model->num_counters; ++i) {
286 struct dentry * dir;
287 char buf[2];
288
289 snprintf(buf, 2, "%d", i);
290 dir = oprofilefs_mkdir(sb, root, buf);
291 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
292 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
293 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
294 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
295 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
296 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
297 }
298
299 return 0;
300 }
301
302
303 static int __init p4_init(char ** cpu_type)
304 {
305 __u8 cpu_model = boot_cpu_data.x86_model;
306
307 if (cpu_model > 4)
308 return 0;
309
310 #ifndef CONFIG_SMP
311 *cpu_type = "i386/p4";
312 model = &op_p4_spec;
313 return 1;
314 #else
315 switch (smp_num_siblings) {
316 case 1:
317 *cpu_type = "i386/p4";
318 model = &op_p4_spec;
319 return 1;
320
321 case 2:
322 *cpu_type = "i386/p4-ht";
323 model = &op_p4_ht2_spec;
324 return 1;
325 }
326 #endif
327
328 printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
329 printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
330 return 0;
331 }
332
333
334 static int __init ppro_init(char ** cpu_type)
335 {
336 __u8 cpu_model = boot_cpu_data.x86_model;
337
338 if (cpu_model > 0xd)
339 return 0;
340
341 if (cpu_model == 9) {
342 *cpu_type = "i386/p6_mobile";
343 } else if (cpu_model > 5) {
344 *cpu_type = "i386/piii";
345 } else if (cpu_model > 2) {
346 *cpu_type = "i386/pii";
347 } else {
348 *cpu_type = "i386/ppro";
349 }
350
351 model = &op_ppro_spec;
352 return 1;
353 }
354
355 /* in order to get driverfs right */
356 static int using_nmi;
357
358 int __init nmi_init(struct oprofile_operations *ops)
359 {
360 __u8 vendor = boot_cpu_data.x86_vendor;
361 __u8 family = boot_cpu_data.x86;
362 char *cpu_type;
363
364 if (!cpu_has_apic)
365 return -ENODEV;
366
367 switch (vendor) {
368 case X86_VENDOR_AMD:
369 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
370
371 switch (family) {
372 default:
373 return -ENODEV;
374 case 6:
375 model = &op_athlon_spec;
376 cpu_type = "i386/athlon";
377 break;
378 case 0xf:
379 model = &op_athlon_spec;
380 /* Actually it could be i386/hammer too, but give
381 user space an consistent name. */
382 cpu_type = "x86-64/hammer";
383 break;
384 }
385 break;
386
387 case X86_VENDOR_INTEL:
388 switch (family) {
389 /* Pentium IV */
390 case 0xf:
391 if (!p4_init(&cpu_type))
392 return -ENODEV;
393 break;
394
395 /* A P6-class processor */
396 case 6:
397 if (!ppro_init(&cpu_type))
398 return -ENODEV;
399 break;
400
401 default:
402 return -ENODEV;
403 }
404 break;
405
406 default:
407 return -ENODEV;
408 }
409
410 init_driverfs();
411 using_nmi = 1;
412 ops->create_files = nmi_create_files;
413 ops->setup = nmi_setup;
414 ops->shutdown = nmi_shutdown;
415 ops->start = nmi_start;
416 ops->stop = nmi_stop;
417 ops->cpu_type = cpu_type;
418 printk(KERN_INFO "oprofile: using NMI interrupt.\n");
419 return 0;
420 }
421
422
423 void nmi_exit(void)
424 {
425 if (using_nmi)
426 exit_driverfs();
427 }
428
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