1 #include <linux/config.h>
2 #include <linux/errno.h>
3 #include <linux/signal.h>
4 #include <linux/sched.h>
5 #include <linux/ioport.h>
6 #include <linux/interrupt.h>
7 #include <linux/slab.h>
8 #include <linux/random.h>
9 #include <linux/smp_lock.h>
10 #include <linux/init.h>
11 #include <linux/kernel_stat.h>
12 #include <linux/sysdev.h>
13 #include <linux/bitops.h>
14
15 #include <asm/8253pit.h>
16 #include <asm/atomic.h>
17 #include <asm/system.h>
18 #include <asm/io.h>
19 #include <asm/irq.h>
20 #include <asm/timer.h>
21 #include <asm/pgtable.h>
22 #include <asm/delay.h>
23 #include <asm/desc.h>
24 #include <asm/apic.h>
25 #include <asm/arch_hooks.h>
26 #include <asm/i8259.h>
27
28 #include <linux/irq.h>
29
30 #include <io_ports.h>
31
32 /*
33 * This is the 'legacy' 8259A Programmable Interrupt Controller,
34 * present in the majority of PC/AT boxes.
35 * plus some generic x86 specific things if generic specifics makes
36 * any sense at all.
37 * this file should become arch/i386/kernel/irq.c when the old irq.c
38 * moves to arch independent land
39 */
40
41 DEFINE_SPINLOCK(i8259A_lock);
42
43 static void end_8259A_irq (unsigned int irq)
44 {
45 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
46 irq_desc[irq].action)
47 enable_8259A_irq(irq);
48 }
49
50 #define shutdown_8259A_irq disable_8259A_irq
51
52 void mask_and_ack_8259A(unsigned int);
53
54 unsigned int startup_8259A_irq(unsigned int irq)
55 {
56 enable_8259A_irq(irq);
57 return 0; /* never anything pending */
58 }
59
60 static struct hw_interrupt_type i8259A_irq_type = {
61 "XT-PIC",
62 startup_8259A_irq,
63 shutdown_8259A_irq,
64 enable_8259A_irq,
65 disable_8259A_irq,
66 mask_and_ack_8259A,
67 end_8259A_irq,
68 NULL
69 };
70
71 /*
72 * 8259A PIC functions to handle ISA devices:
73 */
74
75 /*
76 * This contains the irq mask for both 8259A irq controllers,
77 */
78 unsigned int cached_irq_mask = 0xffff;
79
80 /*
81 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
82 * boards the timer interrupt is not really connected to any IO-APIC pin,
83 * it's fed to the master 8259A's IR0 line only.
84 *
85 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
86 * this 'mixed mode' IRQ handling costs nothing because it's only used
87 * at IRQ setup time.
88 */
89 unsigned long io_apic_irqs;
90
91 void disable_8259A_irq(unsigned int irq)
92 {
93 unsigned int mask = 1 << irq;
94 unsigned long flags;
95
96 spin_lock_irqsave(&i8259A_lock, flags);
97 cached_irq_mask |= mask;
98 if (irq & 8)
99 outb(cached_slave_mask, PIC_SLAVE_IMR);
100 else
101 outb(cached_master_mask, PIC_MASTER_IMR);
102 spin_unlock_irqrestore(&i8259A_lock, flags);
103 }
104
105 void enable_8259A_irq(unsigned int irq)
106 {
107 unsigned int mask = ~(1 << irq);
108 unsigned long flags;
109
110 spin_lock_irqsave(&i8259A_lock, flags);
111 cached_irq_mask &= mask;
112 if (irq & 8)
113 outb(cached_slave_mask, PIC_SLAVE_IMR);
114 else
115 outb(cached_master_mask, PIC_MASTER_IMR);
116 spin_unlock_irqrestore(&i8259A_lock, flags);
117 }
118
119 int i8259A_irq_pending(unsigned int irq)
120 {
121 unsigned int mask = 1<<irq;
122 unsigned long flags;
123 int ret;
124
125 spin_lock_irqsave(&i8259A_lock, flags);
126 if (irq < 8)
127 ret = inb(PIC_MASTER_CMD) & mask;
128 else
129 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
130 spin_unlock_irqrestore(&i8259A_lock, flags);
131
132 return ret;
133 }
134
135 void make_8259A_irq(unsigned int irq)
136 {
137 disable_irq_nosync(irq);
138 io_apic_irqs &= ~(1<<irq);
139 irq_desc[irq].handler = &i8259A_irq_type;
140 enable_irq(irq);
141 }
142
143 /*
144 * This function assumes to be called rarely. Switching between
145 * 8259A registers is slow.
146 * This has to be protected by the irq controller spinlock
147 * before being called.
148 */
149 static inline int i8259A_irq_real(unsigned int irq)
150 {
151 int value;
152 int irqmask = 1<<irq;
153
154 if (irq < 8) {
155 outb(0x0B,PIC_MASTER_CMD); /* ISR register */
156 value = inb(PIC_MASTER_CMD) & irqmask;
157 outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
158 return value;
159 }
160 outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
161 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
162 outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
163 return value;
164 }
165
166 /*
167 * Careful! The 8259A is a fragile beast, it pretty
168 * much _has_ to be done exactly like this (mask it
169 * first, _then_ send the EOI, and the order of EOI
170 * to the two 8259s is important!
171 */
172 void mask_and_ack_8259A(unsigned int irq)
173 {
174 unsigned int irqmask = 1 << irq;
175 unsigned long flags;
176
177 spin_lock_irqsave(&i8259A_lock, flags);
178 /*
179 * Lightweight spurious IRQ detection. We do not want
180 * to overdo spurious IRQ handling - it's usually a sign
181 * of hardware problems, so we only do the checks we can
182 * do without slowing down good hardware unnecesserily.
183 *
184 * Note that IRQ7 and IRQ15 (the two spurious IRQs
185 * usually resulting from the 8259A-1|2 PICs) occur
186 * even if the IRQ is masked in the 8259A. Thus we
187 * can check spurious 8259A IRQs without doing the
188 * quite slow i8259A_irq_real() call for every IRQ.
189 * This does not cover 100% of spurious interrupts,
190 * but should be enough to warn the user that there
191 * is something bad going on ...
192 */
193 if (cached_irq_mask & irqmask)
194 goto spurious_8259A_irq;
195 cached_irq_mask |= irqmask;
196
197 handle_real_irq:
198 if (irq & 8) {
199 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
200 outb(cached_slave_mask, PIC_SLAVE_IMR);
201 outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
202 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
203 } else {
204 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
205 outb(cached_master_mask, PIC_MASTER_IMR);
206 outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */
207 }
208 spin_unlock_irqrestore(&i8259A_lock, flags);
209 return;
210
211 spurious_8259A_irq:
212 /*
213 * this is the slow path - should happen rarely.
214 */
215 if (i8259A_irq_real(irq))
216 /*
217 * oops, the IRQ _is_ in service according to the
218 * 8259A - not spurious, go handle it.
219 */
220 goto handle_real_irq;
221
222 {
223 static int spurious_irq_mask;
224 /*
225 * At this point we can be sure the IRQ is spurious,
226 * lets ACK and report it. [once per IRQ]
227 */
228 if (!(spurious_irq_mask & irqmask)) {
229 printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
230 spurious_irq_mask |= irqmask;
231 }
232 atomic_inc(&irq_err_count);
233 /*
234 * Theoretically we do not have to handle this IRQ,
235 * but in Linux this does not cause problems and is
236 * simpler for us.
237 */
238 goto handle_real_irq;
239 }
240 }
241
242 static char irq_trigger[2];
243 /**
244 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
245 */
246 static void restore_ELCR(char *trigger)
247 {
248 outb(trigger[0], 0x4d0);
249 outb(trigger[1], 0x4d1);
250 }
251
252 static void save_ELCR(char *trigger)
253 {
254 /* IRQ 0,1,2,8,13 are marked as reserved */
255 trigger[0] = inb(0x4d0) & 0xF8;
256 trigger[1] = inb(0x4d1) & 0xDE;
257 }
258
259 static int i8259A_resume(struct sys_device *dev)
260 {
261 init_8259A(0);
262 restore_ELCR(irq_trigger);
263 return 0;
264 }
265
266 static int i8259A_suspend(struct sys_device *dev, u32 state)
267 {
268 save_ELCR(irq_trigger);
269 return 0;
270 }
271
272 static struct sysdev_class i8259_sysdev_class = {
273 set_kset_name("i8259"),
274 .suspend = i8259A_suspend,
275 .resume = i8259A_resume,
276 };
277
278 static struct sys_device device_i8259A = {
279 .id = 0,
280 .cls = &i8259_sysdev_class,
281 };
282
283 static int __init i8259A_init_sysfs(void)
284 {
285 int error = sysdev_class_register(&i8259_sysdev_class);
286 if (!error)
287 error = sysdev_register(&device_i8259A);
288 return error;
289 }
290
291 device_initcall(i8259A_init_sysfs);
292
293 void init_8259A(int auto_eoi)
294 {
295 unsigned long flags;
296
297 spin_lock_irqsave(&i8259A_lock, flags);
298
299 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
300 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
301
302 /*
303 * outb_p - this has to work on a wide range of PC hardware.
304 */
305 outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
306 outb_p(0x20 + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
307 outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
308 if (auto_eoi) /* master does Auto EOI */
309 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
310 else /* master expects normal EOI */
311 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
312
313 outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
314 outb_p(0x20 + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
315 outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
316 outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
317 if (auto_eoi)
318 /*
319 * in AEOI mode we just have to mask the interrupt
320 * when acking.
321 */
322 i8259A_irq_type.ack = disable_8259A_irq;
323 else
324 i8259A_irq_type.ack = mask_and_ack_8259A;
325
326 udelay(100); /* wait for 8259A to initialize */
327
328 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
329 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
330
331 spin_unlock_irqrestore(&i8259A_lock, flags);
332 }
333
334 /*
335 * Note that on a 486, we don't want to do a SIGFPE on an irq13
336 * as the irq is unreliable, and exception 16 works correctly
337 * (ie as explained in the intel literature). On a 386, you
338 * can't use exception 16 due to bad IBM design, so we have to
339 * rely on the less exact irq13.
340 *
341 * Careful.. Not only is IRQ13 unreliable, but it is also
342 * leads to races. IBM designers who came up with it should
343 * be shot.
344 */
345
346
347 static irqreturn_t math_error_irq(int cpl, void *dev_id, struct pt_regs *regs)
348 {
349 extern void math_error(void __user *);
350 outb(0,0xF0);
351 if (ignore_fpu_irq || !boot_cpu_data.hard_math)
352 return IRQ_NONE;
353 math_error((void __user *)regs->eip);
354 return IRQ_HANDLED;
355 }
356
357 /*
358 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
359 * so allow interrupt sharing.
360 */
361 static struct irqaction fpu_irq = { math_error_irq, 0, CPU_MASK_NONE, "fpu", NULL, NULL };
362
363 void __init init_ISA_irqs (void)
364 {
365 int i;
366
367 #ifdef CONFIG_X86_LOCAL_APIC
368 init_bsp_APIC();
369 #endif
370 init_8259A(0);
371
372 for (i = 0; i < NR_IRQS; i++) {
373 irq_desc[i].status = IRQ_DISABLED;
374 irq_desc[i].action = NULL;
375 irq_desc[i].depth = 1;
376
377 if (i < 16) {
378 /*
379 * 16 old-style INTA-cycle interrupts:
380 */
381 irq_desc[i].handler = &i8259A_irq_type;
382 } else {
383 /*
384 * 'high' PCI IRQs filled in on demand
385 */
386 irq_desc[i].handler = &no_irq_type;
387 }
388 }
389 }
390
391 void __init init_IRQ(void)
392 {
393 int i;
394
395 /* all the set up before the call gates are initialised */
396 pre_intr_init_hook();
397
398 /*
399 * Cover the whole vector space, no vector can escape
400 * us. (some of these will be overridden and become
401 * 'special' SMP interrupts)
402 */
403 for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
404 int vector = FIRST_EXTERNAL_VECTOR + i;
405 if (i >= NR_IRQS)
406 break;
407 if (vector != SYSCALL_VECTOR)
408 set_intr_gate(vector, interrupt[i]);
409 }
410
411 /* setup after call gates are initialised (usually add in
412 * the architecture specific gates)
413 */
414 intr_init_hook();
415
416 /*
417 * Set the clock to HZ Hz, we already have a valid
418 * vector now:
419 */
420 setup_pit_timer();
421
422 /*
423 * External FPU? Set up irq13 if so, for
424 * original braindamaged IBM FERR coupling.
425 */
426 if (boot_cpu_data.hard_math && !cpu_has_fpu)
427 setup_irq(FPU_IRQ, &fpu_irq);
428
429 irq_ctx_init(smp_processor_id());
430 }
431
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